CN102044157B

CN102044157B - Multi-lane overspeed detecting system based on field programmable gate array (FPGA)

Info

Publication number: CN102044157B
Application number: CN200910218415A
Authority: CN
Inventors: 史忠科; 贺莹; 王闯
Original assignee: Xian Feisida Automation Engineering Co Ltd
Current assignee: Xian Feisida Automation Engineering Co Ltd
Priority date: 2009-10-20
Filing date: 2009-10-20
Publication date: 2012-09-26
Anticipated expiration: 2029-10-20
Also published as: CN102044157A

Abstract

The invention relates to a multi-lane overspeed detecting system based on a field programmable gate array (FPGA), belonging to an industrial measurement and control technology and a video and image processing technology. In the multi-lane overspeed detecting system, an FPGA chip is utilized as an acquiring and processing unit of two paths of digital images to realize signal detection and remote image transmission for violated overspeed vehicles. The signal sources of the system are two paths of charge coupled device (CCD) analog video signals which are converted into digital video signals after entering an analog-to-digital (A/D) converter. The multi-lane overspeed detecting system provided by the invention is characterized in that the FPGA operates a detecting algorithm for detecting whether a vehicle passes; when the first path of video signal detects that the vehicle passes, the time when the vehicle enters a monitored area is obtained; next, at the moment when a second path video end detects that the vehicle passes, the time when the vehicle leaves the monitored area is obtained; and according to the time difference, whether the vehicle is overspeed and violated is judged, the picture of the overspeed and violated vehicle is shot, and relevant violated information is stored.

Description

Multilane overspeed detection system based on FPGA

Technical field

The present invention relates to a kind of multilane overspeed detection system based on FPGA; Belong to industrial measurement and control technology, video image processing technology; Be to utilize collection and the processing unit of fpga chip, realize the input and the image remote of the vehicle that exeeds the regulation speed are sent as the two-way digital picture.

Background technology

Traffic safety is the eternal research topic of traffic engineering, always relevant person's great attention extremely both at home and abroad.The communication of China has obtained significant progress in recent years; Meanwhile, the vehicles also increase with unprecedented speed, thereby cause traffic hazard to take place more and more continually; This not only endangers the people's the security of the lives and property, and makes country suffer unnecessary economic loss; The factor that influences traffic safety is a lot, and the vehicle of wherein driving over the speed limit is one of main reason that causes traffic hazard.Therefore coming the travel speed of limiting vehicle through overspeed detection is the effective means that reduces traffic hazard, safeguards traffic safety.

Overspeed detection technology commonly used both at home and abroad at present has following several kinds:

1. ground induction coil tests the speed, and this mode judges whether to exceed the speed limit according to the speed of vehicle through parallel coil, needs to the underground inductive coil of burying underground, and is great in constructing amount, in case change then the circle of need heavily sunkening cord on the road surface.Because of working environment is open-air, for guaranteeing the operational reliability of system, considered is prevented operating characteristic such as travel fatigue, rain and snow, high temperature resistance, anti-severe cold when design, reaches the automatically actuated function of faults such as power failure, deadlock; Thereby this method realizes complicated, not easy to operate;

2. radar hypervelocity surveillance, the purpose of promptly utilizing radar signal to realize keeping watch on over-speed vehicles can be seen the big shot of area covered by the radar speed-detecting network on a lot of highways; Yet, beyond area covered by the radar speed-detecting network, can't keep watch on over-speed vehicles; And radar velocity measurement can't directly obtain the license plate number of over-speed vehicles; Under the bad situation of weather, the error of radar velocity measurement reaches 20% sometimes; Be subject to weather effect, measuring accuracy is low;

3. infrared ray and laser detection, this method is the very high mode of a kind of accuracy of detection in theory, but faces multiple tracks road, crossing, many vehicles and multirow people's situation, the efficient of point measurement can't satisfy the supervision requirement.Laser detection can cause great injury to human eye simultaneously;

4. based on the CCD hypervelocity surveillance of Video Detection, video detection system is to have or not the vehicle of driving over the speed limit through the detection of video image is judged; Because system need be installed on the road of highway or appointment or on moving vehicle, working environment be open-air, and the crossing computing machine adopts industrial computer, and the technical grade standard design is pressed in signal, all designs of image delivering system fully, so invest bigger; In addition, this system is when actual motion, and stability is very good and cause Practical Performance not very good;

5. based on DSP+FPGA Video Detection scheme, the DSP+FPGA Video Detection scheme of now a lot of reported in literature all is to replace industrial computer with DSP, realizes video acquisition management, image processing, hypervelocity judgement etc.; Owing to reasons such as image reads, storages, these system speeds can not satisfy the actual requirement of engineering.

Summary of the invention

For avoiding defectives such as the prior art real-time is poor, input is excessive; The present invention provides a kind of multilane overspeed detection system based on FPGA, is provided with to detect starting point and endpoint detection two analoglike video signal sources, and analog video signal is through video decoding chip output digital video signal; FPGA is by the storage space of self and expansion; Control is handled and managed to image, and the detection starting point in each track and terminal point all circulate as one according to two two field pictures basically, and the appointment surveyed area of first two field picture is compared with the second frame surveyed area; Make according to both difference sizes and the threshold value that in FPGA, is provided with and to have or not vehicle to pass through; The machines motor vehicle is sailed origin zone and the time of rolling the outrun away from into respectively, and when certain lane detection starting point had vehicle to pass through, recording picture and vehicle got into the time of surveillance zone; Detecting this lane detection terminal point then has or not vehicle to pass through; Registration of vehicle leaves the time that terminal point is kept watch in this track, and FPGA then stores or be sent to remote monitoring center with relevant violation information with speed, time etc. after the vehicles peccancy image compression according to the Origin And Destination distance and in judgements that exceed the speed limit of the interior running time of this distance if exceed the speed limit; If vehicle is hypervelocity not, carry out the next round circulation and cover visual posting field.

The technical solution adopted for the present invention to solve the technical problems: the multilane overspeed detection system based on FPGA is characterized in that testing process may further comprise the steps:

(a) in image, select the detection zone of zone, a track, when odd-numbered frame arrives, each pixel value in detection zone is sent into totalizer, pixel count is counted as vehicle pass-through, and accumulation result is temporary; When even frame arrives,, send into totalizer then with each the pixel value negate of its surveyed area; Even frame adds up when finishing, and according to accumulation result and pixel counts value, calculates the mean pixel difference FK of area-of-interest; Get 10 pixels with different points at non-detection zone according to the different stage of bright darkness, calculate average background subtraction value BK according to the accumulation result of these pixels in two frames; Confirm appropriate threshold T according to the application scenario of system, if satisfy | FK-BK|＞T, judge that then current time does not have vehicle and passes through;

(b) two cameras are erected at the two ends, speed trap territory of regular length; The at first camera work of surveillance zone porch; The described vehicle detecting algorithm of operating procedure (a); If detect vehicle and pass through, start then that software timer picks up counting and start working through the camera that SS switches to the speed trap outlet;

(c) when detecting vehicle once more at endpiece and pass through; The value of record timer this moment; And with guarantee marginal time that vehicle does not exceed the speed limit relatively, if clocking value less than the marginal time, then draws the conclusion of this overspeed of vehicle; The vehicles peccancy compression of images that take endpiece this moment, and be stored in the storage medium; Simultaneously, switching selection switch carries out the overspeed detection of next car to the camera work of porch once more.

The invention has the beneficial effects as follows: the characteristics of utilizing FPGA hardware logic computing massive parallelism; Simplicity of design is image processing algorithm efficiently; Realized vehicle pass-through information extraction, overcome the deficiency that adopts toroid winding to need excavated pavement, guaranteed that again real-time full frame rate detects image sequence; Simultaneously, system adopts the special image compression chip, makes memory data output unlikely excessive, has guaranteed the real-time of compression and the high resolving power of picture simultaneously.

Table 1: the present invention and prior art comparison sheet

	Radar surveillance system	The toroid winding surveillance	Video monitoring system	Native system
					Display video image	Can not	Can	Can	Can
Cost	High	High	High	Low

Power consumption	High	High	High	Low
					Excavated pavement	Do not need	Need	Do not need	Do not need
Video acquisition	Can not	Can	Can	Can
					The display driver interface	Do not have	Analog/digital	Analog/digital	Numeral
Error	Little	Generally	Generally	Little
					Stability	Good	Difference	Difference	Good

Below in conjunction with accompanying drawing and embodiment the present invention is further specified.

Description of drawings

Accompanying drawing 1 is the multilane overspeed detection system architecture schematic diagram that the present invention is based on FPGA;

Accompanying drawing 2 is the multilane overspeed detection system embodiment schematic diagrams that the present invention is based on FPGA;

Accompanying drawing 3 is that the multilane overspeed detection system algorithm that the present invention is based on FPGA is handled block diagram.

Embodiment

In the concrete implementation procedure of native system, the EP1C12 chip in the Cyclone Series FPGA of FPGA employing U.S. altera corp.This chip closeness reaches 12060 LE unit, and (each LE comprises a LUT; Trigger and interrelated logic; Being the basic structure that chip is realized logic, also is the leading indicator of FPGA comprehensive performance evaluation), can satisfy the needs of image processing algorithm and analyzing logic control fully; 169 users can satisfy a plurality of chip connection requests that system realizes IMAQ and storage with the I/O port; Video acquisition unit adopts CCD, and it can come in the image scene collection and give A/D conversion chip to be for further processing; The A/D chip adopts the 7113H chip of PHILIPS company, and the 7113H chip has 4 analog channels, and through the picture signal of acquisition time 4 tunnel, timesharing is handled, and can select the translative mode of 7113H through programming, through I ²The C bus is programmed, and accomplishes the initial work of 7113H, and the output format of signal is also by I ²The C bus is controlled, and adopts 4: 2: 2 forms of CCIR601.A monolithic IPEG2000 coding chip ADV202 that is used for food and the exquisite compression of images of high bandwidth that the special image compression chip adopts U.S. AD company to release.

With reference to Fig. 2, whether behind the system initialization, at first detecting at surveillance zone inlet has vehicle to pass through, when detect vehicle through the time, then switch to the work of surveillance zone endpiece camera, and start the FPGA software timer through change-over switch.At this moment, endpiece digital video signal one tunnel carries out vehicle passing detection, and one the tunnel gets into image compression chip; When detect once more at endpiece vehicle through the time, relatively timer and the size of marginal time, if the former is big, then change-over switch switches to inlet end and restarts to judge while timer zero clearing; If the latter is big, then will passes through the over-speed vehicles image of image compression chip and send into the IDE storer.Then get into and detect circulation next time.

Claims

1. multilane overspeed detection system based on FPGA; Signal source is the two-way analog video signal, and analog video signal gets into A/D converter and is transformed to digital video signal, the detection algorithm whether the FPGA operation has vehicle to pass through; When first via video signal detection when vehicle passes through; Obtain the time that vehicle gets into surveillance zone, then detect the moment that vehicle passes through, obtain the time that vehicle leaves surveillance zone in the second tunnel video end; Judge whether overspeed violation and absorb the picture of overspeed violation vehicle and preserve relevant violation information of vehicle by the mistiming, it is characterized in that testing process may further comprise the steps: