CN102054818B - Interconnection structure and manufacture method thereof - Google Patents
Interconnection structure and manufacture method thereof Download PDFInfo
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- CN102054818B CN102054818B CN2009101985796A CN200910198579A CN102054818B CN 102054818 B CN102054818 B CN 102054818B CN 2009101985796 A CN2009101985796 A CN 2009101985796A CN 200910198579 A CN200910198579 A CN 200910198579A CN 102054818 B CN102054818 B CN 102054818B
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Abstract
The present invention provides an interconnection structure and manufacture method thereof, wherein the interconnection structure comprises: a semiconductor substrate; at least three metal wiring layers located on the semiconductor substrate; an insulation medium layer location among the metal wiring layers; a conductive plug penetrating the thickness of the insulation medium layer and communicating the metal wiring layers, wherein the combination of the metal wiring layers and a cross-section of the conductive plug forms an annular distribution. The interconnection structure of the present invention is suitable for interconnecting at a high-speed, increasing the signal integrity of the interconnection structure, and reducing interferences between signals.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to interconnection structure and preparation method thereof.
Background technology
The multilayer interconnection technology had become large scale integrated circuit and ULSI preparation technology's important component part already.The ULSI of current high performance has had nearly 7～10 layers metal connecting line.Therefore, seek the interconnect materials of low resistivity and become a big research direction of deep-submicron and nano-device than the insulating material of low-k.
Multilayer interconnect structure includes the multiple layer metal line usually, interconnects through the plug structure in the insulating material.The technology that forms connector is the technology with metal material filling vias or groove, and for example application number is the method for the formation plug structure that provided of the one Chinese patent application file of CN98118290.
In the back segment manufacturing process of semiconductor device, carry out metal interconnect structure Wiring technique such as Fig. 1 to shown in Figure 4.With reference to figure 1, semi-conductive substrate 100 is provided, said Semiconductor substrate 100 has isolation structure and is positioned at the active area between isolation structure, is formed with on the said active area such as semiconductor device such as transistor, capacitor or metal connecting line etc.Subsequently; On Semiconductor substrate 100, form first metal wiring layer 102 successively; Wherein be formed with first separator 103 with first metal wiring layer, 102 consistency of thickness between first metal wiring layer 102, establishedly on said first metal wiring layer 102 and the above-mentioned Semiconductor substrate 100 be communicated with through conductive plunger such as semiconductor device such as transistor, capacitor or metal connecting line etc.
As shown in Figure 2, on first separator 103, form first insulating medium layer 104 with chemical vapour deposition technique, and said first insulating medium layer 104 covers first metal wiring layer 102; The material of said first insulating medium layer 104 can be siliceous oxide.In first insulating medium layer 104, form first conductive plunger 105 that runs through first insulating medium layer, 104 thickness and be communicated with first metal wiring layer 102; Concrete formation technology is following: prior to spin coating photoresist layer on first insulating medium layer 104; Through after the photoetching process, on photoresist layer, define via hole image; With the photoresist layer is mask, to exposing first metal line 102, forms through hole along via hole image etching first insulating medium layer 104; After removing photoresist layer, in through hole, fill full electric conducting material.
As shown in Figure 3; Adopt said method; On first insulating medium layer 104, form second metal wiring layer 106 that covers first conductive plunger 105 successively, wherein be formed with second separator 107 between second metal wiring layer 106 with second metal wiring layer, 106 consistency of thickness; On first insulating medium layer 104, form second insulating medium layer 108 that covers second metal wiring layer 106; In second insulating medium layer 108, form second conductive plunger 109 that runs through second insulating medium layer, 108 thickness and be communicated with second metal wiring layer 106; ... form metal wiring layer, separator, insulating medium layer and the corresponding conductive plunger of requirement N according to arts demand; For example: on the N-1 insulating medium layer, form the N metal wiring layer 110 that covers the N-1 conductive plunger, wherein be formed with N separator 111 between the N metal wiring layer 110 with N metal wiring layer 110 consistency of thickness; On N separator 111, form the N insulating medium layer 112 that covers N metal wiring layer 110; In N insulating medium layer 112, form the N conductive plunger 113 that runs through N insulating medium layer 112 thickness and be communicated with N metal wiring layer 110.
In the existing technology, along with the raising of semiconductor device integrated level, high performance integrated circuit needs the circuit element of lumped resistance, electric capacity or inductance.Existing multilayer interconnect structure is piled up by multi-layer metal wiring and insulating medium layer and forms, and makes the signal between the device disturb increase easily, causes device quality to descend; In addition, this structure is not suitable for semiconductor device at a high speed.
Summary of the invention
The problem that the present invention solves provides a kind of interconnection structure and preparation method thereof, prevents that signal cross-talk and signal integrity thereof are poor.
For addressing the above problem, the present invention provides a kind of interconnection structure, comprising: Semiconductor substrate; Be positioned at the wiring layer of three-layer metal at least on the Semiconductor substrate; Insulating medium layer between metal wiring layer; Run through the dielectric layer thickness with the conductive plunger that is communicated with between the metal wiring layer, said metal wiring layer and conductive plunger cross section constitute annular spread.
Optional, the top-level metallic wiring layer of said annular spread and the wherein layer of metal wiring layer between the underlying metal wiring layer are nested in the annular spread.
Optional, the said metal wiring layer that is nested in the annular spread is not connected with conductive plunger and other metal wiring layer.
Optional, the material of said metal wiring layer is copper, aluminium or albronze, thickness is 0.1 μ m～1.5 μ m.
Optional, the material of said insulating medium layer is silica, silicon nitride or low dielectric constant material, thickness is 0.1 μ m～1.5 μ m.
Optional, the material of said conductive plunger is copper, aluminium or albronze.
Optional, also including the barrier layer between said metal wiring layer and the insulating medium layer, said barrier layer is the nitride of tantalum or titanium, thickness is 10nm～80nm.
The present invention also provides a kind of method of making interconnection structure, comprising: Semiconductor substrate is provided; On Semiconductor substrate, at interval form three-layer metal wiring layer and two-layer at least insulating medium layer at least successively, be formed with in the said insulating medium layer and run through its thickness and the conductive plunger that is communicated with between the metal wiring layer; Wherein, said metal wiring layer and conductive plunger section constitution annular spread.
Optional, the top-level metallic wiring layer of said annular spread and the wherein layer of metal wiring layer between the underlying metal wiring layer are nested in the annular spread.
Optional, the said metal wiring layer that is nested in the annular spread is not connected with conductive plunger and other metal wiring layer.
Optional, the method that forms metal wiring layer is physically splash plating method, chemical vapour deposition technique or electroless plating method.The material of said metal wiring layer is copper, aluminium or albronze, and thickness is 0.1 μ m～1.5 μ m.
Optional, the method that forms insulating medium layer is chemical vapour deposition technique or physics film coated method.The material of said insulating medium layer is silica, silicon nitride or low dielectric constant material, and thickness is 0.1 μ m～1.5 μ m.
Optional, the material of said conductive plunger is copper, aluminium or albronze.
Optional, also being formed with the barrier layer between said metal wiring layer and the insulating medium layer, the method that forms said barrier layer is the physically splash plating method.The material on said barrier layer is the nitride of tantalum or titanium, and thickness is 10nm～80nm.
Compared with prior art; The present invention has the following advantages: the metal wiring layer of multilayer interconnect structure and the cross section of conductive plunger are made into loop configuration; Because loop configuration is isolated metallic signal lines in it and extraneous metallic signal lines, has reduced the interference between metallic signal lines and the metallic signal lines; Simultaneously, the sectional area of loop configuration increases, and can reduce its resistance, is suitable for the pipeline as high potential or electronegative potential reference voltage.This structure can be suitable for high-speed interconnect, strengthens the signal integrity of interconnection structure, can reduce crosstalking between signal simultaneously.
Description of drawings
Fig. 1 to Fig. 3 is the sketch map that prior art forms metal interconnect structure;
Fig. 4 to Fig. 8 is the first embodiment sketch map that the present invention makes interconnection structure;
Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 9 make the second embodiment sketch map of interconnection structure for the present invention;
Fig. 4, Fig. 5, Figure 10, Figure 11, Figure 12 make the 3rd embodiment sketch map of interconnection structure for the present invention.
Embodiment
The present invention is made into loop configuration with the metal wiring layer of multilayer interconnect structure and the cross section of conductive plunger, because loop configuration is isolated metallic signal lines in it and extraneous metallic signal lines, has reduced the interference between metallic signal lines and the metallic signal lines; Simultaneously, the sectional area of loop configuration increases, and can reduce its resistance, is suitable for the pipeline as high potential or electronegative potential reference voltage.This structure can be suitable for high-speed interconnect, strengthens the signal integrity of interconnection structure, can reduce crosstalking between signal simultaneously.
For realizing above-mentioned purpose, the embodiment that the present invention makes interconnection structure is: Semiconductor substrate is provided; On Semiconductor substrate, at interval form three-layer metal wiring layer and two-layer at least insulating medium layer at least successively, be formed with in the said insulating medium layer and run through its thickness and the conductive plunger that is communicated with between the metal wiring layer; Wherein, said metal wiring layer and conductive plunger section constitution annular spread.
Interconnection structure based on above-mentioned execution mode forms comprises: Semiconductor substrate; Be positioned at the wiring layer of three-layer metal at least on the Semiconductor substrate; Insulating medium layer between metal wiring layer; Run through the dielectric layer thickness with the conductive plunger that is communicated with between the metal wiring layer, said metal wiring layer and conductive plunger cross section constitute annular spread.
In other execution mode, between metal wiring layer and the insulating medium layer, be formed with the barrier layer between conductive plunger and the insulating medium layer.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Embodiment one
Fig. 5 to Fig. 9 is the embodiment sketch map that the present invention makes interconnection structure.As shown in Figure 5, semi-conductive substrate 200 is provided, said Semiconductor substrate 200 has isolation structure and is positioned at the active area between isolation structure, is formed with on the said active area such as semiconductor device such as transistor, capacitor or metal connecting line etc.
Continuation is with reference to figure 5; Subsequently; On Semiconductor substrate 200, forming thickness is first metal wiring layer 202 of 0.1 μ m～1.5 μ m; The material of said first metal wiring layer 202 can be copper, aluminium or albronze etc.; Wherein be formed with first separator 203 with first metal wiring layer, 202 consistency of thickness between first metal wiring layer 202, establishedly on said first metal wiring layer 202 and the above-mentioned Semiconductor substrate 200 be communicated with through conductive plunger such as semiconductor device such as transistor, capacitor or metal connecting line etc.
The technology of above-mentioned first metal wiring layer 202 of said formation and first separator 203 is following: if form the material of first metal wiring layer 202 is copper; On Semiconductor substrate 200, form first separator 203 with chemical vapour deposition technique, the material of said first separator 203 is silica or silicon oxynitride etc.; Spin coating photoresist layer on first separator 203 through after the photoetching process, defines first metal wiring pattern; With the photoresist layer is mask, to exposing Semiconductor substrate 200, forms the first metal line opening along the first metal wiring pattern etching, first separator 203; After removing photoresist layer, with galvanoplastic electro-coppering in the first metal line opening.
If forming the material of first metal line 202 is aluminium or albronze, on Semiconductor substrate 200, form the first metal layer with physical vaporous deposition; On the first metal layer, form photoresist layer, after exposure imaging technology, on photoresist layer, define first metal wiring pattern; With the photoresist layer is mask, to exposing Semiconductor substrate, forms first metal wiring layer 202 along the first metal wiring pattern etching the first metal layer; On Semiconductor substrate 200, form first separator 203 with chemical vapour deposition technique, said first separator 203 covers first metal wiring layer 202; With chemical mechanical polishing method first separator 203 is planarized to and exposes first metal wiring layer 202.
With reference to figure 6; Use chemical vapour deposition technique on first separator 203, to form first insulating medium layer 204 that thickness is 0.1 μ m～1.5 μ m; And said first insulating medium layer 204 covers first metal wiring layer 202, and the material of said first insulating medium layer is silica, silicon nitride or low dielectric constant material etc.In first insulating medium layer 204, form first conductive plunger 205 that runs through first insulating medium layer, 204 thickness and be communicated with two ends, first metal wiring layer, 202 edge; Concrete formation technology is following: prior to spin coating photoresist layer on first insulating medium layer 204; Through after the photoetching process, on photoresist layer, define and the corresponding via hole image of first insulating medium layer, 204 end positions; With the photoresist layer is mask, to exposing first metal line 202, forms through hole along via hole image etching first insulating medium layer 204; After removing photoresist layer, in through hole, fill full electric conducting material.
As shown in Figure 7; On first insulating medium layer 204, forming thickness is 0.1 μ m～second metal wiring layer 206a of 1.5 μ m, 206b, 206c; The material of the said second metal wiring layer 206a, 206b, 206c can be copper, aluminium or albronze etc.; Wherein be formed with second separator 207 between the second metal wiring layer 206a, 206b, the 206c with the second metal wiring layer 206a, 206b, 206c consistency of thickness; The said second metal wiring layer 206a, 206c are communicated with first metal wiring layer 202 through first conductive plunger 205 in first insulating medium layer 204 respectively; And the second metal wiring layer 206b is not connected with first metal wiring layer 202 between the second metal wiring layer 206a, 206c.
Said formation is the second metal wiring layer 206a, 206b, the 206c of material with copper; With form with aluminium or albronze etc. be the technology of the second metal wiring layer 206a, 206b, 206c of material with the technology of above-mentioned formation first metal line 202, therefore repeat no more.
As shown in Figure 8; Use chemical vapour deposition technique on second separator 207, to form second insulating medium layer 208 that thickness is 0.1 μ m～1.5 μ m; And said second insulating medium layer 208 covers the second metal wiring layer 206a, 206b, 206c, and the material of said second insulating medium layer 208 is silica, silicon nitride or low dielectric constant material etc.In second insulating medium layer 208, form second conductive plunger 209 that runs through second insulating medium layer, 208 thickness and be communicated with the second metal wiring layer 206a, 206c respectively.The concrete technology that forms repeats no more at this with forming first conductive plunger 205.
With reference to figure 9; On second insulating medium layer 208, forming thickness is the 3rd metal wiring layer 210 of 0.1 μ m～1.5 μ m; The material of said the 3rd metal wiring layer 210 can be copper, aluminium or albronze etc.; Wherein be formed with the 3rd separator 211 with the 3rd metal wiring layer 210 consistency of thickness between the 3rd metal wiring layer 210, the two ends, edge of said the 3rd metal wiring layer 210 are communicated with the second metal wiring layer 206a, 206c through second conductive plungers 209 in second insulating medium layer 208 respectively.
Said formation is the technology of the technology of the 3rd metal wiring layer 210 of material and second metal wiring layer 210 that formation is material with above-mentioned formation first metal line 202 with copper with aluminium or albronze etc., therefore repeats no more.
Except that the foregoing description; Can also form Crossed Circle distributed architecture, seven layers of three annular spread structures, nine layers of Fourth Ring shape distributed architecture that metal wiring layer constitutes that metal wiring layer constitutes that five layers of metal wiring layer constitute ..., can confirm the quantity of metal wiring layer according to concrete technological requirement.As long as make the metal wiring layer of last formation and the continuous outward extending annular spread structure of cross section that conductive plunger combines formation for insulating by insulating medium layer.
Interconnection structure based on the foregoing description formation; Comprise: Semiconductor substrate 200; Said Semiconductor substrate 200 has isolation structure and is positioned at the active area between isolation structure, is formed with on the said active area such as semiconductor device such as transistor, capacitor or metal connecting line etc.; First metal wiring layer 202 is positioned on the Semiconductor substrate 200; First separator 203 on the Semiconductor substrate 200 and be between first metal wiring layer 202, is used for the isolation between first metal wiring layer 202, and its thickness is consistent with first metal wiring layer 202; First insulating medium layer 204 is positioned on first metal wiring layer 202 and first separator 203; First conductive plunger 205 runs through first insulating medium layer, 204 thickness and is communicated with two ends, first metal wiring layer, 202 edge; The second metal wiring layer 206a, 206b, 206c; Be positioned on first insulating medium layer 204; Wherein the second metal wiring layer 206a, 206c are communicated with first metal wiring layer 202 through first conductive plunger 205 in first insulating medium layer 204 respectively; And the second metal wiring layer 206b is not connected with first metal wiring layer 202 between the second metal wiring layer 206a, 206c; Second separator 207; On first insulating medium layer 204 and be between the second metal wiring layer 206a, 206b, the 206c; Be used for the isolation between the second metal wiring layer 206a, 206b, the 206c, its thickness and the second metal wiring layer 206a, 206b, 206c are consistent; Second insulating medium layer 208 is positioned on the second metal wiring layer 206a, 206b, 206c and second separator 207; Second conductive plunger 209 runs through second insulating medium layer, 208 thickness and is communicated with the second metal wiring layer 206a, 206c respectively; The 3rd metal wiring layer 210 is positioned on second insulating medium layer 208, and its two ends, edge are communicated with the second metal wiring layer 206a, 206c through second conductive plunger 209 in second insulating medium layer 208 respectively; The 3rd separator 211 on second insulating medium layer 208 and be between the 3rd metal wiring layer 210, is used for the isolation between the 3rd metal wiring layer 210, and its thickness is consistent with the 3rd metal wiring layer 210.
Embodiment two
Fig. 5, Fig. 6, Fig. 7, Fig. 8, Figure 10 make the second embodiment sketch map of interconnection structure for the present invention.Concrete technology by second conductive plunger 209 that forms first metal wiring layer 202 and first separator 203, first insulating medium layer 204, first conductive plunger 205 that is communicated with two ends, first metal wiring layer, 202 edge, the second metal wiring layer 206a, 206b, 206c and second separator 207, second insulating medium layer 208 among Fig. 5～Fig. 8, is communicated with the second metal wiring layer 206a, 206c respectively has detailed description in embodiment one, repeat no more at this.
With reference to Figure 10; On second insulating medium layer 208, forming thickness is 0.1 μ m～the 3rd metal wiring layer 210a of 1.5 μ m, 210b; The material of said the 3rd metal wiring layer 210a, 210b can be copper, aluminium or albronze etc.; Wherein be formed with the 3rd separator 211 between the 3rd metal wiring layer 210a, the 210b with the 3rd metal wiring layer 210a, 210b consistency of thickness; Said the 3rd metal wiring layer 210a is communicated with the second metal wiring layer 206a through second conductive plunger 209 in second insulating medium layer 208, and the 3rd metal wiring layer 210b is communicated with the second metal wiring layer 206c through second conductive plunger 209 in second insulating medium layer 208.
Continuation is with reference to Figure 10; Use chemical vapour deposition technique on the 3rd separator 211, to form the 3rd insulating medium layer 212 that thickness is 0.1 μ m～1.5 μ m; And said the 3rd insulating medium layer 212 covers the 3rd metal wiring layer 210a, 210b, and the material of said the 3rd insulating medium layer 212 is silica, silicon nitride or low dielectric constant material etc.In the 3rd insulating medium layer 212, form the 3rd conductive plunger 213 that runs through the 3rd insulating medium layer 212 thickness and be communicated with the 3rd metal wiring layer 210a, 210b respectively.The concrete technology that forms repeats no more at this with forming first conductive plunger 205.On the 3rd insulating medium layer 212, forming thickness is the 4th metal wiring layer 216 of 0.1 μ m～1.5 μ m; The material of said the 4th metal wiring layer 216 can be copper, aluminium or albronze etc.; Wherein be formed with the 4th separator 215 with the 4th metal wiring layer 216 consistency of thickness between the 4th metal wiring layer 216, the two ends, edge of said the 4th metal wiring layer 216 are communicated with the 3rd metal wiring layer 210a, 210b through the 3rd conductive plungers 213 in the 3rd insulating medium layer 212 respectively.
Interconnection structure based on the foregoing description formation; Comprise: Semiconductor substrate 200; Said Semiconductor substrate 200 has isolation structure and is positioned at the active area between isolation structure, is formed with on the said active area such as semiconductor device such as transistor, capacitor or metal connecting line etc.; First metal wiring layer 202 is positioned on the Semiconductor substrate 200; First separator 203 on the Semiconductor substrate 200 and be between first metal wiring layer 202, is used for the isolation between first metal wiring layer 202, and its thickness is consistent with first metal wiring layer 202; First insulating medium layer 204 is positioned on first metal wiring layer 202 and first separator 203; First conductive plunger 205 runs through first insulating medium layer, 204 thickness and is communicated with two ends, first metal wiring layer, 202 edge; The second metal wiring layer 206a, 206b, 206c; Be positioned on first insulating medium layer 204; Wherein the second metal wiring layer 206a, 206c are communicated with first metal wiring layer 202 through first conductive plunger 205 in first insulating medium layer 204 respectively; And the second metal wiring layer 206b is not connected with first metal wiring layer 202 between the second metal wiring layer 206a, 206c; Second separator 207; On first insulating medium layer 204 and be between the second metal wiring layer 206a, 206b, the 206c; Be used for the isolation between the second metal wiring layer 206a, 206b, the 206c, its thickness and the second metal wiring layer 206a, 206b, 206c are consistent; Second insulating medium layer 208 is positioned on the second metal wiring layer 206a, 206b, 206c and second separator 207; Second conductive plunger 209 runs through second insulating medium layer, 208 thickness and is communicated with the second metal wiring layer 206a, 206c respectively; The 3rd metal wiring layer 210a, 210b are positioned on second insulating medium layer 208, are communicated with the second metal wiring layer 206a, 206c through second conductive plunger 209 in second insulating medium layer 208 respectively; The 3rd separator 211 on second insulating medium layer 208 and be between the 3rd metal wiring layer 210a, the 210b, is used for the isolation between the 3rd metal wiring layer 210a, the 210b, and its thickness and the 3rd metal wiring layer 210a, 210b are consistent; The 3rd insulating medium layer 212 is positioned on the 3rd metal wiring layer 210a, 210b and the 3rd separator 211; The 3rd conductive plunger 213 runs through the 3rd insulating medium layer 212 thickness and is communicated with the 3rd metal wiring layer 210a, 210b respectively; The 4th metal wiring layer 216 is positioned on the 3rd insulating medium layer 212, and its two ends, edge are communicated with the 3rd metal wiring layer 210a, 210b through the 3rd conductive plunger 213 in the 3rd insulating medium layer 212 respectively; The 4th separator 215 on the 3rd insulating medium layer 212 and be between the 4th metal wiring layer 216, is used for the isolation between the 4th metal wiring layer 216, and its thickness is consistent with the 4th metal wiring layer 216.
Except that the foregoing description; Can also between the 3rd metal wiring layer 210a, 210b and the 4th metal wiring layer 216, form several layers and the 3rd metal wiring layer 210a, the consistent metal wiring layer of 210b distribution, and connect by the conductive plunger in the insulating medium layer.
Embodiment three
Fig. 5, Fig. 6, Figure 11, Figure 12, Figure 13 make the 3rd embodiment sketch map of interconnection structure for the present invention.Concrete technology by first conductive plunger 205 that forms first metal wiring layer 202 and first separator 203, first insulating medium layer 204 among Fig. 5～Fig. 6, is communicated with two ends, first metal wiring layer, 202 edge has detailed description in embodiment one, repeat no more at this.
Shown in figure 11; On first insulating medium layer 204, forming thickness is 0.1 μ m～second metal wiring layer 206a of 1.5 μ m, 206b; The material of the said second metal wiring layer 206a, 206b can be copper, aluminium or albronze etc.; Wherein be formed with second separator 207 with the second metal wiring layer 206a, 206b consistency of thickness between the second metal wiring layer 206a, the 206b, the said second metal wiring layer 206a, 206b are communicated with first metal wiring layer 202 through first conductive plungers 205 in first insulating medium layer 204 respectively.
Shown in figure 12; Use chemical vapour deposition technique on second separator 207, to form second insulating medium layer 208 that thickness is 0.1 μ m～1.5 μ m; And said second insulating medium layer 208 covers the second metal wiring layer 206a, 206b, and the material of said second insulating medium layer 208 is silica, silicon nitride or low dielectric constant material etc.In second insulating medium layer 208, form second conductive plunger 209 that runs through second insulating medium layer, 208 thickness and be communicated with the second metal wiring layer 206a, 206b respectively.The concrete technology that forms repeats no more at this with the method for mentioning among the embodiment one.
Shown in figure 13; On second insulating medium layer 208, forming thickness is 0.1 μ m～the 3rd metal wiring layer 210a of 1.5 μ m, 210b, 210c; The material of said the 3rd metal wiring layer 210a, 210b can be copper, aluminium or albronze etc.; Wherein be formed with the 3rd separator 211 between the 3rd metal wiring layer 210a, 210b, the 210c with the 3rd metal wiring layer 210a, 210b, 210c consistency of thickness; Said the 3rd metal wiring layer 210a, 210c are communicated with the second metal wiring layer 206a, 206b through second conductive plunger 209 in second insulating medium layer 208 respectively; And the 3rd metal wiring layer 210b is not connected with the second metal wiring layer 206a, 206b between the 3rd metal wiring layer 210a, 210c.
Continuation is with reference to Figure 13; Use chemical vapour deposition technique on the 3rd separator 211, to form the 3rd insulating medium layer 212 that thickness is 0.1 μ m～1.5 μ m; And said the 3rd insulating medium layer 212 covers the 3rd metal wiring layer 210a, 210b, 210c, and the material of said the 3rd insulating medium layer 212 is silica, silicon nitride or low dielectric constant material etc.In the 3rd insulating medium layer 212, form the 3rd conductive plunger 213 that runs through the 3rd insulating medium layer 212 thickness and be communicated with the 3rd metal wiring layer 210a, 210b, 210c respectively.On the 3rd insulating medium layer 212, forming thickness is the 4th metal wiring layer 216 of 0.1 μ m～1.5 μ m; The material of said the 4th metal wiring layer 216 can be copper, aluminium or albronze etc.; Wherein be formed with the 4th separator 215 with the 4th metal wiring layer 216 consistency of thickness between the 4th metal wiring layer 216, the two ends, edge of said the 4th metal wiring layer 216 are communicated with the 3rd metal wiring layer 210a, 210c through the 3rd conductive plungers 213 in the 3rd insulating medium layer 212 respectively.
Interconnection structure based on the foregoing description formation; Comprise: Semiconductor substrate 200; Said Semiconductor substrate 200 has isolation structure and is positioned at the active area between isolation structure, is formed with on the said active area such as semiconductor device such as transistor, capacitor or metal connecting line etc.; First metal wiring layer 202 is positioned on the Semiconductor substrate 200; First separator 203 on the Semiconductor substrate 200 and be between first metal wiring layer 202, is used for the isolation between first metal wiring layer 202, and its thickness is consistent with first metal wiring layer 202; First insulating medium layer 204 is positioned on first metal wiring layer 202 and first separator 203; First conductive plunger 205 runs through first insulating medium layer, 204 thickness and is communicated with two ends, first metal wiring layer, 202 edge; The second metal wiring layer 206a, 206b are positioned on first insulating medium layer 204, are communicated with first metal wiring layer 202 through first conductive plunger 205 in first insulating medium layer 204 respectively; Second separator 207 on first insulating medium layer 204 and be between the second metal wiring layer 206a, the 206b, is used for the isolation between the second metal wiring layer 206a, the 206b, and its thickness and the second metal wiring layer 206a, 206b are consistent; Second insulating medium layer 208 is positioned on the second metal wiring layer 206a, 206b and second separator 207; Second conductive plunger 209 runs through second insulating medium layer, 208 thickness and is communicated with the second metal wiring layer 206a, 206b respectively; The 3rd metal wiring layer 210a, 210b, 210c; Be positioned on second insulating medium layer 208; Wherein the 3rd metal wiring layer 210a, 210c are communicated with the second metal wiring layer 206a, 206b through second conductive plunger 209 in second insulating medium layer 208 respectively; And the 3rd metal wiring layer 210b is not connected with the second metal wiring layer 206a, 206b between the 3rd metal wiring layer 210a, 210c; The 3rd separator 211; On second insulating medium layer 208 and be between the 3rd metal wiring layer 210a, 210b, the 210c; Be used for the isolation between the 3rd metal wiring layer 210a, 210b, the 210c, its thickness and the 3rd metal wiring layer 210a, 210b, 210c are consistent; The 3rd insulating medium layer 212 is positioned on the 3rd metal wiring layer 210a, 210b, 210c and the 3rd separator 211; The 3rd conductive plunger 213 runs through the 3rd insulating medium layer 212 thickness and is communicated with the 3rd metal wiring layer 210a, 210c respectively; The 4th metal wiring layer 216 is positioned on the 3rd insulating medium layer 212, and its two ends, edge are communicated with the 3rd metal wiring layer 210a, 210c through the 3rd conductive plunger 213 in the 3rd insulating medium layer 212 respectively; The 4th separator 215 on the 3rd insulating medium layer 212 and be between the 4th metal wiring layer 216, is used for the isolation between the 4th metal wiring layer 216, and its thickness is consistent with the 4th metal wiring layer 216.
Except that the foregoing description; Can also between first metal wiring layer 202 and the second metal wiring layer 206a, 206b, form several layers and the second metal wiring layer 206a, the consistent metal wiring layer of 206b distribution, and connect by the conductive plunger in the insulating medium layer.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (17)
1. interconnection structure comprises:
Semiconductor substrate is positioned at the wiring layer of three-layer metal at least on the Semiconductor substrate, and the insulating medium layer between metal wiring layer runs through the dielectric layer thickness with the conductive plunger that is communicated with between the metal wiring layer; It is characterized in that, said metal wiring layer and conductive plunger cross section constitute annular spread.
2. according to the said interconnection structure of claim 1, it is characterized in that the top-level metallic wiring layer of said annular spread and the wherein layer of metal wiring layer between the underlying metal wiring layer are nested in the annular spread.
3. according to the said interconnection structure of claim 2, it is characterized in that the said metal wiring layer that is nested in the annular spread is not connected with conductive plunger and other metal wiring layer.
4. according to the said interconnection structure of claim 1, it is characterized in that the material of said metal wiring layer is copper, aluminium or albronze, thickness is 0.1 μ m～1.5 μ m.
5. according to the said interconnection structure of claim 1, it is characterized in that the material of said insulating medium layer is silica, silicon nitride or low dielectric constant material, thickness is 0.1 μ m～1.5 μ m.
6. according to the said interconnection structure of claim 1, it is characterized in that the material of said conductive plunger is copper, aluminium or albronze.
7. according to the said interconnection structure of claim 1, it is characterized in that also include the barrier layer between said metal wiring layer and the insulating medium layer, said barrier layer is the nitride of tantalum or titanium, thickness is 10nm～80nm.
8. a method of making the said interconnection structure of claim 1 is characterized in that, comprising:
Semiconductor substrate is provided;
On Semiconductor substrate, at interval form three-layer metal wiring layer and two-layer at least insulating medium layer at least successively, be formed with in the said insulating medium layer and run through its thickness and the conductive plunger that is communicated with between the metal wiring layer;
Wherein, said metal wiring layer and conductive plunger section constitution annular spread.
9. method according to claim 8 is characterized in that, the top-level metallic wiring layer of said annular spread and the wherein layer of metal wiring layer between the underlying metal wiring layer are nested in the annular spread.
10. method according to claim 9 is characterized in that, the said metal wiring layer that is nested in the annular spread is not connected with conductive plunger and other metal wiring layer.
11. method according to claim 8 is characterized in that, the method that forms metal wiring layer is physically splash plating method, chemical vapour deposition technique or electroless plating method.
12. method according to claim 11 is characterized in that, the material of said metal wiring layer is copper, aluminium or albronze, and thickness is 0.1 μ m～1.5 μ m.
13. method according to claim 8 is characterized in that, the method that forms insulating medium layer is chemical vapour deposition technique or physics film coated method.
14. method according to claim 13 is characterized in that, the material of said insulating medium layer is silica, silicon nitride or low dielectric constant material, and thickness is 0.1 μ m～1.5 μ m.
15. method according to claim 8 is characterized in that, the material of said conductive plunger is copper, aluminium or albronze.
16. method according to claim 8 is characterized in that, also is formed with the barrier layer between said metal wiring layer and the insulating medium layer, the method that forms said barrier layer is the physically splash plating method.
17. method according to claim 16 is characterized in that, the material on said barrier layer is the nitride of tantalum or titanium, and thickness is 10nm～80nm.
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| TWI681537B (en) * | 2019-05-30 | 2020-01-01 | 旺宏電子股份有限公司 | Semiconductor structure and method of fabricating wiring structure |
| CN113437042B (en) * | 2021-06-21 | 2022-06-17 | 武汉新芯集成电路制造有限公司 | Pad structure, semiconductor test structure and semiconductor test method |
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| US6333255B1 (en) * | 1997-08-21 | 2001-12-25 | Matsushita Electronics Corporation | Method for making semiconductor device containing low carbon film for interconnect structures |
| JP2006165054A (en) * | 2004-12-02 | 2006-06-22 | Fujitsu Ltd | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6333255B1 (en) * | 1997-08-21 | 2001-12-25 | Matsushita Electronics Corporation | Method for making semiconductor device containing low carbon film for interconnect structures |
| JP2006165054A (en) * | 2004-12-02 | 2006-06-22 | Fujitsu Ltd | Semiconductor device |
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