CN102055479A - Digital-to-analog converter capable of optimizing power consumption and output signal-to-noise ratio - Google Patents
Digital-to-analog converter capable of optimizing power consumption and output signal-to-noise ratio Download PDFInfo
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Abstract
The invention relates to a digital-to-analog converter capable of optimizing power consumption and output signal-to-noise ratio, belonging to the design field of mixed signal integrated circuits. The digital-to-analog converter comprises an interpolation filter, a 1-bit delta-sigma modulator, a class-D power amplifier, an analog low pass filter and a DLPF (Digital Low Pass Filter) coder, wherein the interpolation filter, the 1-bit delta-sigma modulator, the class-D power amplifier and the analog low pass filter are sequentially connected; and the DLPF coder is connected between the 1-bit delta-sigma modulator and the class-D power amplifier. The input multi-bit digital signals firstly finish the up-sampling through the interpolation filter and then finish the noise shaping through the 1-bit delta-sigma modulator, 1-bit codes output by the modulator are coded by the DLPF coder, 2-bit codes output by the DLPF coder control the switching operation of the class-D power amplifier, and finally, the unnecessary out-of-band noise is filtered out through the analog low pass filter, thereby realizing digital-to-analog conversion and power amplification. The invention can lower the switching operation frequency of the class-D power amplifier, thereby lowering the power consumption of a delta-sigma digital-to-analog converter; and the invention also can improve the signal-to-noise ratio of output signals.
Description
Technical field
The invention belongs to the composite signal integrated circuits design field, particularly a kind of Δ ∑ digital to analog converter of optimizing power consumption and output signal-to-noise ratio.
Background technology
Δ ∑ (Delta-Sigma) digital to analog converter has been transferred to numeric field to most of transfer process, exchange high request for the complexity of digital circuit to analog conversion circuit, can realize the high accuracy conversion and not need accurate element coupling, cost is low and be easy to integratedly, thereby is widely used in fields such as high-quality digital audio and video signals processing, multimedia signal dispose.The D power-like amplifier has advantages such as efficient height, volume is little, in light weight, power output is big, can effectively reduce the requirement to power supply and heat radiation, becomes portable set and selects preferably.Therefore the Δ ∑ digital to analog converter of integrated D power-like amplifier can be finished whole the operating in the numeric field before the simulation low-pass filter, and has both advantages simultaneously concurrently.
Traditional Δ ∑ digital to analog converter normally is made of the interpolation filter, Δ ∑ modulator, inner D/A converting circuit and the simulation low-pass filter that connect successively, as shown in Figure 1.Will consider that often the inside D/A converting circuit of 1 bit designs fairly simple when inner D/A converting circuit designs in the traditional structure, but the slew rate of the signal that export the conversion back is higher, and contains higher out-of-band signal energy; The inside D/A converting circuit of many bits is owing to the nonlinearity erron that needs to eliminate digital-to-analogue conversion needs extra complicated circuit design.Simultaneously, the stronger if desired load capacity of traditional Δ ∑ digital to analog converter also needs extra power amplification circuit.
A kind of project organization the most close with the present invention as shown in Figure 2, be to constitute by the interpolation filter, 1 bit Δ ∑ modulator, D power-like amplifier, the simulation low-pass filter that connect successively, this structure can be finished all operations before the simulation low-pass filter in numeric field, avoided the design of inner D/A converting circuit in the traditional structure, and because can carrying out highly efficient power, amplifies the D power-like amplifier, so no longer the required power amplifying circuit can drive load efficiently.But, the interpolation filter of prime makes that the working clock frequency of circuit is higher owing to carrying out signal liter to sample, the quick break-make of 1 bit stream of the high speed after 1 bit Δ ∑ modulators modulate and inverse code current control D power-like amplifier switch thereof causes circuit power consumption relatively large; In order to obtain output signal, after making, 1 bit stream driving D power-like amplifier at a high speed has relatively high expectations relatively on the analogue low pass filtering circuit design of level, so have much room for improvement than high s/n ratio.
Summary of the invention
The objective of the invention is to propose a kind of digital to analog converter of optimizing power consumption and output signal-to-noise ratio for overcoming the weak point of prior art.On the one hand, by 1 bit code of 1 bit Δ ∑ modulator output is carried out logic coding, signal behind the coding is controlled the switch motion of D power-like amplifier again, can reduce the switch motion frequency of D power-like amplifier, and then reduces the power consumption of Δ ∑ digital to analog converter; On the other hand, the encoder that adds before the D power-like amplifier has the function of wave digital lowpass filter, can improve the signal to noise ratio of output signal.
A kind of digital to analog converter of optimizing power consumption and output signal-to-noise ratio of the present invention, adopt Δ ∑ digital to analog converter, comprise the interpolation filter, 1 bit Δ ∑ modulator, D power-like amplifier and the simulation low-pass filter that connect successively, it is characterized in that, also comprise the DLPF encoder that is connected between 1 bit Δ ∑ modulator and the D power-like amplifier; Wherein, the multiple bit digital signal of input is finished by interpolation filter earlier and is risen sampling, finish noise shaping by 1 bit Δ ∑ modulator then, 1 bit code of modulator output is encoded through the DLPF encoder again, the switching manipulation of the 2 bit code control D power-like amplifier of DLPF encoder output, final through the unnecessary out-of-band noise of simulation low-pass filter filtering, realize digital-to-analogue conversion and power amplification.
The optimization power consumption that the present invention proposes and the course of work of Δ ∑ digital to analog converter when carrying out digital-to-analogue conversion of output signal-noise ratio are:
(1) the multiple bit digital input signal carries out interpolation filtering through interpolation filter, and the process of interpolation filtering is finished and risen sampling, promptly the sample rate of the output signal of interpolation filter become the input signal sample rate OSR doubly, OSR is an over-sampling rate.
(2) output signal of interpolation filter enters 1 bit Δ ∑ modulator and carries out noise shaping, and output signal is the digital code stream of 1 bit.
The digital code stream of (3) 1 bits is input to the DLPF encoder and encodes, and the output signal behind the coding is 2 bit code OUT12 and OUT34, and OUT12 and OUT34 are controlling the switch on and off of D power-like amplifier.
(4) power amplification of signal is carried out in OUT12 and the OUT34 switching manipulation of controlling the D power-like amplifier, and the digital signal after the power amplification is EPOUT12-EPOUT34, and this is ternary (1,0,1) signal.
(5) EPOUT12-EPOUT34 is input to simulation low-pass filter, and the outer high fdrequency component of filtering band obtains the analog output signal that needs.
Innovation part of the present invention is to add the DLPF encoder between Δ ∑ modulator and D power-like amplifier, will effectively reduce the switch motion frequency of D power-like amplifier behind the adding DLPF encoder, and then reduce the power consumption of digital to analog converter; The DLPF encoder that adds has the function of wave digital lowpass filter, so can improve the signal to noise ratio of output signal.
Description of drawings
Fig. 1 is the structure chart of traditional Δ ∑ digital to analog converter.
Fig. 2 is the structure chart that designs the most close digital to analog converter with the present invention.
The structure chart of the Δ ∑ digital to analog converter that Fig. 3 designs for the present invention.
Fig. 4 is the example structure figure of interpolation filter of the present invention.
The time-division multiplexing unit that Fig. 5 adopts when partly realizing with iir filter for interpolation filter.
Fig. 6 is the example structure figure of DLPF encoder of the present invention.
Fig. 7 is the example structure figure of D power-like amplifier of the present invention.
Embodiment
A kind of Δ ∑ digital to analog converter of optimizing power consumption and output signal-to-noise ratio that the present invention proposes reaches embodiment in conjunction with the accompanying drawings and is described in detail as follows:
A kind of digital to analog converter of optimizing power consumption and output signal-to-noise ratio of the present invention, adopt Δ ∑ digital to analog converter, comprise the interpolation filter, 1 bit Δ ∑ modulator, D power-like amplifier and the simulation low-pass filter that connect successively, it is characterized in that, also comprise DLPF (the Digital Low Pass Filter) encoder that is connected between 1 bit Δ ∑ modulator and the D power-like amplifier; As shown in Figure 3; Wherein, the multiple bit digital signal of input is finished by interpolation filter earlier and is risen sampling, finish noise shaping by 1 bit Δ ∑ modulator then, 1 bit code of modulator output is encoded through the DLPF encoder again, the switching manipulation of the 2 bit code control D power-like amplifier of DLPF encoder output, final through the unnecessary out-of-band noise of simulation low-pass filter filtering, realize digital-to-analogue conversion and power amplification.
The specific embodiment and the function of each device of the present invention are described in detail as follows:
(1) interpolation filter:
Oversampling technique is one of core technology of Delta-Sigma digital to analog converter, and it is realized by signal is carried out interpolation.Interpolation filter can be realized the conversion of sample rate, eliminates the image signal of introducing because of interpolation simultaneously.Because the passband of interpolation filter far is narrower than the sample frequency of input signal usually, so interpolation filter needs very precipitous transition band, but the coefficient that reaches steeper transition band filter is often too big, be unfavorable for the hardware realization, adopt multilevel hierarchy to realize that interpolation filter is to address this problem usually.
Interpolation filter of the present invention adopts the 2 grade of half band iir filter that connects successively by switch, 4 grades of comb value filtering devices, finishes 64 times and rises sampling, as shown in Figure 4.The time-division multiplexing unit that each level partly adopts the method for designing of BMCU (Basic Micro ControlUnit) to realize with iir filter.Can make full use of the time slot that over-sampling produces, hardware circuit is carried out time division multiplexing, this time-division multiplexing unit as shown in Figure 5, time-division multiplexing unit is only by adder, command register St, complement code transducer, shift unit, and simple element circuit such as a plurality of MUX and a plurality of D class triggers is realized, wherein, from command register, take out the operation that instruction Ins (16:0) controls each bar data path, the Q of input port
1And Q
0Be the list entries value in continuous two moment, other labels are represented a kind of annexation, and the node of same numeral connects together.Concrete sequential operation is as shown in table 1:
Table 1
The operation that each step realizes is respectively:
Step 1:M=Q
1+ Q
0/ 8
Step 2:y
1(n)=M-y
1(n-2)/8
Step 3:M=0-y
2(n-3)/2
Step 4:y
2(n-1)=M-y
2(n-3)/16
Step 5:Dout1=y
1(n-1)+y
2(n-2)
Step 6:y
1(n)=0-y
1(n-2)/8
Step 7:M=Q
0/ 2+Q
0/ 16
Step 8:M=M+Q
1
Step 9:M=M-y
2(n-3)/2
Step 10:y
2(n-1)=M-y
2(n-3)/16
Step 11:M=y
1(n-1)+y
2(n-2)=Dout2
11 steps were utilized 11 time slots altogether.Output Dout1 when St=011111 (partly being with 2 of iir filters to be St=01111), output Dout2 when St=111111 (partly being with 2 of iir filters to be St=01111) is so realized that 2 times rise sampling.
The embodiment of comb value filtering device of the present invention adopts document " a kind of digital audio Z-AD/A transducer that is applicable to " (Zhou Lin, Li Dongmei, Wang Zhihua. a kind of digital audio Z-AD/A transducer [J] that is applicable to. microelectronics, 2005/12, PP:639-646) method for designing in realizes.
(2) 1 bit Δ ∑ modulators:
Δ ∑ modulator is realized noise shaping, has the all-pass wave filtering effect for inband signaling, then has the high-pass filtering effect for quantizing noise.Output 1 bit code in modulation back is moved quantizing noise to band outer high frequency.1 bit Δ ∑ modulator in the present embodiment adopts the feed forward architecture of quadravalence single-bit band feedback, by the level Four integrator, the one-level quantizer, article five, (the concrete definite of each parameter can be referring to Jeongjin Roh in the circuit for feedforward branch road and a feedback branch formation, Sanho Byun, Youngkil Choi, Hyungdong Roh, Yi-Gyeong Kim, and Jong-Kee Kwon, " A 0.9-V 60-W1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range; " IEEE J.Solid-StateCircuits, vol.43, no.2, pp.361-370, February 2008).
(3) DLPF encoder: the main distinction technical characterictic that is the present invention and existing Δ ∑ digital to analog converter.
DLPF encoder of the present invention is immediately following after Δ ∑ modulator, and its input signal is exactly 1 bit code of Δ ∑ modulator output.The embodiment of DLPF encoder as shown in Figure 6, by four d type flip flops, an adder, an XOR gate, an inverter constitutes, concrete annexation is: input signal DIN (n) links to each other with the D port of first d type flip flop and the B port of adder, the Q port of first d type flip flop links to each other with the D port of second d type flip flop, the Q port of second d type flip flop links to each other with the A port of adder, the S port of adder links to each other with the A port of XOR gate, the C port of XOR gate links to each other with the D port of 3d flip-flop, the Q port of 3d flip-flop links to each other with output signal OUT12, the C port of adder links to each other with the B port of XOR gate and the A port of inverter simultaneously, the B port of inverter links to each other with the D port of the 4th trigger, the Q port of the 4th trigger links to each other with output signal OUT34, input clock signal CLK respectively with first d type flip flop, second d type flip flop, 3d flip-flop, the CLK port of four d flip-flop links to each other.
The concrete course of work of DLPF encoder is: the signal DIN (n-1) that first d type flip flop of input signal DIN (n) process trailing edge triggering earlier and second d type flip flop that rising edge triggers obtain postponing a clock cycle, then DIN (n) and DIN (n-1) addition are obtained output signal and position S and carry digit C, will obtain the two-way output signal OUT12 of DLPF encoder and the switch on and off that OUT34 removes to control the D power-like amplifier through the logical circuit that constitutes by XOR gate and inverter with position S and carry digit C again.Obtaining encoding the institute of output signal OUT12 and OUT34 by input signal DIN (n) might situation, and as shown in table 2, wherein the EPOUT12-EPOUT34 in the table 2 is the output signal (Fig. 7) of D power-like amplifier.
Table 2
Through the DLPF encoder encodes, the one, can effectively reduce the D power-like amplifier switch on and off speed so that reduce the power consumption of digital-to-analogue dress parallel operation, the 2nd, in the DLPF encoder be by the transfer function that is input to adder output
Be the effect that this encoder plays a wave digital lowpass filter, so can improve the signal to noise ratio of output signal again.
(4) D power-like amplifier:
D power-like amplifier of the present invention adopts full bridge structure, as shown in Figure 7, be made of drive circuit and D power-like amplifier output stage, wherein drive circuit constitutes the D power-like amplifier output stage by the inverter of level Four cascade successively and is made of M1, M2, four large-sized MOS of M3, M4.OUT12 is connected to the grid of M1 and M2 behind drive circuit, OUT34 is connected to the grid of M3 and M4 behind drive circuit.The difference of EPOUT12 and EPOUT34 is the difference output of D class power amplifier.
This structure can directly apply to digital audio and video signals, need not to be converted to earlier analog signal.Has very high power efficiency.Reduce operating current, prolong battery service time.So the present invention is because D power-like amplifier pipe sizing needs drive circuit greatly.
(5) simulation low-pass filter
Simulation low-pass filter adopts the fertile low pass filter now of common common Bart to get final product, if load is earphone or loud speaker, this simulation low-pass filter can save so.
The example structure of above-mentioned each parts is and illustrates a kind of implementation of the present invention, and in order to limit protection scope of the present invention, each parts promptly of the present invention all can not adopt other known circuit structure of the same function that reaches with each embodiment.
Claims (2)
1. digital to analog converter of optimizing power consumption and output signal-to-noise ratio, adopt Δ ∑ digital to analog converter, comprise the interpolation filter, 1 bit Δ ∑ modulator, D power-like amplifier and the simulation low-pass filter that connect successively, it is characterized in that, also comprise the DLPF encoder that is connected between 1 bit Δ ∑ modulator and the D power-like amplifier; Wherein, the multiple bit digital signal of input is finished by interpolation filter earlier and is risen sampling, finish noise shaping by 1 bit Δ ∑ modulator then, 1 bit code of modulator output is encoded through the DLPF encoder again, the switching manipulation of the 2 bit code control D power-like amplifier of DLPF encoder output, final through the unnecessary out-of-band noise of simulation low-pass filter filtering, realize digital-to-analogue conversion and power amplification.
2. digital to analog converter as claimed in claim 1, it is characterized in that, described DLPF encoder is by four d type flip flops, an adder, an XOR gate, an inverter constitutes, concrete annexation is: input signal DIN (n) links to each other with the D port of first d type flip flop and the B port of adder, the Q port of first d type flip flop links to each other with the D port of second d type flip flop, the Q port of second d type flip flop links to each other with the A port of adder, the S port of adder links to each other with the A port of XOR gate, the C port of XOR gate links to each other with the D port of 3d flip-flop, the Q port of 3d flip-flop links to each other with output signal OUT12, the C port of adder links to each other with the B port of XOR gate and the A port of inverter simultaneously, the B port of inverter links to each other with the D port of the 4th trigger, the Q port of the 4th trigger links to each other with output signal OUT34, input clock signal CLK respectively with first d type flip flop, second d type flip flop, 3d flip-flop, the CLK port of four d flip-flop links to each other.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103107813A (en) * | 2012-11-13 | 2013-05-15 | 长沙景嘉微电子股份有限公司 | Voice frequency digital-to-analog converter (DAC) circuit with Class-AB output |
| CN104202052A (en) * | 2014-08-29 | 2014-12-10 | 辽宁工程技术大学 | Sigma-Delta modulator self-adaptive mixing optimization method for improving signal to noise ratio |
| CN104485958A (en) * | 2014-11-07 | 2015-04-01 | 绵阳市维博电子有限责任公司 | Analog-to-digital converter output signal processing system and method |
| CN106817138A (en) * | 2017-01-09 | 2017-06-09 | 东南大学 | A kind of radio frequency sending set and its signal generating method |
| CN108871385A (en) * | 2017-05-12 | 2018-11-23 | 西门子公司 | Encoder, motor, encoder data processing method and storage medium |
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| US20060146956A1 (en) * | 2005-01-04 | 2006-07-06 | Jae-Wan Kim | RF transmitter for efficiently compensating output power variation due to temperature and process |
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| US20060146956A1 (en) * | 2005-01-04 | 2006-07-06 | Jae-Wan Kim | RF transmitter for efficiently compensating output power variation due to temperature and process |
| CN101741389A (en) * | 2009-12-21 | 2010-06-16 | 西安电子科技大学 | Segmented current-steering digital-to-analog converter |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103107813A (en) * | 2012-11-13 | 2013-05-15 | 长沙景嘉微电子股份有限公司 | Voice frequency digital-to-analog converter (DAC) circuit with Class-AB output |
| CN103107813B (en) * | 2012-11-13 | 2015-04-01 | 长沙景嘉微电子股份有限公司 | Voice frequency digital-to-analog converter (DAC) circuit with Class-AB output |
| CN104202052A (en) * | 2014-08-29 | 2014-12-10 | 辽宁工程技术大学 | Sigma-Delta modulator self-adaptive mixing optimization method for improving signal to noise ratio |
| CN104202052B (en) * | 2014-08-29 | 2017-06-23 | 辽宁工程技术大学 | A kind of Sigma Delta modulator ADAPTIVE MIXED optimization methods for improving signal to noise ratio |
| CN104485958A (en) * | 2014-11-07 | 2015-04-01 | 绵阳市维博电子有限责任公司 | Analog-to-digital converter output signal processing system and method |
| CN104485958B (en) * | 2014-11-07 | 2017-09-22 | 绵阳市维博电子有限责任公司 | A kind of analog-digital converter output signal processing system and method |
| CN106817138A (en) * | 2017-01-09 | 2017-06-09 | 东南大学 | A kind of radio frequency sending set and its signal generating method |
| CN108871385A (en) * | 2017-05-12 | 2018-11-23 | 西门子公司 | Encoder, motor, encoder data processing method and storage medium |
| CN108871385B (en) * | 2017-05-12 | 2021-09-07 | 西门子公司 | Encoder, motor, encoder data processing method, and storage medium |
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Application publication date: 20110511 |