CN102074551A - 半导体装置封装件及其制造方法 - Google Patents

半导体装置封装件及其制造方法 Download PDF

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CN102074551A
CN102074551A CN2010101619595A CN201010161959A CN102074551A CN 102074551 A CN102074551 A CN 102074551A CN 2010101619595 A CN2010101619595 A CN 2010101619595A CN 201010161959 A CN201010161959 A CN 201010161959A CN 102074551 A CN102074551 A CN 102074551A
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semiconductor device
grounding assembly
electromagnetic interference
packaging body
electrical
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CN102074551B (zh
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邱基综
廖国宪
易维绮
陈郁琪
范振铨
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体装置封装件及其制造方法。一实施例中的半导体装置封装件包括半导体装置、封装体、一组重新分配层及电磁干扰遮蔽。封装体覆盖半导体装置的侧表面、封装体的下表面及半导体装置的下表面。重新分配层邻近于前表面而配置并包括接地组件。接地组件包括连接表面，且连接表面电性暴露邻近于此组重新分配层的至少一侧表面之处。电磁干扰遮蔽邻近于封装体而配置并电性连接接地组件的连接表面。接地组件提供用以将入射至电磁干扰遮蔽的电磁辐射接地的电性路径。

Description

半导体装置封装件及其制造方法
技术领域
本发明是有关于一种半导体装置封装件及其制造方法，且特别是有关于一种具有电磁干扰遮蔽的晶圆级半导体装置封装件及其制造方法。
背景技术
市场上对于小尺寸及高处理速度的需求渐增，在某种程度上亦驱使半导体装置日益复杂。虽然小尺寸及高处理速度的半导体装置具有其优点，同时亦带来了其它的问题。
在已知晶圆级封装工艺中，晶圆内的半导体装置于切割晶圆的步骤前进行封装。因此，已知的晶圆级封装受到扇入配置(fan-in configuration)的限制，亦即半导体装置封装件的电性接点(electrical contacts)及其它组件受到由半导体装置的边缘所定义的区域的限制。配置于半导体装置的边缘外的任何组件通常无法被支持，且此些组件通常于切割晶圆的步骤即被移除。当装置的尺寸缩小时，扇入配置的限制的问题更显得严重。
此外，高频率速度(clock speed)可能使得讯号准位(signal level)间的转态(transition)更为频繁，亦即可能造成较高频率或较短波长的高准位电磁辐射。电磁辐射可从来源半导体装置发射出，且可入射至邻近的半导体装置。当邻近的半导体装置的电磁辐射准位够高时，此些放射可能反过来影响来源半导体装置的运作。此种现象有时称为电磁干扰(electromagnetic interference，EMI)。由于小尺寸的半导体装置在整体电子系统中的半导体装置密度较高，因而可能使得电磁干扰问题更为严重，进而造成邻近的半导体装置具有不必要的高准位的电磁辐射。
由以上叙述可知，发展出具有电磁干扰遮蔽的晶圆级半导体封装件及其方法具有相当的需求性。
发明内容
本发明有关于一种具有电磁干扰遮蔽的晶圆级半导体装置封装件。一实施例中，半导体装置封装件包括半导体装置、封装体、一组重新分配层及电磁干扰遮蔽。半导体装置具有下表面、邻近半导体装置的边缘配置的数个侧表面并包括接触垫。接触垫邻近半导体装置的下表面配置。封装体覆盖半导体装置的侧表面并封装体具有上表面、下表面及数个侧表面。封装体的侧表面邻近封装体的边缘配置。封装体的下表面及半导体的下表面定义一前表面。重新分配层邻近前表面配置且具有数个侧表面并包括接地组件。重新分配层的侧表面邻近重新分配层的边缘配置。接地组件包括连接表面，连接表面邻近重新分配层的该些侧表面中至少一者暴露出，以作为电性连接之用。电磁干扰遮蔽邻近封装体的上表面及封装体的侧表面配置。电磁干扰遮蔽电性连接于接地组件的连接表面。接地组件提供一电性路径，以将发生在电磁干扰遮蔽的电磁放射放电至接地端。
另一实施例中，半导体装置封装件包括半导体装置、封装体、重新分配单元及电磁干扰遮蔽。半导体装置包括主动表面。封装体覆盖半导体装置，使得半导体装置的主动表面暴露出，以作为电性连接之用。封装体包括外部表面。重新分配单元包括介电层、电性走线及接地组件。介电层邻近半导体装置的主动表面配置并定义数个开口。介电层的开口对齐于半导体装置的主动表面。电性走线沿着介电层延伸并透过由介电层所定义的该些开口的一者电性连接于半导体装置的主动表面。接地组件沿着介电层延伸并包括侧表面。接地组件的侧表面邻近重新分配单元的边缘配置。电磁干扰遮蔽邻近封装体的外部表面配置并电性连接于接地组件的侧表面。接地组件提供一电性路径，以将发生在电磁干扰遮蔽的电磁放射放电至接地端。
本发明有关于一种具有电磁干扰遮蔽的晶圆级半导体装置封装件的制造方法。一实施例中，此制造方法包括下列步骤。提供具有主动表面的半导体装置；涂布封胶材料以形成封胶结构，封胶结构覆盖半导体装置，半导体装置的主动表面中至少一部份从封胶材料中暴露出；形成重新分配结构于邻近于半导体装置的主动表面之处。重新分配结构包括电性连接部，电性连接部侧向地延伸于重新分配结构中；形成穿透封胶结构与重新分配结构的切割狭缝，切割狭缝对齐于重新分配结构。如此一来，重新分配结构被分割以形成重新分配单元，封胶结构被分割以形成包括外部表面的封装体且电性连接部的残留部成为具有暴露的连接表面的接地组件；涂布电磁干扰涂层至封装体的外部表面及接地组件的连接表面，以形成电磁干扰遮蔽。
为让本发明的上述内容能更明显易懂，下文特举一较佳实施例，并配合所附图式，作详细说明如下：
附图说明
图1绘示依照本发明的实施例的晶圆级半导体装置封装件的立体图；
图2绘示图1的封装件沿着A-A线的剖面图；
图3绘示图1的封装件的部份放大剖面图；
图4绘示依照本发明的另一实施例的晶圆级半导体装置封装件的剖面图；
图5绘示依照本发明的另一实施例的晶圆级半导体装置封装件的剖面图；
图6绘示依照本发明的另一实施例的晶圆级半导体装置封装件的剖面图；
图7A至图7K绘示依照本发明的实施例的晶圆级半导体封装件的制造方法；及
图8A至图8B绘示依照本发明的另一实施例的图5的封装件的制造方法。
主要组件符号说明：
100、400、500、600：半导体装置封装件
102、402a、402b、402c、502、602a、602、602c：半导体装置
104：半导体装置的下表面
106：半导体装置的上表面
108、110：半导体装置的侧表面
112a、112b、412a、412b、412c、412d、512a、512b、612b、612c、612d：接触垫
114、414、514、614：封装体
116：封装体的下表面
118：封装体的上表面
120、122：封装体的侧表面
124、424、524、624：重新分配单元
126：重新分配单元的下表面
128：重新分配单元的上表面
130、132：重新分配单元的侧表面
134、136、536、716、726、808：介电层
138、720、814：导电层
140a、140b、142a、142b、560、810a、810b、810c：介电层的开口
144a、144b、444a、444b、444c、444d、544a、544b、644a、644b、644c、644d：电性接点
146a、146b、446a、446b、546a、546b、646a、646b：电性连接部
148a、148、448b、448c、448d、548b、648b、648c、648d、816：导孔
150a、150、450b、450c、450d、550b、650b、650c、650d：电性走线
152、452、552、652：接地部份
154、454、554、654：电磁干扰遮蔽
156：电磁干扰遮蔽的上部
158：电磁干扰遮蔽的侧部
300：电磁干扰遮蔽的内层
302：电磁干扰遮蔽的外层
700、738：载具
702、736：胶带
704：载具的上表面
706：封胶材料
708、804：封胶结构
710、802：封胶结构的上表面
712：封胶结构的下表面
714、800：介电材料
718、724、812：导电材料
722、818：虚线
728：重新分配结构
730：刀具
732：切割狭缝
734：电磁干扰涂层
806、806’：主动表面
S1、S2、S1’、S2’、S2”’：连接表面
具体实施方式
以下的定义应用于本发明的实施例的部份方面。此处可同样地扩充此些定义。
除非特别且清楚地指出，否则文中所使用的词汇「一」、「一个」及「此」包括数个的形式。因此，举例来说，除非另外清楚地说明，否则一接地组件可包括数个接地组件。
在此处所用的词汇「组」指一或多个组件的集合。因此，举例来说，一组膜层可包括一单一膜层或数个膜层。一组的组件可代表此组中的构件。一组的组件可为相同或相异。在某些例子中，一组的组件可具有一或多个共同的特性。
此处所用的词汇「相邻」指接近或紧邻。相邻的组件可彼此分离或可实际上接触或直接彼此接触。在某些例子中，相邻的组件可彼此连接或可一体成形。
此处所用的相对的词汇，例如是「内」、「内部」、「外」、「外部」、「顶」、「底」、「前」、「后」、「上」、「向上」、「下」、「向下」、「垂直」、「垂直地」、「侧向」、「侧向地」、「之上」及「之下」，指一组组件中彼此的方位，例如是根据图式的方位。然而，但在制造或使用时并不限定为特定的方位。
此处所用的词汇「相连」、「被连接」及「连接」指操作上的耦接或结合。相连接的组件可直接地彼此耦接或可间接地彼此耦接，例如是透过另一组组件而耦接。
此处所用的词汇「实质上地」及「实质上」指达到相当的程度或范围。当与事件或情况并用时，此些词汇可用以代表事件或情况准确地发生，或代表事件或情况相当接近地发生，例如是代表此处所述的制造程序的一般的误差范围。
此处所用的词汇「导电」及「导电性」指传导电流的能力。导电材料一般指对于电流的流动具有很小或无阻抗的材料。导电性的单位的一为每公尺的西门数(S·m-1)。一般来说，导电材料为导电性约大于104S·m-1的材料，例如是至少约为105S·m-1或至少约为106S·m-1。材料的导电性有时会随着温度变化。除非特别说明，材料的导电性定义为室温下的导电性。
图1及图2绘示依照本发明的实施例的晶圆级半导体装置封装件100。具体地来说，图1绘示封装件100的立体图，而图2绘示封装件100沿着图1的A-A线的剖面图。
图示的实施例中，封装件100的侧面实质上为平面，并具有实质上垂直的方位，用以定义实质上沿着封装件100的整个边缘延伸的侧向形状。经由减少或缩小封装件100的占用面积(footprint area)，此垂直的侧向形状减少了整体半导体封装件的尺寸。。然而，封装件100的侧向形状一般来说可为其它形状，例如是曲面、斜面、阶梯状或为粗糙材质。
请参照图2，封装件100包括半导体装置102。半导体装置102具有下表面104、上表面106与侧表面108及110。侧表面108及110邻近于半导体装置102的边缘，并于下表面104及上表面106间延伸。图示的实施例中，表面104、106、108及110皆实质上为平面，而侧表面108及110垂直于下表面104及上表面106。但可了解的是，在其它的实施方式中，表面104、106、108及110亦可为其它形状或方位。如图2所示，上表面106为半导体装置102之后表面，而下表面104为半导体装置102的主动表面(active surface)半导体装置102的接触垫112a及112b邻近于下表面104而配置。接触垫112a及112b提供半导体装置102输入及输出的电性连接，而接触垫112a及112b中的其中之一为接地的接触垫。举例来说，接触垫112b可为接地的接触垫。图标的实施例中，半导体装置102为半导体芯片。但可了解的是，一般来说半导体装置102可为任何主动组件、被动组件或其组合。当图2绘示其中一种半导体装置时，可了解的是，本发明的其它实施方式亦可包括其它的半导体装置。
如图2所示，封装件100亦包括邻近于半导体装置102而配置的封装体114。封装体114及重新分配单元124实质上覆盖或包覆半导体装置102，用以提供机械性的稳定及抗氧化、潮湿及其它环境条件的保护。重新分配单元124将于之后更详细地说明。图示的实施例中，封装体114实质上覆盖半导体装置102的上表面106及侧表面108与110，且封装体114实质上暴露出或无覆盖半导体装置102的下表面104。然而，可了解的是，封装体114所覆盖的范围可不同于图2中所示。举例来说，封装体114可实质上仅覆盖侧表面108及110，且封装体114可实质上无覆盖下表面104及上表面106。
如图2所示，封装体114由封胶材料所形成，且封装体114具有下表面116及外部表面。封装体114的外部表面包括上表面118及侧表面120及122。侧表面120及122邻近于封装体114的边缘而配置，并于下表面116及上表面118之间延伸。图示的实施例中，表面116、118、120及122实质上为平面，而侧表面120及122实质上垂直于下表面116或上表面118。在其它的实施方式中，表面116、118、120及122的形状及方位可为不同，如图2所示，由侧表面120及122所定义的封装体114的边缘可大于半导体装置102的边缘，使得封装件100具有扇出配置(fan-out configuration)。换言之，封装件100的组件可配置于由半导体装置102所定义的边缘内及外。此外，封装体114的下表面116实质上对齐于半导体装置102的下表面104，或与半导体装置102的下表面104共平面，藉以定义实质上为平面的一前表面。更具体地来说，当下表面104实质上暴露于外或无遮盖物时可进行对齐，例如是经由减少或最小化接触垫112a及112b的覆盖范围。在其它实施方式中，可了解的是下表面104及116的对齐方式可不同于图2的方式，而下表面104至少部份暴露出来，使接触垫112a及112b可提供输入及输出的电性连接。此外，亦可了解的是，封装体114可包括支撑结构及封胶材料，或以支撑结构取代封胶材料。举例来说，封装体114可包括一结构或中介层(interposer)，可由玻璃、硅、金属、金属合金、高分子材料或其它适合的结构性材料所形成。
请参照图2，封装件100亦包括重新分配单元124。重新分配单元124邻近于由下表面104及116所定义的前表面配置。重新分配单元124电性连接于半导体装置102并提供电性路径(electrical pathway)、机械稳定性及抗环境条件的保护。如图2所示，重新分配单元124包括下表面126、上表面128及侧表面130与132。侧表面130与132邻近于重新分配单元124的边缘而配置，并于下表面126及上表面128间延伸。在图示的实施例中，表面126、128、130及132实质上为平面，而侧表面130及132实质上垂直于下表面126或上表面128。可了解的是，在其它的实施方式中，表面126、128、130及132的形状与方位可为不同。由侧表面130及132所定义并由封装体114所支撑的重新分配单元124的边缘大于半导体装置102的边缘，使得封装件100形成扇出配置。再者，重新分配单元124的侧表面130及132实质上分别对齐于封装体114的侧表面120及122，或与封装体114的侧表面120及122共平面。更具体地来说，由于侧表面130及132实质上暴露于外或无遮蔽物，使重新分配单元124的侧表面130及132可分别实质上对齐于封装体114的侧表面120及122，例如是经由减少或最小化侧表面130及132的覆盖范围。在其它的实施方式中，可了解的是侧表面120、122、130、132的对齐方式可不同于图2的对齐方式，而至少部份的侧表面130及132暴露出来，以作为电性连接的用。在某些实施方式中，重新分配单元124的厚度TR，亦即重新分配单元124的下表面126及上表面128间的距离，可约介于10微米(μm)至50微米之间，例如是介于约12微米至50微米之间，或介于约14微米至42微米之间。
请继续参照图2，在其它的实施方式中，重新分配单元124可包括其它结构。在图标的实施例中，重新分配单元124具有数层且包括一对介电层134及136与一导电层138。至少部份的导电层138被介电层134及136所夹住。一般而言，介电层134及136可由介电材料所形成，且介电材料可为聚合物或非聚合物。举例来说，介电层134及136中至少一者为聚亚酰胺(polyimide)、聚苯恶唑(polybenzoxazole)、苯环丁烯(benzocyclobutene)或其组合。介电层134及136可由相同或不同的介电材料所形成。在某些实施方式中，介电层134及136中至少一者可由感光(photoimageable)或光敏(photoactive)的介电材料形成，经由使用微影工艺以进行图案化的程序，进而减少制作成本及时间。介电层134及136的厚度TD可约介于1微米至12微米之间，例如是介于约1微米至10微米之间，或介于约2微米至6微米之间。虽然图2中绘示两介电层，可了解的是其它实施方式中可包括更多或更少的介电层。
如图2所示，介电层136定义开口140a及140b，且开口140a及140b的位置及尺寸使至少部份的接触垫122a及122b分别暴露于外。介电层134定义开口142a及142b，且开口142a及142b的位置分别使得至少部份的导电层138暴露于外。开口142a及142b的尺寸用以容纳电性接点144a及144b。电性接点144a及144b提供封装件100输入及输出的电性连接，且电性接点144a及144b中至少一个透过导电层138电性连接至半导体装置102。图示的实施例中，电性接点144a及144b为焊料凸块(solder bumps)，且电性接点144a及144b中至少一个为电性连接至接地接触垫112b的接地电性接点。举例来说，电性接点144b为接地的电性接点。根据封装件100的扇出配置，电性接点144a及144b往侧面的方向配置于半导体装置102的边缘的外侧。但可了解的是，一般而言电性接点144a及144b亦往侧面方向配置于半导体装置102的边缘内或/且外。如此一来，封装件100的扇出配置在配置及隔开电性接点144a及144b上具有更佳的弹性，并可减少与半导体装置102的接触垫112a及112b的配置及间隔的依赖性。
导电层138做为半导体装置102的接触垫112a及112b的重新分配网络。依照封装件100的扇出配置，导电层138于重新分配单元124中及半导体装置102的边缘外侧向延伸。如图2所示，导电层138包括电性连接部(electrical interconnect)146a及146b。电性连接部146a电性连接接触点112a及电性接点144a，电性连接部146b电性连接接地的接触垫112b及接地的电性接点144b。更具体地来说，电性连接部146a及146b包括位于开口140a及140b中的部份以及沿着介电层136的下表面延伸的另一部份。位于开口140a及140b中的部份电性连接至接触垫112a或112b的导孔148a或148b，另一部份则为电性连接至电性接点144a或144b的电性走线(electrical trace)150a或150b。一般来说，电性连接部146a及146b可由金属、金属合金、金属或金属合金散布于其中的基质(matrix)或其它适合的导电材料所形成。举例来说，电性连接部146a及146b中至少一个可由铝、铜、钛或其组合所形成。电性连接部146a及146b可由相同或相异的导电材料所形成。在某些实施方式中，电性连接部146a及146b的厚度TE可约介于1微米至12微米之间，例如是介于约1微米至10微米之间，或介于约2微米至6微米之间。虽然图2仅绘示一导电层，但其它实施方式亦可包括其它导电层。
图示的实施例中，电性连接部146b亦用以做为接地组件，以减少电磁干扰。电性连接部146b包括接地部份152，且接地部份152邻近重新分配单元的边界而配置。如图2所示，接地部份152围绕重新分配单元124的至少部份边缘而延伸。更具体地来说，根据以下所述的制造程序，电性连接部146b为接地环(groundingring)或一组接地条(grounding strip)。请参照图2，接地部份152包括连接表面S1及S2，且连接表面S1及S2为背对封装件100内部的侧表面并邻近于重新分配单元124的边缘而配置。更具体地来说，连接表面S1及S2实质上于重新分配单元124的边缘处暴露出来或无遮蔽物，并分别于邻近侧表面130及132之处暴露出来，以作为电性连接之用。经由部份或全部延伸于重新分配单元124的边缘，接地部份152提供面积较大的连接表面S1及S2，进而提供具有更佳的可靠度及效能的电性连接，以减少电磁干扰。然而，可了解的是，在其它的实施方式中，接地部份152环绕重新分配单元124的边缘的范围可为不同。亦可了解的是，其它实施方式可包括数个不连续的接地组件，且连接表面S1及S2指此些接地组件的侧表面。
如图1及图2所示，封装件100更包括电磁干扰遮蔽(electromagneticinterference shield)154。电磁干扰遮蔽154邻近于封装体114的外部表面、接地部份152的连接表面S1及S2以及重新分配单元124的侧表面130及132。电磁干扰遮蔽154由导电材料所形成，且实质上环绕封装件100内的半导体装102，以提供防止电磁干扰的保护。在图示的实施例中，电磁干扰遮蔽154包括上部156及侧部158。侧部158实质上围绕封装体114的整个边缘延伸，并定义封装件100的垂直侧向形状。如图2所示，侧部158由上部156向下延伸，并沿着重新分配单元124的侧表面130及132延伸。此外，侧部158的下端实质上对齐于重新分配单元124的下表面126，或与下表面126共平面。然而，可了解的是，在其它实施方式中，侧部158的范围及其下端对齐下表面126的方式可为不同。
如图2所示，电磁干扰遮蔽154电性连接至电性连接部146b的接地部份152的连接表面S1及S2。当由封装件100的内部发出的电磁辐射入射至电磁干扰遮蔽154时，至少一部份的电磁辐射可透过电性连接部146b而被有效地接地，藉以减少穿过电磁干扰遮蔽154的电磁辐射的程度，并减少对邻近的半导体装置的损害。同样地，当由邻近的半导体装置发出的电磁辐射入射至电磁干扰遮蔽154时，亦会发生同样的接地作用，以减少半导体装置102于封装件100内的电磁干扰。当运作时，封装件100可配置于印刷电路板上，并透过电性接点144a及144b电性连接至印刷电路板。如上所述，电性接点144b为接地的电性接点，且接地的电性接点144b可电性连接至由印刷电路板提供的接地电压。透过包括电性连接部146b及接地的电性接点144b的电性路径可将入射至电磁干扰遮蔽154的电磁辐射放电至接地端。由于电性连接部146b亦电性连接至半导体装置102的接地的接触垫112b，电性连接部146b可降低电磁干扰并使半导体装置102接地，进而保护封装件100内的重要区域。然而，可了解的是，其它的实施方式可包括用以降低电磁干扰的专用的接地组件。由于电磁干扰遮蔽154的下端实质上对齐于重新分配单元124的下表面126，因此，下端可电性连接至由印刷电路板提供的接地电压，进而提供另一种将有害的电磁辐射放电至接地端的替代电性路径。
在图示的实施例中，电磁干扰遮蔽154为覆盖(conformal)遮蔽物，且为一组膜层或薄膜。其优点在于电磁干扰遮蔽154可在不使用黏着剂的情况下邻近并直接接触封装体114的外部表面，进而提升对于温度、湿度及其它环境条件的可靠度及抵抗性。此外，电磁干扰遮蔽154的覆盖特性使得相似的电磁干扰遮蔽及相似的制造程序可快速地应用于不同尺寸及形状的半导体装置封装件，因而降低应用于不同封装件的制造成本及时间。在某些实施方式中，电磁干扰遮蔽154的厚度可介于约1微米至500微米之间，例如是介于约1微米至100微米之间，介于约1微米至50微米之间，或介于约1微米至10微米之间。厚度较薄的电磁干扰遮蔽154降低了封装件的整体尺寸，因而成为所述的实施例的优点。
图3绘示图1及图2的封装件100的部份放大剖面图。更具体地来说，图3绘示邻近于封装体114而配置的电磁干扰遮蔽154的一种实施方式。
如图3所示，电磁干扰遮蔽154为多层的结构并包括内层300及外层302。内层300邻近于封装体114而配置，且外层302邻近内层300配置并暴露于封装件100的外部。一般来说，内层300及外层302可由金属、金属合金、金属或金属合金散布其中的基质、或为其它适合的导电材料所形成。举例来说，内层300及外层302中至少一个可由铝、铜、铬、锡、金、银、镍、不锈钢或其组合而形成。内层300及外层302可由相同或相异的导电材料所形成。举例来说，内层300及外层302可由例如是镍的金属所形成。在某些例子中，内层300及外层302可由不同的导电材料所形成，以提供互补的功能。举例来说，内层300可由具有高导电性的金属所形成以提供电磁干扰遮蔽作用，此处的高导电性的金属例如是铝、铜、金或银，用。另一方面，外层302可由具有导电性略低的金属所形成以保护内层300抵抗氧化、湿度及其它环境条件，此处的导电性略低的金属例如是镍。在此情况下，外层302可提供电磁干扰遮蔽作用，亦可具有保护的功能。虽然图3中为两层的结构，可了解的是，其它实施方式可包括较多或较少膜层。
图4绘示依照本发明的另一实施例的晶圆级半导体装置封装件400的剖面图。如图4所示，封装件400包括封装体414、重新分配单元424、电性接点444a、444b、444c及444d与电磁干扰遮蔽454。部份的封装件400与前述的图1中的封装件100相似，因此不重复叙述。
请参照图4，封装件400为多装置配置，并包括多个半导体装置402a、402b及402c。在图标的实施例中，半导体装置402a及402c为半导体芯片，且半导体装置402b为被动组件，例如是电阻器、电容器或电感器。虽然图4包括三个半导体装置，可了解的是，其它实施方式可包括较多或较少半导体装置。
请继续参照图4，重新分配单元424包括电性连接部446a及446b。电性连接部446a电性连接于半导体装置402a的接触垫412a与电性接点444a。电性连接部446b电性连接半导体装置402a、402b与402c的接地的接触垫412b、412c及412d至电性接点444d，且电性接点444d为接地的电性接点。更具体地说，电性连接部446b包括导孔448b、448c与448d与电性走线450b、450c及450d。导孔448b、448c与448d分别电性连接至接触垫412b、412c及412d。电性走线450b于导孔448b及448c间延伸，并电性连接导孔448b及448c。电性走线450c于导孔448c及448d间延伸，并电性连接导孔448c及448d。电性走线450d于导孔448d及接地部份452间延伸，并电性连接导孔448d及接地部份452。此外，电性走线450d亦电性连接至接地的电性接点444d。
图示的实施例中，接地部份452围绕至少一部份的重新分配单元424的边缘而延伸。更具体地来说，依照后述的制造程序，接地部份452为接地环或一组接地条。请参照图4，接地部份452包括连接表面S1’及S2’。连接表面S1’及S2’为背向封装件400的内部的侧表面且实质上从重新分配单元424暴露出来。经由环绕部份或全部的重新分配单元424的边缘，接地部份452提供面积较大的连接表面S1’及S2’，进而提升用以减少电磁干扰的电性连接部的可靠度及效率。然而，可了解的是，在其它的实施方式中，环绕重新分配单元424的边缘的接地部份的范围可为不同。
图5绘示依照本发明的另一实施例的晶圆级半导体装置封装件500的剖面图。如图5所示，封装件500包括半导体装置502、封装体514、重新分配单元524、电性接点544a及544b与电磁干扰遮蔽554。部份的封装件500与上述的图1至图3中的封装件100相似，因此不再重复叙述。
请参照图5，重新分配单元524包括电性连接部546a及546b。电性连接部546a电性连接半导体装置502的接触垫512a至电性接点544a。电性连接部546b电性连接于半导体装置502的接地的接触垫512b及电性接点544b，且电性接点544b为接地的电性接点。更具体地来说，电性连接部546b包括导孔548b及电性走线550b。导孔548b电性连接至接地的接触垫512b。电性走线550b于导孔548b及接地部份552间延伸，并电性连接导孔548b及接地部份552。此外，电性走线550b亦电性连接至接地的电性接点544b。
图示的实施例中，接地部份552为接地的导孔。更具体地说，依照后述的制造程序，接地部份552为接地的导孔的残留部。接地部份552配置于由重新分配单元524的介电层536所定义的开口560中。请参照图5，接地部份552由导电材料所形成，且导电材料实质上填满开口560，并实质上垂直地贯穿介电层536的整个厚度。然而，可了解的是，在其它的实施方式中，接地部份552的范围可为不同，且其它的实施方式可包括接地环或一组接地条，用以取代接地部份552或与接地部份552并用。请继续参照图5，接地部份552包括连接表面S2”。连接表面S2”为背向封装件500内部的侧表面，且实质上于重新分配单元524的边缘暴露出来或无遮蔽物。较佳地，接地部份552提供面积较大的连接表面S2”，进而提升用以降低电磁干扰的电性连接部的可靠度及效率。在某些实施方式中，接地部份552的高度H及宽度W可介约于2微米至24微米之间，例如是介于约5微米至15微米之间，或介于约8微米至12微米之间。
图6绘示依照本发明的另一实施例的晶圆级半导体装置封装件600的剖面图。如图6所示，封装件600包括封装体614、重新分配单元624、电性接点644a、644b、644c及644d与电磁干扰遮蔽654。部份的封装件600与上述的图1至图3中的封装件100以及图5的封装件500相似，因此不重复叙述。
请参照图6，封装件600为多层结构并包括数个半导体装置602a、602及602c。图标的实施例中，半导体装置602a及602c为半导体芯片，而半导体装置602b为被动组件，例如是电阻器、电容器或电感器。虽然图6中包括三个半导体装置，可了解的是，其它的实施方式可包括较多或较少半导体装置。
请继续参照图6，重新分配单元624包括电性连接部646a及646b。电性连接部646a电性连接于半导体装置602a的接触垫612a及电性接点644a。电性连接部646b电性连接半导体装置602a、602b及602c的接地的接触垫612b、612c及612d至电性接点644d，且电性接点644d为接地的电性接点。更具体地来说，电性连接部646b包括导孔648b、648c及648d与电性走线650b、650c、650d。导孔648b、648c及648d分别电性连接至接地的接触垫612b、612c及612d。电性走线650b于导孔648b与648c之间延伸并电性连接于导孔648b及648c。电性走线650c于导孔648c与648d之间延伸，并电性连接导孔648c及648d。电性走线650d于导孔648d与接地部份652之间延伸并电性连接于导孔648d及接地部份652。电性走线650d亦电性连接至接地的电性接点644d。图示的实施例中，接地部份652为接地的导孔。更具体地来说，依照后述的制造程序，接地部份652为接地的导孔的残留部。请参照图6，接地部份652包括连接表面S2”’。连接表面S2”’为背向封装件600的内部的侧表面，且实质上于重新分配单元624之处暴露出来或无遮蔽物。较佳地，接地部份652提供面积较大的连接表面S2”’，进而提升用以降低电磁干扰的电互连接的可靠度及效率。
图7A至图7K绘示依照本发明的实施例的晶圆级半导体封装件的制造方法。为了方便说明，后述的制造方法参照图1至图3而说明。然而，可了解的是，制造方法亦可形成其它的半导体装置封装件，例如是图4的封装件400。
请参照图7A，提供载具700，且胶带702邻近于载具700的上表面704而配置。胶带702可为单面或双面胶带。胶带702用以固定一组件，使该组件彼此分隔适当的距离并使接续的制造程序可于邻近于载具700的组件上进行。
当提供载具700之后，数个半导体装置可配置于邻近胶带702之处，使得部份的制造程序可快速地平行或连续进行。半导体装置包括半导体装置102及邻近的半导体装置102’。半导体装置102及102’于晶圆中形成并彼此相隔特定的距离，之后对晶圆进行分割程序以分离半导体装置102及102’。半导体装置102及102’与其它的半导体装置可以数组的方式排列于胶带702上，数个半导体装置以二维的方式排列。或者，数个半导体装置可为条状配置，亦即半导体装置线性地连续排列。图标的实施例中，与半导体装置在晶圆中的最邻近间距(nearest-neighbor spacing)相较，半导体装置102及102’于载具700上的排列使半导体装置彼此间具有较大的最邻近间距，促使制成的封装件可形成扇出配置。然而，可了解的是，其它的实施方式中，半导体装置102及102’之间距可为不同。为了方便说明，后述的制造程序主要地参照半导体装置102及相关组件而叙述。然而，制造程序亦可用以制造其它半导体装置及相关组件。
接着，如图7B所示，封胶材料706涂布于载具700上，藉以实质上覆盖或包覆半导体装置102及102’。由于半导体装置102及102’排列于胶带702上，封胶材料706可实质上暴露半导体装置102及102’的主动表面104及104’。举例来说，封胶材料706可包括酚醛基树脂(Novolac-based resin)、环氧基树脂(epoxy-basedresin)、硅基树脂(silicone-based resin)或其它适当的包覆剂。封胶材料706亦可包括适当的填充剂，例如是粉状的二氧化硅。可利用数种封装技术涂布封胶材料706，例如是压缩成型(compression molding)、注射成型(injection molding)或转注成型(transfer molding)。当涂布封胶材料706之后，封胶材料706被硬化或固化，例如是经由降低温度至封胶材料706的熔点的下，藉以形成封胶结构708。请参照图7B，封胶结构708及被包覆的半导体装置102及102’可彼此适当地分隔，促使封装件形成扇出配置。在后续的分割程序中，为了使得封胶结构708得以适当地配置，可于封胶结构708中形成基准标志(fiducial marks)，例如是使用激光标记。
当封胶结构708形成后，封胶结构708及被包覆的半导体装置102及102’与胶带702分离，并如图7C所示地重新定位至一直立的方位。图标的实施例中，封胶结构708(沿着直立的方位)的上表面710实质上对齐于半导体装置102及102’的主动表面104及104’，或与主动表面104及104’共平面。虽然未绘示于图7C中，可了解的是，在后续的制造过程中，可使用胶带固定封胶结构708(沿着直立的方位)的下表面712。胶带可为单面或双面胶带。
之后，于邻近封胶结构708的上表面710及半导体装置102及102’的主动表面104及104’形成一组重新分配层。请参照图7D，利用数种涂布技术的一种以涂布介电材料714，该些涂布技术例如是印刷(printing)、旋涂(spinning)或喷涂(spraying)。之后，将介电材料714图案化以形成介电层716。图案化的步骤后，介电层716具有对齐于主动表面104及104’的开口。开口140a及140b的位置及尺寸用以暴露出半导体装置102的至少部份的接触垫112a及112b。介电材料714的图案化的步骤可以数种不同的方式完成，例如是微影工艺(photolithography)、化学蚀刻(chemical etching)、激光钻孔(laser drilling)或机械钻孔(mechanicaldrilling)，因此可形成多种形状的开口。开口的形状包括柱状或非柱状，柱状例如是圆柱状、椭圆柱状、方形柱状或矩形柱状，非柱状例如是圆锥状、漏斗状或其它渐缩的形状。可了解的是，形成的开口的侧向边界可为弯曲状或为粗糙的材质。
然后，如图7E及图7F所示，导电材料718可经由数种涂布技术而涂布于介电层716并填入由介电层716定义的开口中，例如是利用化学气相沈积、无电镀法(electroless plating)、电解电镀(electrolytic plating)、印刷、旋涂、喷涂、溅镀(sputtering)或真空沈积法(vacuum deposition)。接着，图案化导电材料718以形成导电层720。由图案化步骤形成的导电层720具有电性连接部。彼此分离的电性连接部沿着介电层716的特定部份延伸，且电性连接部暴露出介电层716的其它部份。将导电材料718图案化的步骤可经由数种方式完成，例如是微影工艺、化学蚀刻、激光钻孔或机械钻孔。
图7G及图7H绘示于图案化的步骤之后的导电层720的两种实施方式的上视图。图7G绘示格状的导电层720。导电层720包括一组实质上平行的条状物与另一组实质上垂直的平行条状物，且两组条状物为相交。图7H绘示平行柱状的导电层720。导电层720包括一组实质上平行的条状物。图7G及图7H中的虚线722代表将于后续切割程序中形成的切割狭缝的方位及位置。可了解的是，图7G及图7H中所绘示的导电层720的特定的实施方式仅作为范例之用，其它的实施方式中可包括不同的形式。
请参照图7I，介电材料724可应用数种涂布技术的一种涂布于导电层720及介电层716的暴露的部份，该些涂布技术例如是印刷、旋涂或喷涂。接着，图案化介电材料724以形成介电层726。由图案化的步骤形成的介电层726具有对齐于导电层720的开口。开口142a及142b的位置用以暴露出至少部份的导电层720，且其尺寸用以容纳焊料凸块。图案化介电材料724的步骤可以数种方式完成，例如是微影工艺、化学蚀刻、激光钻孔或机械钻孔。形成的开口可为数种形状，包括柱状及非柱状。柱状可例如是圆柱壮、椭圆柱状、方形柱状或矩形柱状。非柱状例如是圆锥状、漏斗状或其它渐缩的形状。可了解的是，形成的开口的侧向边界可为弯曲状或粗糙的材质。请参照图7I，介电层726、导电层720及介电层716可称为重新分配结构728。重新分配结构728邻近于封胶结构708的上表面710而配置，并沿着封胶结构708的上表面710及半导体装置102的主动表面104及104’而延伸。
之后，沿着虚线722切割，如图7J所示。图示的实施例使用刀具730进行切割，而形成切割狭缝732。可在切割步骤中使用基准标示辅助对齐刀具730。如此一来，当形成切割狭缝732时，刀具730得以正确地定位。具体地来说，切割狭缝732完全穿过封胶结构708及重新分配结构728，藉以将封胶结构708及重新分配结构728分割为分离单元，此分离单元包括封装体114及重新分配单元124。请继续参照图7J，刀具730侧向地放置并对齐重新分配结构128，使得电性连接部146b可做为接地组件，且连接表面S1及S2从重新分配单元124的边缘暴露出来。在图7G的格状结构的情况下，连接表面S1及S2为接地环的侧表面。在图7H的平行柱状结构的情况下，连接表面S1及S2分别为接地条的侧表面。
接着，如图7K所示，电磁干扰涂层734邻近暴露出的表面而形成，该些暴露出的表面包括封装体114的外部表面、连接表面S1及S2与重新分配单元124的侧表面130及132。电磁干扰涂层734可使用数种涂布技术而形成，例如是化学气相沈积、无电镀法、电解电镀、印刷、旋涂、喷涂、溅镀或真空沈积法。举例来说，电磁干扰涂层734可包括应用无电镀法形成且材料为镍的单一膜层，其厚度至少约5微米，例如是介于约5微米至50微米之间，或例如是介于约5微米至10微米之间。当电磁干扰涂层734为多层结构时，不同膜层可使用相同或不同的涂布技术形成。举例来说，内层可由铜并使用无电镀法形成，外层可由镍并使用无电镀法或电解电镀形成。在另一个例子中，内层(作为基层之用)可由铜并使用溅镀或无电镀法形成，其厚度至少约1微米，例如是介于1微米至50微米之间，或介于约1微米至10微米之间。外层(做为抗氧化层之用)可由不锈钢、镍或铜并使用溅镀法形成，其厚度约不大于1微米，例如是介于约0.01微米至1微米之间，或介于约0.01微米至0.1微米之间。在此些例子中，可在电磁干扰涂层所涂布的表面进行预先处理程序，有助于内层及外层的形成。举例来说，此些预先处理程序可包括表面粗糙化，例如透过化学蚀刻或机械磨蚀法，或形成晶种层(seed layer)。将重新分配单元124及相关组件由胶带736及载具738分离，例如是使用捡放技术(pick-and-place technique)，藉以形成包括电磁干扰遮蔽154的封装件100。
图8A至图8B绘示依照本发明的另一实施例的晶圆级半导体装置封装件的制造方法。为了方便说明，后述的制造程序参考图5的封装件500而叙述。然而，可了解的是，此制造程序亦可类似地用以形成其它的半导体装置封装件，例如是图6的封装件600。此外，部份的制造程序与上述中图7A至图7K的制造程序相同，因而不重复叙述。
请参照图8A，介电材料800涂布于封胶结构804的上表面802以及半导体装置502及邻近的半导体装置502’的主动表面806及806’。之后，图案化介电材料800以形成介电层808。经过图案化之后，介电层808具有对齐于主动表面806及806’的开口。开口810a及810b的位置及尺寸用以暴露半导体装置502的至少部份的接触垫512a及512b。图示的实施例中，介电层808亦具有位于两相邻的半导体装置间的开口，包括开口810c。开口810a、810b及810c可为数种形状，包括柱状及非柱状。柱状例如是圆柱壮、椭圆柱状、方形柱状或矩形柱状。非柱状例如是圆锥状、漏斗状或其它渐缩的形状。可了解的是，开口810a、810b及810c的侧向边界可为弯曲状或为粗糙材质。
然后，如图8B所示，导电材料812涂布于介电层808上并填入由介电层808所定义的开口810a、810b及810c中。接着，图案化导电材料812以形成导电层814。经过图案化的步骤后，导电层814具有电性连接部及间隙。电性连接部沿着介电层808的某些部份延伸。间隙介于暴露介电层808的其它部份的电性连接部之间。图示的实施例中，导电材料812被引入开口810c中，藉以填入开口810c中，因而形成接地的导孔816。开口810c的填充可促使连接表面具有较大的面积，进而提升用以减少电磁干扰的电性连接的可靠度及效率。请继续参照图8B，接着，沿着虚线818进行分割，使得产生的切割狭缝移除部份的接地导孔816，形成具有暴露的连接表面的接地组件。
综上所述，虽然本发明已以一较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。此外，为了应用于特定的条件、材料、物质成分、方法或程序，亦可对于本发明的目的、精神及范围作各种更动与润饰。本发明的保护范围当包括此些更动与润饰。文中揭露的方法按照特定的顺序而叙述。然而，可了解的是，此些步骤可被合并、分割或重新排列，以在不脱离本发明的精神下形成等价的方法。除非特别说明，此些步骤的顺序或群组不可视为本发明的限制。

Claims (17)

1.一种半导体装置封装件，包括：
一半导体装置，具有一下表面及数个侧表面并包括一接触垫，该些侧表面邻近该半导体装置的一边缘而配置，且该接触垫邻近于该半导体装置的该下表面而配置；
一封装体，覆盖该半导体装置的该些侧表面，该封装体具有一上表面、一下表面及数个侧表面，该封装体的该些侧表面邻近于该封装体的一边缘而配置，且该封装体的该下表面及该半导体装置的该下表面定义一前表面；
一组重新分配层，邻近于该前表面而配置，该组重新分配层具有数个侧表面并包括一接地组件，该组重新分配层的该些侧表面邻近于该重新分配层的一边缘而配置，且该接地组件包括一连接表面，该连接表面从邻近该组重新分配层的该些侧表面中至少一者暴露出，以作为电性连接之用；以及
一电磁干扰遮蔽，邻近于该封装体的该上表面及该封装体的该些侧表面配置，该电磁干扰遮蔽电性连接于该接地组件的该连接表面；
其中，该接地组件提供一电性路径，以将发生在该电磁干扰遮蔽的电磁放射放电至接地端。
2.如权利要求1所述的半导体装置封装件，其中该接地组件延伸于该半导体装置的该接触垫与该组重新分配层的该些侧表面中至少一者之间。
3.如权利要求2所述的半导体装置封装件，其中该组重新分配层更具有一下表面，该半导体装置封装件更包括一电性接点，该电性接点邻近于该组重新分配层而的该下表面而配置，且该接地组件电性连接至该电性接点。
4.如权利要求3所述的半导体装置封装件，其中该电性接点侧向地配置于该半导体装置的该边缘。
5.如权利要求1所述的半导体装置封装件，其中该接地组件包括一第一部份及一第二部份，该第一部份电性连接于该半导体装置的该接触垫，而该第二部份邻近该组重新分配层的该边缘配置且该第二部份包括该连接表面。
6.如权利要求5所述的半导体装置封装件，其中该第二部份为一接地环。
7.如权利要求5所述的半导体装置封装件，其中该第二部份为一接地条。
8.如权利要求5所述的半导体装置封装件，其中该第二部份为一接地导孔的一残留部。
9.如权利要求1所述的半导体装置封装件，其中该组重新分配层包括一介电层，该介电层邻近该前表面配置，且该接地组件包括一电性走线，该电性走线沿着该介电层延伸。
10.如权利要求1所述的半导体装置封装件，其中该电磁干扰遮蔽包括一侧部，该侧部沿着该组重新分配层的该些侧表面延伸。
11.如权利要求10所述的半导体装置封装件，其中该组重新分配层具有一下表面，该侧部的一下端实质上对齐于该组重新分配层的该下表面。
12.一半导体装置封装件，包括：
一半导体装置，包括一主动表面；
一封装体，覆盖该半导体装置并使该半导体装置的该主动表面暴露出，以作为电性连接之用，且该封装体包括数个外部表面；
一重新分配单元，包括一介电层、一电性走线及一接地组件，该介电层邻近于该半导体装置的该主动表面配置并定义数个开口，该些开口对齐于该半导体装置的该主动表面，该电性走线沿着该介电层延伸并透过由该介电层所定义的该些开口中的一者电性连接于该半导体装置的该主动表面，该接地组件沿着该介电层延伸且包括一侧表面，该接地组件的该侧表面邻近该重新分配单元的一边缘配置；以及
一电磁干扰遮蔽，邻近于该封装体的该些外部表面配置并电性连接于该接地组件的该侧表面；
其中，该接地组件提供一电性路径，以将发生在该电磁干扰遮蔽的电磁放射放电至接地端。
13.如权利要求12所述的半导体装置封装件，其中该接地组件包括一部份，该部份邻近该重新分配单元的该边缘而配置，该部份包括该侧表面且该部份为一接地环、一接地条与一接地导孔的一残留部中至少一者。
14.如权利要求12所述的半导体装置封装件，其中该接地组件透过由该介电层所定义的该些开口中的另一者电性连接于该半导体装置的该主动表面。
15.如权利要求12所述的半导体装置封装件，其中该电磁干扰遮蔽的厚度介于1微米至50微米。
16.如权利要求12所述的半导体装置封装件，其中该重新分配单元的厚度介于14微米至42微米，且该接地组件的厚度介于2微米至6微米。
17.一种半导体装置封装件的制造方法，该制造方法包括：
提供具有一主动表面的一半导体装置；
涂布一封胶材料以形成覆盖该半导体装置的一封胶结构，该半导体装置的该主动表面中至少一部份从该封胶材料中暴露出；
形成一重新分配结构于邻近该半导体装置的该主动表面之处，该重新分配结构包括一电性连接部，该电性连接部侧向地延伸于该重新分配结构中；
形成数个切割狭缝，该些切割狭缝穿过该封胶结构及该重新分配结构，该些切割狭缝对齐于该重新分配结构，用以分割该重新分配结构以形成一重新分配单元、用以分割该封胶结构以形成包括数个外部表面的一封装体以及使该电性连接部的一残留部对应至一接地组件，该接地组件具有被暴露的一连接表面；以及
涂布一电磁干扰涂层于该封装体的该些外部表面及该接地组件的该连接表面，以形成一电磁干扰遮蔽。
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