CN102087973B - Method for reducing gate oxide film pinholes - Google Patents
Method for reducing gate oxide film pinholes Download PDFInfo
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- CN102087973B CN102087973B CN 200910201905 CN200910201905A CN102087973B CN 102087973 B CN102087973 B CN 102087973B CN 200910201905 CN200910201905 CN 200910201905 CN 200910201905 A CN200910201905 A CN 200910201905A CN 102087973 B CN102087973 B CN 102087973B
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- polysilicon
- polysilicon gate
- gate
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Abstract
The invention discloses a method for reducing gate oxide film pinholes. Layered deposition is adopted during the deposition of polysilicon grids, and oxygen is introduced among all layers of polysilicon grids to form oxide films on the surfaces of the polysilicon grids. By the method, the formation of the gate oxide film pinholes can be effectively resisted by controlling the grain sizes of polysilicon electrodes.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly relate to a kind of method that reduces gate oxidation films pin hole problem.
Background technology
Fig. 1 is present accepted standard grid structure, and the polysilicon electrode above the gate oxidation films is one-pass film-forming in developmental process; After activation that polysilicon electrode is mixed, the crystal grain that its recrystallization forms is bigger, as shown in Figure 2.In follow-up wet processing, soup infiltrates than the gap that is easier to along structure cell, finally forms pin hole at gate oxidation films, as shown in Figure 3.Especially the thickness of polysilicon electrode is thicker, the easier pin hole that occurs of gate oxidation films that the follow-up wet etching time is long.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method that reduces gate oxidation films pin hole problem, by the grain size of control polysilicon electrode, the formation that can effectively resist the grid oxidation film pin hole.
For solving the problems of the technologies described above, the method of minimizing gate oxidation films pin hole problem of the present invention is to adopt following technical scheme to realize: adopt the layering deposit in the deposit of polysilicon gate, aerating oxygen between each layer polysilicon gate makes the surface of polysilicon gate form oxide-film.
Adopt method of the present invention, by the mode of layering deposit, the oxygen that feeds low concentration between polysilicon gate layer and layer is isolated each layer polysilicon electrode in the deposit of polysilicon gate.Can reduce the crystal grain of polysilicon gate deposit owing to form oxide-film on the surface of polysilicon gate, thereby avoid or reduce the generation of gate oxidation films pin hole.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is present accepted standard grid structural representation;
Fig. 2 be polysilicon gate through overdoping, activate recrystallization after crystal grain become big schematic diagram;
Fig. 3 is the schematic diagram that pin hole appears in gate oxidation films;
Fig. 4 is the polysilicon gate of one-pass film-forming and the polysilicon gate that adopts method of the present invention to form, at the comparison diagram of surface microstructure situation under atomic force microscope that mixes after activating recrystallization;
Fig. 5 is the polysilicon gate of one-pass film-forming, the pin hole schematic diagram that occurs on the gate oxidation films;
Fig. 6 adopts method gate oxidation films of the present invention to keep the complete schematic diagram that pin hole do not occur;
Fig. 7 is method control flow chart of the present invention.
Embodiment
Referring to shown in Figure 7, owing to crystal grain in the polysilicon gate developmental process can increase along with the increase of polysilicon thickness, the present invention has adopted in deposit and has fed 500-3000sccm subsequently behind one deck polysilicon, the O of＜5% concentration
2/ Ar makes the oxide-film of the about 5-10 dust of surface growth one deck of polysilicon, continues to increase to suppress polysilicon grain.Repeat said process then, namely just feed a small amount of low concentration oxygen immediately behind every deposit one deck polysilicon, final polysilicon grain is diminished, to avoid pin hole occurring in the follow-up wet processing.
Fig. 4 a is the polysilicon gate that adopts method of the present invention to form, the photo of polysilicon surface crystal grain situation under atomic force microscope after the activation recrystallization of mixing.Fig. 4 b is the polysilicon gate of one-pass film-forming, the photo of polysilicon surface crystal grain situation under atomic force microscope after the activation recrystallization of mixing.Comparison diagram 4a and Fig. 4 b can significantly see, the last crystal grain of the polysilicon gate that adopts method of the present invention to form is much smaller than the crystal grain of the polysilicon gate of deposit formation.
Remove through wet etching and with the polysilicon on surface, the gate oxidation films below keeping, the photo that obtains under the scanning electron microscopy by being positioned at of blemish somascope is shown in Fig. 5,6.Wherein Fig. 5 is the polysilicon gate photo of a deposit, and can see has pin hole to occur on the gate oxidation films below the polysilicon gate; Fig. 6 is the polysilicon gate photo that adopts method of the present invention to form, and the gate oxidation films below the polysilicon gate keeps complete, does not have pin hole to occur.Comparison diagram 5,6 explanations method of the present invention have formed very obvious effects at the opposing pin hole.
Be a specific embodiment below, more effect of the present invention can be described.In the standard grid structure shown in Figure 1, the condition of polysilicon gate deposit is to adopt the method for 620 ℃ low-pressure vapor phase deposit to form.The deposition thickness of single level polysilicon grid is 2000 dusts.The polysilicon gate deposit of improvement project is first deposit 700 dusts; Feed the O of 5 minutes 1% concentration again
2/ Ar, deposit 700 dust polysilicons again feed the O of 5 minutes 1% concentration again
2/ Ar, the polysilicon of deposit 600 dusts again. adopt 900 ℃ then, 70 minutes phosphorus oxychloride is carried out phosphorus and is expanded under normal pressure.Use 1: 30 hydrofluoric acid and ammonium fluoride to carry out wet etching 20 minutes afterwards.Under atomic force microscope, carry out the affirmation of polysilicon grain size, referring to shown in Figure 4, find that the polysilicon grain of improvement project is much smaller than the crystal grain that single deposit forms.Then the polysilicon on surface is removed the back and position with the defective of blemish somascope to silicon chip surface, and carry out defect confirmation with scanning electron microscopy.Adopt the silicon chip surface of improvement process program of the present invention pin hole not occur, and adopted the silicon chip surface of original scheme that a lot of pin holes is arranged.
More than by embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (1)
1. method that reduces gate oxidation films pin hole problem is characterized in that: adopt the layering deposit in the deposit of polysilicon gate, aerating oxygen between each layer polysilicon gate, the flow of described oxygen are 500-3000sccm, concentration＜5%; Make the surface of described each layer polysilicon gate form oxide-film; Adopt phosphorus oxychloride under normal pressure, described polysilicon gate to be carried out phosphorus and expand, realize the doping of described polysilicon gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910201905 CN102087973B (en) | 2009-12-08 | 2009-12-08 | Method for reducing gate oxide film pinholes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910201905 CN102087973B (en) | 2009-12-08 | 2009-12-08 | Method for reducing gate oxide film pinholes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102087973A CN102087973A (en) | 2011-06-08 |
| CN102087973B true CN102087973B (en) | 2013-09-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200910201905 Active CN102087973B (en) | 2009-12-08 | 2009-12-08 | Method for reducing gate oxide film pinholes |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010008442A (en) * | 1998-12-31 | 2001-02-05 | 김영환 | Method for forming transistor of semiconductor device |
| US6348380B1 (en) * | 2000-08-25 | 2002-02-19 | Micron Technology, Inc. | Use of dilute steam ambient for improvement of flash devices |
| US6413841B1 (en) * | 1998-10-22 | 2002-07-02 | Nec Corporation | MOS type semiconductor device and manufacturing method thereof |
| US6620714B2 (en) * | 2002-01-14 | 2003-09-16 | Macronix International Co., Ltd. | Method for reducing oxidation encroachment of stacked gate layer |
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2009
- 2009-12-08 CN CN 200910201905 patent/CN102087973B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413841B1 (en) * | 1998-10-22 | 2002-07-02 | Nec Corporation | MOS type semiconductor device and manufacturing method thereof |
| KR20010008442A (en) * | 1998-12-31 | 2001-02-05 | 김영환 | Method for forming transistor of semiconductor device |
| US6348380B1 (en) * | 2000-08-25 | 2002-02-19 | Micron Technology, Inc. | Use of dilute steam ambient for improvement of flash devices |
| US6620714B2 (en) * | 2002-01-14 | 2003-09-16 | Macronix International Co., Ltd. | Method for reducing oxidation encroachment of stacked gate layer |
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|---|---|
| CN102087973A (en) | 2011-06-08 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131218 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20131218 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |