CN102088059A - 在集成电路或其它装置上制造小型接脚的方法 - Google Patents
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Abstract
一种装置的形成方法,包括形成具有一侧壁的一构造的步骤。一侧壁间隙壁形成于该侧壁上。侧壁间隙壁依据一图案被蚀刻以界定该侧壁间隙壁的该宽度。宽度为次光刻等级,包括譬如约40纳米或更小。
Description
本申请是申请日为2005年11月22日且发明名称为“在集成电路或其它装置上制造小型接脚的方法”的中国专利申请No.200510124825.5的分案申请。
技术领域
本发明涉及一种集成电路与其它装置的制造方法,特别是涉及极小型接脚状的构造的制造方法。
背景技术
目前对用以制造极小型构造的集成电路工艺已经出现需求。举例而言,包括硫属材料或其它相变化材料的小型元件可通过施加电流而产生相变化。此种特性已经使我们对于使用相变化材料以形成非挥发性存储电路产生兴趣。
目前的发展方向已朝向小数量的可规划式电阻式材料的使用,尤其是在小毛细孔中。阐明朝向小毛细孔的发展的专利包括:Ovshinsky的发证于1997年11月11日的美国专利第5,687,112号,其名称为“具有梯形接点的多位单一单元存储器元件(Multibit Single Unit Memory Element Having TaperedContact)”;Zahorik等人的发证于1998年8月4日的美国专利号第5,789,277号,其名称为“硫族化物存储装置的制造方法(Method of Making ChalcogenideMemory Device)”;Doan等人的发证于2000年11月21日的美国专利号第6,150,253号,其名称为“可控制双向开关半导体元件相变化半导体存储装置及其制造方法(Controllable Ovonic Phase-Change Semiconductor MemoryDevice and Methods of Fabricating the Same)”。
本申请发明人的美国专利申请公开号US-2004-0026686-A1揭露一种相变化存储器单元,于其中相变化元件包括位于电极/介电材料/电极的堆栈上的一侧壁。数据通过使用电流而导致在非晶系与结晶系状态之间的相变化材料的转变而得以储存。电流加热此材料并导致在前述状态之间的转变。从非晶系至结晶系状态的变换一般而言是一种较低电流操作。从结晶系至非晶系的变换(于此以重置表示)一般而言是一种较高电流操作。理想上是可将用以导致从结晶系状态至非晶系状态的相变化材料的转变的重置(复位)电流的大小予以最小化。通过降低单元中的相变化材料元件的尺寸与电极和相变化材料之间的接触面积,可降低重置所需要的重置电流的大小。
供小型构造用的其它应用亦在集成电路制造中出现,且理想上是可提供新的制造技术与构造来满足此需求。
发明内容
本发明包括用以形成狭小侧壁间隙壁或接脚的方法。以下说明基于此一狭小侧壁间隙壁或接脚来形成一存储器单元的方法,此方法包括以下步骤。形成一堆栈,此堆栈包括一第一电极、位于第一电极上方的一绝缘层及位于绝缘层上方的第二电极,且一侧壁位于至少此堆栈的绝缘层上。形成一侧壁间隙壁,其包括与第一电极与第二电极电气连通的一可规划式电阻式材料。侧壁间隙壁具有沿着侧壁自第一电极延伸至第二电极的一长度、大致垂直于长度的一宽度、及由用以形成侧壁间隙壁的一层可规划式电阻式材料的厚度所决定的一厚度。侧壁间隙壁通过以下动作而形成:沉积一层可规划式电阻式材料于堆栈的侧壁上,各向异性蚀刻该层可规划式电阻式材料以将远离侧壁的在多个区域中的材料予以移除,以及依据一图案来选择性蚀刻可规划式电阻式材料来界定侧壁间隙壁的宽度。在说明于此的实施例中,宽度小于50纳米,更好是约40纳米或更少。
为了依据一图案来选择性地蚀刻可规划式电阻式材料以界定具有这样狭小宽度的一侧壁间隙壁,所使用的一项技术包括形成具有一光刻(平版印刷)图案的一蚀刻光掩模以界定一光刻宽度,然后修整蚀刻光掩模以提供一修整过的光掩模来界定图案,用来界定侧壁间隙壁的宽度。于一例子中,蚀刻光掩模包括一光致抗蚀剂,其通过使用一氧基等离子体蚀刻而被各向异性地蚀刻以形成修整过的光掩模。于另一例子中,蚀刻光掩模包括使用一光刻处理所界定的一硬性光掩模,其被蚀刻以缩小其宽度并形成修整过的光掩模。
说明于此的界定在单元的相变化接脚中的有源区域的尺寸三种尺寸最好是小于50纳米,并可全部小于被应用来制造此单元的光刻处理的最小特征尺寸。这些尺寸于说明于此的技术中由相变化材料的薄膜厚度、电极间介电材料薄膜厚度及修整过的光掩模所界定。因此,单元尺寸(相变化材料的体积)很小(小于F3,其中F是用以制造存储器单元的处理工艺的最小光刻特征尺寸)。所产生的相变化材料的单元包括位于一电极堆栈的侧壁上的一狭小型接脚。在上电极与下电极的至少一者及相变化材料接脚之间的接触面积,亦由供这些高度用的电极层厚度及供此宽度的接点用的光致抗蚀剂图案修整处理而以次平板印刷的方式被界定。小单元与小接触区域允许具有很小重置电流与低功率消耗的存储器的实施。
本发明亦说明包括一堆栈的一种存储装置,这堆栈包括一第一电极、位于第一电极上方的一电极间绝缘构件及位于电极间绝缘构件上方的一第二电极。这堆栈具有在至少绝缘构件上方的侧壁。包括位于侧壁上的可规划式电阻式材料的一间隙壁,与第一电极与第二电极电气连通。间隙壁具有沿着绝缘层的侧壁而从第一电极延伸至第二电极的一长度,而此绝缘层大致垂直于长度与厚度。于说明于此的技术的实施例中,间隙壁的宽度与厚度小于40纳米。可规划式电阻式材料包括一种可逆且可规划的相变化材料。
说明于此的用以形成相变化材料接脚的方法可被使用来在一集成电路或其它装置上制造供其它纳米技术使用的极小型接脚,所使用的材料可以是除相变化材料以外的材料,就像是金属、介电材料、有机物、半导体等等。小尺寸侧壁接脚可形成于此构造上,而非说明于此的用来供相变化存储器单元用的构造上,例如包括其它型式的堆栈的薄膜的构造,例如薄膜介电材料的堆栈,而可具有或不具有一电极层以供接触至接脚。
为让本发明的上述目的、特征、和优点能更明显易懂,以下配合附图以及优选实施例,以更详细地说明本发明。
附图说明
图1为侧壁有源接脚存储器单元的立体图。
图2为包括相变化存储器元件的一存储器阵列的示意图。
图3为包括薄膜熔丝相变化存储器阵列与其它电路的集成电路装置的方块图。
图4为依据本发明的一实施例的最终阵列构造的剖面。
图5为在前端线处理与电极堆栈薄膜层的形成以后的前述构造的剖面。
图6A与图6B显示分别地在电极堆栈蚀刻图5的构造之后的俯视图与剖面图。
图7显示沉积于图6B的构造上的相变化材料薄膜。
图8A与图8B分别显示在GST薄膜间隙壁蚀刻以后的俯视图与剖面图。
图9显示在介电材料填充层形成以后的剖面图。
图10显示在用以平坦化与曝光相变化材料侧壁的化学机械抛光以后的剖面图。
图11显示在光致抗蚀剂图案的形成及供相变化侧壁接脚宽度的界定用的修整以后的俯视图。
图12A与图12B分别显示在相变化材料侧壁的选择性蚀刻以界定一相变化侧壁接脚宽度尺寸以后的俯视图与剖面图。
图13显示在移除光致抗蚀剂所产生的相变化材料侧壁接脚以后的俯视图。
图14显示在通过移除相变化材料侧壁所留下的小接缝中的填充以及后来的氧化物沉积以后的剖面图。
图15显示在通道孔形成与用以界定位线的金属化以后的俯视图与剖面图。
图16显示一实施例,其中薄膜相变化材料侧壁部分被蚀刻。
图17显示用以于一集成电路上制造一小型接脚的代表工艺的一第一阶段。
图18显示用以于一集成电路上制造一小型接脚的代表工艺的一第二阶段。
图19显示用以于一集成电路上制造一小型接脚的代表工艺的一第三阶段。
图20显示用以于一集成电路上制造一小型接脚的代表工艺的一第四阶段。
图21与22分别地显示用以于一集成电路上制造一小型接脚的一代表工艺的一第五阶段的剖面与立体图。
图23显示显示用以于一集成电路上制造一小型接脚的代表工艺的一第六阶段。
图24显示用以于一集成电路上制造一小型接脚的代表工艺的一第七阶段。
图25显示用以于一集成电路上制造一小型接脚的代表工艺的一第八阶段。
图26显示依据于此说明所制作的一小型接脚。
简单符号说明
L:长度
T:厚度
W:光刻宽度
5:接脚
6:第一电极/薄膜电极
7:第二电极/薄膜电极
8:电极间介电材料层
9:介电材料
10:侧壁有源接脚存储器单元
23、24:字线
28:共同电源线
32:下电极构件
33:下电极构件
34:上电极构件
35:侧壁接脚存储器单元
36:侧壁接脚存储器单元
37:上电极构件
41、42:位线
45、46:方块
50-53:存取晶体管
55:存储器阵列
56:列译码器
58:总线
59:方块
60:电极堆栈
61:侧壁
62:字线
63:行译码器
64:位线
65:电极堆栈
66:侧壁
67:数据总线
68:偏压配置电源电压
69:状态机
71:数据输入线
72:数据输出线
74:其它电路
74:集成电路
99:构造
100-103:侧壁有源接脚相变化随机存取存储器单元
110:半导体基板
111、112:沟槽
113、114:多晶硅字线
115:掺杂区/漏极区
116:共源极区/共源极掺杂区
117:掺杂区/漏极区
118:介电材料层
119:电源线
120:插塞
121:下电极
122:薄膜电极间介电材料层
123:上电极
124:侧壁接脚
125:薄氧化层
126:钨插塞
127:介电材料填充层
129、130、131、132:接点
141:插塞
150:下电极薄膜
151:电极间介电材料
152:上电极薄膜
153:上介电材料
155:第一矩形
156:第二矩形
160:上介电材料层
170:保形层(conformal layer)
171、172:侧壁
173:上表面
180:介电材料层
181、182:顶端
185、186:延伸部
187、188:修整过的光掩模
190:接缝
193、194:填料
195:层
196、197:插塞
198:金属层
201:接脚
202:上电极层
203:残留层
210:狭小区域
300:硅晶片
301:第一层
302:第二层
303-304:构造
305、306:侧壁
307:表面
308:层
309:填充层
310-316:表面
320:光掩模
321:修整过的光掩模
322:接缝
323:补片
325:接脚
326:顶端
330:构造
具体实施方式
以下参考附图进行下述详细说明。所举出的元件实施例用以说明本发明,而非局限本发明的保护范围。本领域技术人员将明白到依照此说明所作的种种的等效变化,皆落于本发明的范畴内。
图1为侧壁有源接脚存储器单元10的立体图。此单元包括一狭小侧壁间隙壁,其被称为位于一电极堆栈的一侧壁上的一接脚5,此电极堆栈包括一第一薄膜电极6、一第二薄膜电极7及分离该第一电极6与第二电极7两者的一电极间介电材料层8。在所显示的实施例中,一种介电材料9覆盖于电极堆栈上面。接脚5由一可规划式电阻式材料(例如一相变化材料)所组成。接脚5具有一有源区域,此相变化在有源区域之内会被限制,接脚5在第一电极6与第二电极7之间具有的一长度L由电极间介电材料层8的厚度所决定。接脚5的有源区域具有厚度T,其由形成于电极堆栈的侧壁上的薄膜的厚度所决定。电极堆栈通过使用一光刻处理或其它型式的光刻处理而制成,从而能使其宽度约等于光刻处理所特有的最小特征尺寸。关于进阶的光刻处理,电极堆栈的宽度W可以为约90纳米。接脚5的有源区域具有小于供用以界定电极堆栈的光刻处理用的最小特征尺寸的宽度。在说明于此的实施例中,接脚5的有源区域的宽度约40纳米或更少。
如所显示地,接脚5的有源区域具有由电极间介电材料层8的薄膜厚度所界定的长度L,其本发明的实施例中的范围可以在约20与50纳米之间。同样地,接脚5的有源区域具有厚度T,其由使用以形成侧壁接脚的此材料的薄膜厚度所界定,此厚度T在本发明的实施例中的范围在约10与50纳米之间。因此,接脚5的所有三个尺寸于本发明的实施例中小于50纳米,且最好是小于约40纳米或更少。
在本发明的实施例中,可规划式电阻式材料包括一相变化材料,例如Ge2Sb2Te5或下述其它材料。材料在接脚5内的体积因而是很小的,于此体积中,相变化于显示于图1的构造中生成。关于接脚5的有源区域的长度L、该宽度W与厚度T小于40纳米的实施例,有源区域的体积小于64×10-24m3。因此,供相变换用所需要的重置电流是很小的。
存储器单元的实施例包括供侧壁接脚5用的相变化基存储器材料,其包括硫属基材料与其它材料。硫族元素(chalcogen)包括形成周期表的VI族的一部份的氧(O)、硫(S)、硒(Se)与碲(Te)的四种元素的任何一者。硫属包括具有更多正电性元件或原子团的一硫族元素的化合物。硫属合金包括硫属与例如过渡金属的其它材料的组合。硫属合金通常包括元素周期表的第六列的一个或多个元素,例如锗(Ge)与锡(Sn)。通常,硫属合金包括含有一个或多个锑(Sb)、镓(Ga)、氧化铟锡(In)与银(Ag)的组合。多数的相变化基存储器材料已被说明于技术文献中,包括以下合金:Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te与Te/Ge/Sb/S。在Ge/Sb/Te合金的家族中,宽广范围的合金组成物可能可以工作。组成物可被特征化为TeaGebSb100-(a+b),其中a与b表示将组成元素的100%的原子总计起来的原子百分比。一研究者已经说明最有用的合金是于所沉积的材料中具有Te的平均浓度是70%以下,一般约60%以下,且其范围一般是从低达约23%至多达约58%的Te,更好约48%至58%的Te。Ge的浓度在约5%之上且范围在此材料中是从约8%的低值至约30%的平均值,维持大致50%以下。Ge的浓度的范围最好是从约8%至约40%。于此组成物中,主要组成元素的其余部分为Sb(Ovshinsky的美国专利第5,687,112号,第10-11栏)。由另一研究者所评估的特定合金包括Ge2Sb2Te5、GeSb2Te4与GeSb4Te7(Noboru Yamada,“高数据纪录速率的Ge-Sb-Te相变化光盘的电位(Potential of Ge-Sb-Te Phase-Change Optical Disks forHigh-Data-Rate Recording)”,SPIE v.3109,pp.28-37(1997)。)更一般言之,例如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、白金(Pt)及其混合物或合金的过渡金属,可能与Ge/Sb/Te结合以形成具有可规划式电阻特性的相变化合金。可能有用的存储器材料的特定例子为Ovshinsky的美国专利第5,687,112号的第11-13栏,此例子藉此列入参考数据。
相变化材料能在一第一构造状态与一第二构造状态之间被转换,于第一构造状态中,此材料大致是呈非晶系固相,而于第二构造状态中,此材料于此单元的有源通道区中的局部次序(local order)大致呈结晶系固相。这些相变化材料至少是双稳态的。专门用语“非晶系”用以表示相当少有次序的构造,其比具有可侦测的特征(例如比结晶相具有高的电阻系数)的单晶更没有次序。专门用语“结晶系”用以表示相当更有序的构造,其比非晶系构造更有次序,而非晶系构造具有例如比非晶相具有低的电阻系数的可侦测的特征。一般而言,相变化材料可能在横越过在完全非晶系与完全结晶系状态之间的幅度中,于局部次序的不同的可侦测状态之间作电气转换。受在非晶系与结晶相之间的变换所影响的其它材料特征包括原子次序、自由电子密度与活化能。此材料可能转换成不同固相或具有两个以上的固相的混合物,因而提供在完全非晶系与完全结晶系状态之间的灰阶度。材料中的电气特性可能因此有所差异。
通过施加电脉冲可能使相变化材料从一相状态变换成另一相状态。我们已观察到较短且较高振幅脉冲易于将相变化材料变换成大致非晶系状态。较长且较低振幅脉冲易于将相变化材料变换成大致结晶系状态。较短且较高振幅脉冲的能量高到足够允许结晶系构造的键结被损坏,并短到足以避免这些原子对准成为一结晶系状态。脉冲的适当的轮廓可根据经验来决定,而不需要过度实验,其特别适合于特定相变化合金。
在揭露内容的下述部分中,相变化材料以GST表示,且申请人将理解到亦可使用其它型式的相变化材料。一种说明于此的有用于实施存储器单元的材料为Ge2Sb2Te5。
类似于相变化材料的可规划式电阻式材料的有用特征,包括具有可规划的电阻的材料,最好是以可逆方式可规划的电阻的材料,例如通过具有可被电流可逆地感应生成的至少两固相。这至少两个相包括一非晶相与一结晶相。然而,在操作中,可规划式电阻式材料无法被完全转换至非晶系或结晶相。中间相或混合相在材料特征方面可具有一可侦测的差异。两个固相一般而言是双稳态的,且具有不同的电气特性。可规划式电阻式材料可能是一种硫属材料。一种硫属材料可包括GST。或者,其可能是说明于上面的其它相变化材料的其中一者。
图2为存储器阵列的示意图,其可如说明于此地被实施。于图2的示意图中,一共同电源线28、字线23与24通常配置成平行于Y方向。位线41与42通常配置成平行于X方向。因此,在方块45中的一Y译码器与一字线驱动器连接至字线23、24。在方块46中的一X译码器与一组感测放大器连接至位线41与42。共同电源线28连接至存取晶体管50、51、52与53的源极端子。存取晶体管50的栅极连接至字线23。存取晶体管51的栅极连接至字线24。存取晶体管52的栅极连接至字线23。存取晶体管53的栅极连接至字线24。存取晶体管50的漏极连接至具有上电极构件34的侧壁接脚存储器单元35的下电极构件32。上电极构件34连接至位线41。同样地,存取晶体管51的漏极连接至具有上电极构件37的侧壁接脚存储器单元36的下电极构件33。上电极构件37连接至该位线41。存取晶体管52与53亦连接至位线42上的对应的侧壁接脚存储器单元。由此可观察到共同电源线28由两列存储器单元共享,其中一列在所显示的概要中配置于Y方向。在其它实施例中,存取晶体管可被二极管或于用以读取与写入数据的阵列中用以控制电流流动至选定装置的其它构造所置换。
图3为依据本发明的一实施例的集成电路的简化方块图。集成电路75包括位于一个半导体基板上的一存储器阵列55,此存储器阵列55通过使用侧壁有源接脚相变化存储器单元来实施。一列译码器56连接至多条字线62,并沿着存储器阵列55的列配置。一行译码器63连接至沿着存储器阵列55的行配置的多条位线64,用以读取并规划来自阵列55中的侧壁接脚存储器单元的数据。地址于总线58上被提供至行译码器63与列译码器56。在方块59中的感测放大器与数据输入构造经由数据总线67而连接至行译码器63。数据经由数据输入线71而从集成电路75上的输入/输出埠或从集成电路75的内部或外部的其它数据源提供至方块59中的数据输入构造。在所显示的实施例中,其它电路包括于集成电路中,例如一泛用处理器或特殊用途应用电路,或提供被薄膜熔丝相变化存储器单元阵列所支持的系统整合芯片(system-on-a-chip)的功能的模块的一组合。数据经由数据输出线72而从方块59中的感测放大器提供至集成电路75上的输入/输出埠,或至集成电路75的内部或外部的其它数据目标。
一种于此例子使用偏压配置状态机69来实施的控制器,控制例如读取、程序化、抹除、抹除确认与程序化确认电压的偏压配置电源电压68的施加。使用本技术领域所熟知的特殊用途逻辑电路亦可实施控制器。在替代实施例中,控制器包括一泛用处理器,其可能于同一集成电路上实施,此集成电路执行一计算机程序以控制装置的操作。在又其它的实施例中,可能利用特殊用途逻辑电路与泛用处理器的一组合来实施控制器。
图4说明多个侧壁有源接脚相变化随机存取存储器单元100-103的剖面。单元100-103形成于一个半导体基板110上。例如浅沟槽隔离STI介电材料沟槽(trench)111与112的隔离构造将存储器单元存取晶体管的成对的列予以隔离。存取晶体管通过基板110上的共源极区116及基板110上的漏极区115与117而形成。多晶硅字线113与114形成存取晶体管的栅极。介电材料填充层118形成于多晶硅字线113与114上方。接触窗插塞构造141与120接触个别的存取晶体管漏极,而共同电源线119沿着阵列中的一列接触源极区。共同电源线119接触共源极区116。插塞构造120接触单元101的一下电极121。类似单元100、102与103的单元101包括一薄膜下电极121、一薄膜电极间介电材料层122、一薄膜上电极123及含有GST或另一相变化材料的一侧壁接脚124。一介电材料填充层127覆盖于单元100-103上面。钨插塞126接触上电极123。提供接点129、130、131、132的一图案化的金属层覆盖于介电材料填充层127上面。一般而言,接点129-132为延伸至译码电路的一单一位线的一部份,如图2所示。所显示的一薄氧化层125覆盖于上电极123上。层125供给处理裕度用,如下所述。
在代表实施例中,图案化的金属层(接点129-132)包括铜金属化物。亦可利用包括铝与铝合金的其它型式的金属化物。上电极与下电极(例如121,123)包括厚度为10至30nm的锡或TaN。或者,这些电极可能是TiAlN或TaAlN,或可包括选自于Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、Ru与O所组成的群组的一个或多个元素。电极间绝缘层可能是氧化硅、氮氧化硅、氮化硅、Al2O3、其它低K介电材料或一种ONO或SONO多层构造。或者,电极间绝缘层可包括选自于由Si、Ti、Al、Ta、N、O与C所组成的群组的一个或多个元素。电极间厚度可能是10至200nm,更好50纳米或更少。第二电极可能是锡或TaN。
图5显示在前端线处理以后的构造99,此前端线处理在所显示的实施例形成标准CMOS元件,并于显示于图2的阵列中对应至字线、电源线及存取晶体管。在图5中,电源线119覆盖于半导体基板中的掺杂区116上面,其中此掺杂区116对应到在图中的左侧的一第一存取晶体管的源极端子,以及图中的右侧的一第二存取晶体管。于本实施例中,电源线119延伸至构造99的上表面。于其它实施例中,电源线并不是一直延伸至此表面。掺杂区115对应到第一存取晶体管的漏极端子。包括多晶硅113与硅化物盖体(未显示)的一字线作为第一存取晶体管的栅极。介电材料层118覆盖于多晶硅字线113上面。插塞120接触掺杂区115,并提供一导电路径至构造99的表面,用以接触至如下所述的存储器单元电极。第二存取晶体管的漏极端子由掺杂区117所提供。包括多晶硅线114与硅化物盖体(未显示)的一字线作为第二存取晶体管的栅极。插塞141接触掺杂区117并提供一导电路径至构造99的上表面,用以接触一存储器单元电极,如下所述。隔离用沟槽111与112将连接至插塞120与141的这两个晶体管构造和邻近的两个晶体管构造予以分离。显示于图5的构造99提供一基板,用以形成存储器单元元件,详述如下。
在形成插塞120、141与供构造99用的电源线119之后,形成一多层薄膜构造,其包括下电极薄膜150、上电极薄膜152、电极间介电材料151及保护上介电材料153。下电极薄膜150的厚度小于50纳米,最好的范围是在10至30纳米之间。上电极薄膜152的厚度小于50纳米,最好的范围是在10至30纳米之间,并且可不同于下电极薄膜的厚度。举例而言,上电极薄膜152的厚度可略大于下电极的厚度,以便改善使用钨插塞技术等等的可靠接点的处理裕度。上介电材料153提供供平坦化用的化学机械抛光、侧壁间隙壁蚀刻的变化等等的使用的处理裕度。亦可实施不具有上介电材料153的替代实施例。
图6A显示包括一第一矩形155与一第二矩形156的光掩模图案的俯视图,此光掩模图案用以蚀刻图5的多层薄膜构造,来形成电极堆栈60,65,如图6B的剖面所示。电极堆栈60包括下电极121、电极间介电材料122与上电极123。电极堆栈60具有侧壁61。同样地,电极堆栈65具有侧壁66。反应性离子蚀刻REI被利用以便将侧壁61与66建构成尽可能垂直。虽然未显示图中,反应性离子蚀刻RIE可能过切至介电材料填充层118中。在代表处理中,此过切约20纳米。可使用BCl3及/或Cl2基的修整法的处理过程。
图7显示在沉积以后的构造,此沉积通过在此等堆栈60、65上方溅射譬如GST的一保形层(conformal layer)170或其它可规划式电阻式材料而实施。通过使用不具有准直性的溅射,可于约250℃下沉积GST。当使用Ge2Sb2Te5作为相变化材料时,这导致一薄膜在电极堆栈的上端具有约60至80纳米的厚度,在侧壁上具有约20至30纳米的厚度,以及在这些堆栈之间具有约60至80纳米的厚度。处理过程的各种不同的实施例可将整个晶片溅射成在平坦表面上具有40至100纳米的厚度。
图8A显示通过一蚀刻处理进行侧壁蚀刻的结果的平面视图,该蚀刻处理自平坦表面移除GST层,并留下于堆栈60上的侧壁171及堆栈65上的侧壁172,侧壁171与172完全围绕堆栈60与65。可使用各向异性Cl2及/或BCl3修整法的RIE处理工艺。图8B显示剖面中的侧壁171与172。由于轻微的过度蚀刻以确保全部移除离开构造99的表面173,侧壁具有略低于上介电材料层160的表面的顶端。
图9显示介电材料填入工艺。此工艺涉及到遍布该相变化材料侧壁上的低温度填料氧化物、一氮化硅层或氧化硅层(未显示)的形成,所使用的处理温度低于约200℃。一项适当的处理为使用等离子体增强式化学气相沉积PECVD来涂敷二氧化硅。在填料形成以后,介电材料填料180通过使用较高温度处理工艺(例如二氧化硅或其它类似材料的高密度等离子体HDP CVD)来实施。
如图10所示,应用至一氧化物化学机械抛光CMP处理来将此构造予以平坦化,并暴露GST侧壁171、172的顶端181、182。在电极堆栈上的上介电材料层确保CMP不会碰触上电极材料(例如锡),并保护使其免受于RIE处理或其它蚀刻步骤以后的损坏。
图11显示用以形成次光刻光掩模以修整侧壁171、172的光致抗蚀剂图案修整。一光致抗蚀剂图案通过使用包括从一光掩模或一组光掩模转移一图案至光致抗蚀剂层的光刻技术而形成,光致抗蚀剂层包括位于堆栈60上方的一长方形延伸部185及位于该堆栈65上方的一长方形延伸部186,如虚线轮廓所示。延伸部185、186的宽度W1在光致抗蚀剂显影之后接近所利用的光刻处理的最小特征尺寸,以形成图案延伸部185、186。接着,延伸部185、186的宽度W1通过光致抗蚀剂修整而被缩小至次光刻宽度W2,以留下狭小修整过的光掩模187、188。举例而言,通过使用一氧化物等离子体来对光致抗蚀剂进行各向异性地蚀刻,以在0.2微米(200纳米)的最小特征尺寸光刻处理环境下,将图案化光致抗蚀剂的宽度与厚度下修至例示实施例中的小于50纳米的宽度W2,并将譬如约40纳米的宽度W2。
在替代实施例中,可将例如SiN或SiO2的低温度沉积层的一硬性光掩模层(未显示)置放在光致抗蚀剂图案与堆栈60、65的表面之间,用以避免单元的蚀刻损坏,如果光致抗蚀剂在修整处理之后并非足够厚的话,或GST与硬性光掩模的选择性蚀刻由硬性光掩模加以改良。
图12A显示依据修整过的光掩模187、188的侧壁单元宽度蚀刻的平面视图,譬如使用氯基反应性离子蚀刻俾能使介电材料填料180不被蚀刻。蚀刻动作移除露出的GST,而留下一狭小侧壁接脚124于电极堆栈上,如图12B的剖面所示。在堆栈60与堆栈65周围的一接缝190残留于介电材料层180,其最好是延伸至构造99的上表面173,且GST完全被移除。在上述处理的实施例中,在接缝190中的所有GST不需被移除。反之,在接缝190中的GST的显着部分能被移除就足够了,俾能使在下电极与上电极之间的电流集中于此堆栈的电极间介电材料层的一狭小型接脚。
图13以平面视图显示在前述处理的次一步骤,其涉及到修整过的光致抗蚀剂光掩模(187,188)与硬性光掩模层(如果有的话)的移除。在堆栈60上的侧壁接脚124与在堆栈65上的侧壁接脚124A在处理过程的实施例中具有约40纳米或更少的一次光刻宽度W。
图14显示小接缝填入与氧化物沉积步骤。可通过使用原子层沉积而以电气及/或热绝缘填料193、194来填满通过移除侧壁所留下的小接缝190(图13B)。在代表实施例中,原子层沉积用以沉积介电材料材料,例如AlO2,HfO2等等。在其它实施例中,通过使用无机旋涂式玻璃或″低K″材料来旋转涂布氧化硅,可将这些接缝填满。在另一实施例中,这些接缝被密封以形成基本上被排空的一孔洞,用以为这些单元提供良好隔热效果。其次,一上氧化物沉积以介电材料的一层195覆盖电极堆栈,此层195在制备后来的金属化物时被平坦化。上氧化层最好是通过PECVD或其它较低温处理工艺而形成。
图15显示通道孔形成与供位线与至存储器单元的接点用的金属化。通道孔于层195被蚀刻并以钨或其它导体材料填满以形成插塞196与197,来达成接触至堆栈60的上电极层123及堆栈65的上电极层123A。一图案化的金属层198提供在此图的平面上延伸至译码电路的多条位线。如上所述,插塞120与141将在堆栈60与65的各下电极之间的接点提供至存取晶体管的漏极115与117。字线113、114通过存取晶体管的多晶硅栅极而形成。共源极掺杂区116与电源线119为感测电流提供的流动,从位线经由存储器单元而到存取晶体管并下至共同电源线。
图16显示依据一替代实施例的在GST层侧壁蚀刻沉积以后的例如堆栈60的电极堆栈的剖面,其中GST层只有在电极堆栈的周边周围被局部蚀刻,从而于接缝(190,参见图12B)的底部留下一残留层203围绕此堆栈。于图16的本实施例中,接脚201具有一次光刻宽度,于此其接触上电极层202,并延伸至电极间介电材料层中,俾能使电流流动集中于相变化材料接脚的狭小区域210。
上述相变化材料接脚与用以制造此接脚的工艺,代表使用如说明于此的纳米规模构造的技术。图17-25显示在用以制造一小型接脚的另一代表工艺的阶段的顺序。图17显示包括一硅晶片300的基板,硅晶片300具有一第一层301的材料与形成于第一层301上的一第二层302的材料。于此实施例中,第一层301的材料包括″材料B″而第二层302的材料包括″材料A,″其中这两种材料被选择成能使它们可被选择性地蚀刻。代表性的材料包括集成电路、平面显示与相关工艺中的氮化硅与二氧化硅。第一层301的材料的代表厚度的范围从约50至约500纳米,与于显示的例子中更特别是200纳米左右的氮化硅。于某些实际例子中的第二层302的材料的代表厚度的范围亦是从约50至约500纳米,且在所显示的例子中更特别是约220纳米的二氧化硅。
图18显示代表工艺的第二阶段。于此阶段中,第二层302的材料依据一图案而被蚀刻下至第一层301的材料的表面307,而留下在第二层302的材料中具有一侧壁305的构造303以及在第二层302的材料中具有一侧壁306的一构造304。
图19显示代表工艺的第三阶段。于此阶段中,一层308的侧壁材料形成于构造303、304与第一层301的材料的表面307上方,并保有第二层302的材料中的侧壁305、306的形状。侧壁材料包括一相变化材料,如上述的一实施例。在其它实施例中,侧壁材料包括一金属,例如铝、钨、铜、钛,、氮化钛、钽、氮化钽、金、白金及其它金属,金属化合物与金属合金。在其它实施例中,侧壁材料包括一种半导体,例如硅,锗,氮化镓,及其它化合物。在又其它实施例中,侧壁材料包括一非金属,例如氧化铝、氧化钛,氧化铪,或其它高介电常数(K)与热的电气绝缘材料。可使用作为侧壁材料的材料包括导体、半导体与绝缘体。可使用作为侧壁材料的材料可已是结晶硅、多晶硅与非晶质材料。可使用作为侧壁的材料可能是有源材料,例如用来制作存储器元件、晶体管栅极、激光二极管、量子阱装置等等。层308的侧壁材料的厚度取决于特定应用。于代表构造中,侧壁305、306上的侧壁材料的范围从约10纳米至约50纳米。在其它构造中,可应用更大或更小厚度的侧壁材料。
图20显示代表工艺的第四阶段。于此阶段中,一填充层309形成此层308的侧壁材料上。用来作填充层309的材料于此例子可包括″材料A″或二氧化硅。在替代系统中,用来作填充层309的材料不同于″材料A″,其包括譬如与″材料B″相同的材料。用来作填充层309的材料最好是适合使用于下述的后来的工艺的一回蚀与平坦化工艺。
图21与22显示代表工艺的第五阶段。在第五阶段中,图20的构造被回蚀与平坦化,所使用的程序例如化学机械抛光。所产生的构造具有一平坦表面,其包括构造303的一表面310、侧壁材料的表面312、填充材料的表面314、侧壁材料的表面313及构造304的表面311。如图22所示,在由层309充填的沟槽的末端的侧壁,在化学机械抛光或其它回蚀与平坦化步骤以后具有与填充材料的表面314及侧壁材料的表面312、313齐平的表面315、316。
图23显示代表程序的次一阶段,其中对一层的光致抗蚀剂进行沉积、图案化与显影,以于至少一侧壁间隙壁(例如具有露出表面313的侧壁间隙壁)形成一光刻光掩模320。在构造304上方的光掩模320自填充层309的表面314上方延伸横越过侧壁间隙壁的表面313。光刻光掩模320的宽度通过使用一光刻处理(例如是一光刻处理)来界定,且最好是具有利用光刻处理所特有的最小特征尺寸。举例而言,现代化的光刻处理可具有的最小特征尺寸范围是从约90到约200纳米。可能应用进阶的光刻处理以达成小的最小特征尺寸。
图24显示代表程序的第七阶段。在第七阶段中,使用一各向异性蚀刻程序(例如被应用至光致抗蚀剂材料的氧基等离子体蚀刻)来修整光刻光掩模320。因为光刻光掩模320的蚀刻的结果,形成一个次光刻的修整过的光掩模321,其具有小于光刻处理所特有的最小特征尺寸的宽度。代表实施例的修整过的光掩模321的宽度约40纳米或更少,此处的最小特征尺寸约200纳米或更少。如图24所示,光刻光掩模320的宽度与厚度两者被修整过,从而能使修整过的光掩模321比光刻光掩模来得更狭小且更薄。在替代系统中,可利用一硬性光掩模材料与一光致抗蚀剂,或可利用一硬性光掩模材料来取代光致抗蚀剂。举例而言,可使用光刻处理来形成与图案化一层氮化硅,用以提供包括氮化硅的一光刻光掩模320。然后,蚀刻氮化硅光刻光掩模320以形成修整过的光掩模321。在形成修整过的光掩模321之后,所产生的构造选择性地被蚀刻以移除不被修整过的光掩模321所覆盖的区域的侧壁材料。因为选择性蚀刻的结果,留下接缝322围绕具有一表面314的填充层309。于一元件实施例中,选择性蚀刻移除了所有的填充材料下至第一层301的材料的表面(未显示),并导致侧壁材料的一补片(patch)323,其位于填充层309下方并与在构造304与填充层309之间残留于侧壁上的侧壁材料的接脚325呈连续。
图25显示前述程序的第八阶段。于第八阶段中,修整过的光掩模321被移除以留下小型接脚325与在填充层309与构造304之间的接缝。接脚的长度由在第二层302的材料的回蚀后的薄膜厚度所决定。接脚的厚度由构造304的侧壁上的侧壁材料的薄膜厚度所决定。接脚的宽度由次光刻、修整过的光掩模321及用来依据由修整过的光掩模321所界定的图案进行选择性蚀刻的蚀刻处理所决定。
图26显示依据于此说明所制作的一接脚325。接脚325由含有侧壁材料的一补片323的构造330上的一狭小侧壁间隙壁及一层填充材料309所组成。接脚325的顶端326与填充层309的表面314齐平。在所显示的构造中,所显示的接脚325位于包括填充层309的构造330一侧。在替代系统中,可将填充层309移除,而留下接脚325于第二层302的材料的构造304的该侧面。
综上所述,虽然本发明以优选实施例揭露如上,然而其并非用以限定本发明,本领域的技术人员在不脱离本发明的精神和范围内,可作些许的更动与润饰,因此本发明的保护范围应当以后附的权利要求所界定者为准。
Claims (31)
1.一种小型构造的形成方法,包含以下步骤:
形成一电极堆栈,至少依序包括第一导电层、第一绝缘层、第二导电层、和第二绝缘层堆栈而成,该第一、二导电层由该第一绝缘层分离;
利用图案化蚀刻该电极堆栈以形成具有侧壁的构造;
沉积侧壁材料保形层于该侧壁上,以及
蚀刻该侧壁材料保形层,以在该侧壁上形成侧壁间隙壁,使该电极堆栈与该侧壁间隙壁构成内存单元。
2.如权利要求1所述的方法,其中选择性地蚀刻的该步骤包含:
形成具有平版印刷图案的蚀刻光掩模以界定平版印刷宽度;以及
修整该蚀刻光掩模以提供修整过的光掩模来界定该图案以界定该侧壁间隙壁的该宽度。
3.如权利要求1所述的方法,其中选择性地蚀刻的该步骤包含:
形成具有平版印刷图案的蚀刻光掩模以界定平版印刷宽度;以及
非等向性地蚀刻该蚀刻光掩模以提供修整过的光掩模来界定该图案以界定该侧壁间隙壁的该宽度。
4.如权利要求1所述的方法,还包含以下步骤:
在该沉积步骤之后,非等向性地蚀刻该层的侧壁材料,以从除该构造的该侧壁以外的多个区域移除该侧壁材料。
5.如权利要求1所述的方法,还包含以下步骤:
在该沉积步骤之后,涂敷一层填充材料遍布该构造与该层的侧壁材料上;及
回蚀在该构造的顶端上的该层填充材料与该层的侧壁材料,以留下实质上平坦的表面并于该实质上平坦的表面露出该侧壁上的该侧壁材料。
6.如权利要求1所述的方法,其中该回蚀步骤包含化学机械抛光。
7.如权利要求1所述的方法,其中该构造具有小于1微米的厚度,且侧壁间隙壁沿着该侧壁具有小于1微米的长度。
8.如权利要求1所述的方法,其中该构造具有小于0.5微米的厚度,且该侧壁间隙壁沿着该侧壁具有小于0.5微米的长度。
9.如权利要求1所述的方法,其中该构造中该第一、二绝缘层为介电材料,该第一、二导电层为薄膜电极,且该侧壁材料包含与该至少一导电层电气连通的导电材料。
10.如权利要求1所述的方法,其中该构造中该第一、二绝缘层为介电材料,该第一、二导电层为薄膜电极,且该侧壁材料包含与该至少一导电层电气连通的一种半导体材料。
11.如权利要求1所述的方法,其中该电极堆栈通过光刻处理和平版印刷处理其中之一的方式所制成。
12.如权利要求1所述的方法,其中依据图案来选择性地蚀刻该侧壁材料,且依据该图案蚀刻后所界定出该侧壁间隙壁的宽度小于40nm。
13.一种小型构造的形成方法,包含以下步骤:
形成电极堆栈,至少依序包括第一导电层、第一绝缘层、第二导电层、和第二绝缘层堆栈而成,该第一、二导电层由该第一绝缘层分离;
使用具有最小平版印刷特征部尺寸的平版印刷处理,在该电极堆栈上形成具有侧壁的构造;
沉积侧壁材料保形层于该侧壁上;以及
蚀刻该侧壁材料保形层,以于该侧壁上形成侧壁间隙壁,使该电极堆栈与该侧壁间隙壁构成内存单元,且所界定的该侧壁间隙壁的该宽度小于该最小平版印刷特征部尺寸。
14.如权利要求13所述的方法,其中选择性地蚀刻的该步骤包含:
形成具有平版印刷图案的蚀刻光掩模以界定平版印刷宽度;及
修整该蚀刻光掩模以提供修整过的光掩模来界定该图案以界定该侧壁间隙壁的该宽度。
15.如权利要求13所述的方法,其中选择性地蚀刻的该步骤包含:
形成具有平版印刷图案的蚀刻光掩模以界定平版印刷宽度;以及
非等向性地蚀刻该蚀刻光掩模以提供修整过的光掩模来界定该图案以界定该侧壁间隙壁的该宽度。
16.如权利要求13所述的方法,还包含以下步骤:
在该沉积步骤之后,非等向性地蚀刻该层的侧壁材料,以从除该构造的该侧壁以外的多个区域移除该侧壁材料。
17.如权利要求13所述的方法,还包含以下步骤:
在该沉积步骤之后,涂敷一层填充材料遍布该构造与该层的侧壁材料上;及
回蚀在该构造的顶端上的该层填充材料与该层的侧壁材料,以留下实质上平坦的表面并在该实质上平坦的表面露出该侧壁上的该侧壁材料。
18.如权利要求17所述的方法,其中该回蚀步骤包含化学机械抛光。
19.如权利要求13所述的方法,其中该构造具有小于1微米的厚度,且侧壁间隙壁沿着该侧壁具有小于1微米的长度。
20.如权利要求13所述的方法,其中该构造具有小于0.5微米的厚度,且该侧壁间隙壁沿着该侧壁具有小于0.5微米的长度。
21.如权利要求13所述的方法,其中该构造中该第一、二绝缘层为介电材料,该第一、二导电层为薄膜电极,且该侧壁材料包含与该至少一导电层电气连通的导电材料。
22.如权利要求13所述的方法,其中该构造中该第一、二绝缘层为介电材料,该第一、二导电层为薄膜电极,且该侧壁材料包含与该至少一导电层电气连通的一种半导体材料。
23.如权利要求13所述的方法,其中该电极堆栈通过一光刻处理和该平版印刷处理其中之一的方式所制成。
24.如权利要求13所述的方法,其中依据一图案来选择性地蚀刻该侧壁材料,且依据该图案蚀刻后所界定出该侧壁间隙壁的宽度小于40nm。
25.一种装置,包含:
电极堆栈的构件,其至少依序包括第一导电层、第一绝缘层、第二导电层、和第二绝缘层堆栈而成,该第一、二导电层由该第一绝缘层分离,且该构件于该电极堆栈的表面上具有侧壁;及
侧壁间隙壁,其沿着该构件的该侧壁设置,使该电极堆栈与该侧壁间隙壁构成内存单元。
26.如权利要求25所述的装置,其中该间隙壁具有沿着该侧壁的长度、大致垂直于该长度的宽度及厚度,其中该宽度与该厚度小于40nm。
27.如权利要求25所述的装置,其中该侧壁间隙壁具有10至20nm的厚度。
28.如权利要求25所述的装置,其中该构造具有小于1微米的厚度,且该侧壁间隙壁沿着该侧壁具有小于1微米的长度。
29.如权利要求25所述的装置,其中该构造具有小于0.5微米的厚度,且该侧壁间隙壁沿着该侧壁具有小于0.5微米的长度。
30.如权利要求25所述的装置,其中该构造中该第一、二绝缘层为介电材料,该第一、二导电层为薄膜电极,且侧壁材料包含与该至少一导电层电气连通的导电材料。
31.如权利要求25所述的装置,其中该构造中该第一、二绝缘层为介电材料,该第一、二导电层为薄膜电极,且该侧壁材料包含与该至少一导电层电气连通的一种半导体材料。
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-
2005
- 2005-11-21 US US11/285,525 patent/US20060108667A1/en not_active Abandoned
- 2005-11-21 US US11/285,473 patent/US7608503B2/en not_active Expired - Fee Related
- 2005-11-22 TW TW094141002A patent/TWI355045B/zh active
- 2005-11-22 TW TW094141001A patent/TW200623474A/zh unknown
- 2005-11-22 CN CN2010105838799A patent/CN102088059A/zh active Pending
- 2005-11-22 CN CNA2005101248255A patent/CN1917248A/zh active Pending
- 2005-11-22 CN CN2005101248240A patent/CN1819297B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1819297A (zh) | 2006-08-16 |
TW200633145A (en) | 2006-09-16 |
US7608503B2 (en) | 2009-10-27 |
US20060110878A1 (en) | 2006-05-25 |
CN1819297B (zh) | 2013-08-21 |
TWI354386B (zh) | 2011-12-11 |
US20060108667A1 (en) | 2006-05-25 |
TW200623474A (en) | 2006-07-01 |
CN1917248A (zh) | 2007-02-21 |
TWI355045B (en) | 2011-12-21 |
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