CN102129168B - Photoresist graph correction method - Google Patents
Photoresist graph correction method Download PDFInfo
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- CN102129168B CN102129168B CN 201010022719 CN201010022719A CN102129168B CN 102129168 B CN102129168 B CN 102129168B CN 201010022719 CN201010022719 CN 201010022719 CN 201010022719 A CN201010022719 A CN 201010022719A CN 102129168 B CN102129168 B CN 102129168B
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Abstract
The invention discloses a photoresist graph correction method. The method comprises the following steps of: establishing a database of a relationship among the transmission rate of the area of a photoresist graph exposed from a substrate to the area of the substrate, a photoresist graph after develop inspection-critical dimension (ADI-CD) and an etching correction time; providing the substrate, wherein a dielectric layer is formed on the surface of the substrate; forming the photoresist graph on the surface of the dielectric layer; selecting the etching correction time from the database according to the transmission rate of the area of the photoresist graph exposed from the substrate to the area of the substrate and the photoresist graph ADI-CD; and performing etching correction on the photoresist graph by adopting the etching correction time. Grooves formed by the corrected photoresist graph provided by the method have small etching deviation and high efficiency.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly the modification method of photoresist figure.
Background technology
At present; Development along with VLSI (very large scale integrated circuits); The circuit design size is more and more littler; When particularly having arrived the technology below the 65nm, the variation of the characteristic dimension of circuit (Critical Dimension) is also increasing for the influence of device performance, and for example the feature size variations of circuit can directly cause the variation of device travelling speed.
Owing to receive the influence of the resolution limit (ResolutionLimit) of exposure bench (Optical Exposure Tool); Carrying out exposure technology when being transferred to circuitous pattern on the photoresist, just be easy to produce deviation to being formed on circuitous pattern on the mask (Mask).In U.S. Pat 6042973, can find to form the resolution of the inferior parsing fence (Sub-resolution Grating) of sub-circular in order to the raising circuitous pattern at the circuitous pattern edge, but the deviation that this method can't avoid circuitous pattern to shift.For fear of the deviation that mask pattern shifts, existing semiconductor technology all is to utilize drift correction to overcome the deviation that existing mask pattern shifts, and concrete steps comprise:
Semiconductor substrate is provided;
On said Semiconductor substrate, form photoresist layer;
Said photoresist layer is made public, develops, form the photoresist figure;
(After Develop Inspection-CriticalDimension ADI-CD) checks to the characteristic dimension of the said photoresist figure after developing;
Confirm to revise the deviation of photoresist figure according to ADI-CD.
But; Development along with VLSI (very large scale integrated circuits); The existing modification method of confirming to revise the deviation of photoresist figure according to ADI-CD has certain limitation, for the photoresist figure of different batches, all need confirm ADI-CD at every turn; Confirm the modification method of the deviation of correction photoresist figure then according to ADI-CD, above-mentioned modification method efficient is lower.
Summary of the invention
The problem that the present invention solves provides the modification method of the deviation of effective correction photoresist figure.
For addressing the above problem, the present invention provides a kind of modification method of deviation of photoresist figure, comprising: set up the photoresist figure and expose the area of substrate and ratio, photoresist figure ADI-CD and the database of etching correction time of Substrate Area; Substrate is provided, and said substrate surface is formed with dielectric layer; Form the photoresist figure on said dielectric layer surface; Expose the area of substrate and the ratio and the said photoresist figure ADI-CD of Substrate Area according to said photoresist figure, the selective etching correction time from database, adopt the said etching correction time that said photoresist figure is carried out the etching correction.
Compared with prior art; The present invention has the following advantages: set up the photoresist figure and expose the area of substrate and ratio, photoresist figure ADI-CD and the database of etching correction time of Substrate Area; Expose the area of substrate and the ratio selective etching correction time of Substrate Area according to the photoresist figure, the etching groove deviation that adopts revised photoresist figure to form is little.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Fig. 1 is the schematic flow sheet of photoresist figure modification method one embodiment provided by the invention;
Fig. 2 to Fig. 6 is the process synoptic diagram of photoresist figure modification method one embodiment provided by the invention;
Fig. 7 carries out the synoptic diagram that etching forms groove for being mask with the corrected photoresist figure of the present invention to said dielectric layer.
Embodiment
Can know by background technology; Development along with VLSI (very large scale integrated circuits); The existing modification method of confirming to revise the deviation of photoresist figure according to ADI-CD has certain limitation, for the photoresist figure of different batches, all need confirm ADI-CD at every turn; Confirm to revise the modification method of the deviation of photoresist figure then according to ADI-CD, efficient is lower.
For this reason, inventor of the present invention analyzes above-mentioned experiment through a large amount of experiments; The photoresist figure that discovery has different batches has different pitch (Pitch), has intensity (Dense) and sparse type different patterns distribution situations such as (Iso), for this reason; Inventor of the present invention takes all factors into consideration the photoresist figure difference of different batches; Propose a kind of photoresist figure modification method of optimization,, comprising with reference to figure 1:
Step S101 sets up the photoresist figure and exposes the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD and etching correction time relationship database;
Step S102 provides substrate, and said substrate surface is formed with dielectric layer;
Step S103 forms the photoresist figure on said dielectric layer surface;
Step S104 exposes the area of substrate and the ratio and the said photoresist figure ADI-CD of Substrate Area according to said photoresist figure, the selective etching correction time from database, adopts the said etching correction time that said photoresist figure is carried out the etching correction.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes synoptic diagram to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The sectional view of expression device architecture can be disobeyed general ratio and done local the amplification, and said synoptic diagram is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 to Fig. 6 is the process synoptic diagram of photoresist figure modification method one embodiment provided by the invention, does detailed explanation below in conjunction with Fig. 1 to Fig. 6 specific embodiments of the invention.
Step S101 sets up the photoresist figure and exposes the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD and the database of etching correction time.
Said photoresist figure exposes the area of substrate and the ratio of Substrate Area (TransmissionRate) exposes the area of substrate and the ratio of Substrate Area for the photoresist figure that is formed on the substrate; But calculate said photoresist figure and expose the area of substrate and the ratio of Substrate Area for convenient, also can carry out mathematical statistics and be similar to and obtain the value of ratio that the photoresist figure exposes area and the Substrate Area of substrate the mask that forms said photoresist figure.
Inventor of the present invention is through a large amount of experiments; Find that different photoresist figures exposes the area of substrate and the ratio of Substrate Area (Transmission Rate) is as shown in Figure 2 with the etching deviation of the groove that adopts said photoresist to form; Experimental data to Fig. 2 is carried out the mathematics match; Obtaining the relational expression that etching deviation and photoresist figure expose the area of substrate and the ratio of Substrate Area (Transmission Rate) is y=0.0017x-0.0465; For further understanding the present invention, with concrete data instance, shown in the A point of Fig. 2; When the photoresist figure exposed the area of substrate and the ratio of Substrate Area (Transmission Rate) and is 30.3 (unit is %), etching deviation was about 0.002 (unit is μ m); Shown in the B point of Fig. 2, when the photoresist figure exposed the area of substrate and the ratio of Substrate Area (Transmission Rate) and is 46.8 (unit is %), etching deviation was about 0.003 (unit is μ m).Can know that from above-mentioned data analysis expose the variation of ratio of area and the Substrate Area of substrate along with the photoresist figure, etching deviation also changes thereupon.
For this reason; The inventor exposes the correction time that the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD confirm etching according to the photoresist figure, and Fig. 3 is that the photoresist figure that the present invention sets up exposes the area of substrate and the ratio of Substrate Area (TransmissionRate), photoresist figure ADI-CD and the graph of a relation of etching correction time.As shown in Figure 3, make according to simulation or through actual process, collect data, set up the photoresist figure and expose the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD and the relational database of etching correction time.
Step S102 provides substrate, and said substrate surface is formed with dielectric layer.
With reference to figure 4; Said substrate 100 can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.
Still with reference to figure 4; Said substrate 100 surfaces are formed with dielectric layer 110; Said dielectric layer 110 is used for active area in the substrate 100 and the isolation between the active area perhaps are used for lead on the substrate 100 and the isolation between the lead, and the thickness of said dielectric layer 110 is 20 nanometer to 5000 nanometers.
Concrete said dielectric layer 110 can be before-metal medium layer (Pre-Metal Dielectric; PMD), also can be interlayer dielectric layer (Inter-Metal Dielectric, ILD); What need particularly point out is that said dielectric layer can also be that single coating also can be the multiple-level stack structure.
Before-metal medium layer is to be deposited on the substrate with MOS device; Utilize depositing operation to form; In before-metal medium layer, can form groove at subsequent technique, form connecting hole with metal filled groove, said connecting hole is used for connecting the electrode of MOS device and the plain conductor of upper layer interconnects layer.
Interlayer dielectric layer is the dielectric layer of postchannel process between metal interconnecting layer, can in subsequent technique, form groove in the interlayer dielectric layer, forms connecting hole with metal filled groove, and said connecting hole is used for connecting the lead of adjacent metal interconnects layer.
The material of said dielectric layer 110 is selected from SiO usually
2The SiO that perhaps mixes
2USG (Undoped Silicon Glass for example; The silex glass that does not have doping), BPSG (BorophosphosilicateGlass; The silex glass of boron phosphorus doped), BSG (Borosilicate Glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Said dielectric layer 110 generally selects for use the dielectric material of low-k, the material of said dielectric layer 110 specifically to be selected from the silit (BLOK) that monox (Black Diamond) that fluorine silex glass (FSG), carbon mix and nitrogen mix at 130 nanometers and following process node.
The formation technology of said dielectric layer 110 can be any conventional vacuum coating technology; For example atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like are not here done and are given unnecessary details.
Step S103 forms the photoresist figure on said dielectric layer surface.
In the present embodiment, said photoresist figure is used to define groove figure, and as the mask of groove figure, said photoresist figure thickness is 500 nanometers to 2 micron.
With reference to figure 5, the formation step of said photoresist figure 120 comprises: form photoresist layer (not shown) on said dielectric layer 110 surfaces; To said photoresist layer exposure imaging, form photoresist figure 120.
Step S104 exposes the area of substrate and the ratio and the said photoresist figure ADI-CD of Substrate Area according to said photoresist figure, the selective etching correction time from database, adopts the said etching correction time that said photoresist figure is carried out the etching correction.
With reference to figure 6, said etching correction also can consume certain photoresist figure 120 thickness when revising said photoresist figure 120, but because the thickness of photoresist figure 120 is enough thick, the etching correction can full consumption photoresist figure 120.
What need particularly point out is; Said etching correction using plasma etching technics, the concrete parameter of said plasma etch process comprises: the selective etching correction time from database, etching cavity pressure is 10 millitorr to 300 millitorrs; Etching power is 50 watts to 200 watts, and etching gas is CF
4, CF
4Flow is 10SCCM to 50SCCM, and assist gas is Ar, and the Ar flow is 10SCCM to 50SCCM.
With reference to figure 7; Above-mentioned technology is mask with said corrected photoresist figure 120 after accomplishing, and said dielectric layer 110 is carried out etching; Form groove 111; Can know that by narration before expose the area of substrate and ratio of Substrate Area (Transmission Rate) and ADI-CD owing to take all factors into consideration the photoresist figure, the etching deviation of said groove 111 is less.
The present invention exposes ratio and said photoresist figure ADI-CD, the database of etching correction time of area and the Substrate Area of substrate according to said photoresist figure; The selective etching correction time from database; Said photoresist figure is carried out the etching correction, and the etching groove deviation that adopts revised photoresist figure to form is little.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the modification method of a photoresist figure comprises:
The relational expression of ratio that exposes area and the Substrate Area of substrate according to etching deviation and photoresist figure is that y=0.0017x-0.0465, experimental simulation or actual process are made, and sets up the photoresist figure and exposes the area of substrate and ratio, photoresist figure ADI-CD and the etching correction time relationship database of Substrate Area;
Substrate is provided, and said substrate surface is formed with dielectric layer;
Form the photoresist figure on said dielectric layer surface;
Expose the area of substrate and the ratio and the said photoresist figure ADI-CD of Substrate Area according to said photoresist figure, the selective etching correction time from database, adopt the said etching correction time that said photoresist figure is carried out the etching correction.
2. the modification method of photoresist figure as claimed in claim 1 is characterized in that, also comprises step: with said corrected photoresist figure is mask, and said dielectric layer is carried out etching, forms groove.
3. the modification method of photoresist figure as claimed in claim 1 is characterized in that, said photoresist figure is used to define groove figure.
4. the modification method of photoresist figure as claimed in claim 1 is characterized in that, the technology of said etching correction is plasma etch process.
5. the modification method of photoresist figure as claimed in claim 4 is characterized in that, the concrete parameter of said plasma etch process comprises: etching cavity pressure is 10 millitorr to 300 millitorrs, and etching power is 50 watts to 200 watts, and etching gas is CF
4, CF
4Flow is 10SCCM to 50SCCM, and assist gas is Ar, and the Ar flow is 10SCCM to 50SCCM.
6. the modification method of photoresist figure as claimed in claim 1 is characterized in that, the formation step of said photoresist figure comprises: form photoresist layer on said dielectric layer surface; To said photoresist layer exposure imaging, form the photoresist figure.
7. the modification method of photoresist figure as claimed in claim 1 is characterized in that, said photoresist layer thickness is 500 nanometers to 2 micron.
8. the modification method of photoresist figure as claimed in claim 1 is characterized in that, said dielectric layer is single coating or multiple-level stack structure.
9. the modification method of photoresist figure as claimed in claim 1 is characterized in that, said substrate is multi layer substrate, classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, substrate, the patterning of section processes or the substrate that is not patterned.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010022719 CN102129168B (en) | 2010-01-12 | 2010-01-12 | Photoresist graph correction method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010022719 CN102129168B (en) | 2010-01-12 | 2010-01-12 | Photoresist graph correction method |
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| CN102129168A CN102129168A (en) | 2011-07-20 |
| CN102129168B true CN102129168B (en) | 2012-12-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108020991A (en) * | 2016-10-31 | 2018-05-11 | 无锡中微掩模电子有限公司 | Mask plate for integrated circuit carries on the back exposure method |
| CN110928149B (en) * | 2018-09-20 | 2024-04-19 | 长鑫存储技术有限公司 | Control method and control system for critical dimension |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320402B1 (en) * | 2000-02-03 | 2001-11-20 | Advanced Micro Devices Inc | Parallel inspection of semiconductor wafers by a plurality of different inspection stations to maximize throughput |
| CN1349245A (en) * | 2000-10-17 | 2002-05-15 | 联华电子股份有限公司 | Method of improving outline of photoresist pattern |
| CN1881087A (en) * | 2005-06-17 | 2006-12-20 | 台湾积体电路制造股份有限公司 | Mask CD correction based on global pattern density |
| CN101047109A (en) * | 2006-03-29 | 2007-10-03 | 台湾积体电路制造股份有限公司 | Critical dimension (CD) control method by spectrum metrology |
| CN101430566A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for controlling etching deviation |
| CN101592858A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Revise the method for photoresist pattern error |
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2010
- 2010-01-12 CN CN 201010022719 patent/CN102129168B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320402B1 (en) * | 2000-02-03 | 2001-11-20 | Advanced Micro Devices Inc | Parallel inspection of semiconductor wafers by a plurality of different inspection stations to maximize throughput |
| CN1349245A (en) * | 2000-10-17 | 2002-05-15 | 联华电子股份有限公司 | Method of improving outline of photoresist pattern |
| CN1881087A (en) * | 2005-06-17 | 2006-12-20 | 台湾积体电路制造股份有限公司 | Mask CD correction based on global pattern density |
| CN101047109A (en) * | 2006-03-29 | 2007-10-03 | 台湾积体电路制造股份有限公司 | Critical dimension (CD) control method by spectrum metrology |
| CN101430566A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for controlling etching deviation |
| CN101592858A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Revise the method for photoresist pattern error |
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Effective date of registration: 20121102 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |