CN102148186B - Method for manufacturing semiconductor device - Google Patents
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- CN102148186B CN102148186B CN 201010110470 CN201010110470A CN102148186B CN 102148186 B CN102148186 B CN 102148186B CN 201010110470 CN201010110470 CN 201010110470 CN 201010110470 A CN201010110470 A CN 201010110470A CN 102148186 B CN102148186 B CN 102148186B
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Abstract
The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps of: providing a front end device layer; forming an etching stop layer on the surface of the front end device layer; forming an interlayer dielectric layer on the surface of the etching stop layer; etching the interlayer dielectric layer and the etching stop layer by using a first mask to form a first through hole; forming a first metal layer in the first through hole; forming a first transition layer on the surfaces of the first metal layer and the interlayer dielectric layer; forming a second metal layer on the surface of the first transition layer; forming a second transition layer on the surface of the second metal layer; etching the second transition layer, the second metal layer and the first transition layer in sequence by using a second mask; forming a passivation layer on the surfaces of the interlayer dielectric layer and the second transition layer; and etching the passivation layer above the second transition layer by using a third mask to form a passivation layer through hole.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of method of making semiconductor device.
Background technology
The performance of high-end micro-chip processor more and more is subject to the restriction of the signal transferring lag in the interconnection wiring, and each equipment room that this interconnection wiring is used in this chip keeps connecting.In the interconnection that usually is referred to as backend process (BEOL), the delay in these wires represents by the product of associated resistance R and capacitor C.Along with improving constantly of chip integration, copper has replaced aluminium becomes the main flow interconnection technique of very lagre scale integrated circuit (VLSIC) in making.As the substitute of aluminium, copper conductor can reduce interconnection impedance, reduces power consumption and cost, improves integrated level, device density and the clock frequency of chip.When adopting copper to replace aluminium to reduce R in BEOL wiring, the minimizing of C can realize by reducing around the dielectric constant of the dielectric of interconnection wiring.Adopted the IMD that inter-metal dielectric (IMD) is changed over lower k from silicon dioxide (dielectric constant k is about 4), such as fluoro silicon dioxide (k is about 3.6) and spin coating forms by CVD or on film organosilicate (k is greatly about 2.7～3.2), with the electric capacity of further reduction BEOL.In the technique of making semiconductor interconnect structure, the aluminum cushion layer that the aluminium lamination of last layer pattern forms array is that I/O (I/O) or power supply/ground signalling provide connection.
The method of traditional making interconnection structure is shown in Figure 1A to 1F.
At first, shown in Figure 1A, one front end device layer 101 is provided, this front end device layer 101 comprises formed device architecture layer in the preorder technique, such as metal interconnect structure layer etc., the concrete conductor layer 100 that is exemplified as is formed in the front end device layer 101, and conductor layer 100 is the metal level that need to be drawn out to device surface, for example copper.Form the first etching stop layer 102 at front end device layer 101, material can be chosen as silicon nitride, and generation type can be chosen as CVD (chemical vapour deposition (CVD)) method.Then, form one deck interlayer dielectric layer 103 on the surface of the first etching stop layer 102, material can be but be not limited to a kind of or its combination in silica, carborundum, silicon nitride, carbon silicon oxide compound, the nitrogen-doped silicon carbide.
Then, as shown in Figure 1B, use Damascus technics, adopt first the first mask plate (not shown), with the dry etching method interlayer dielectric layer 103 is carried out etching, form through hole.Adopt again the second mask plate (not shown), interlayer dielectric layer 103 is carried out dry etching, form Damascus through hole 104.Again the first etching stop layer 102 is carried out etching, with the first etching stop layer 102 openings.
Then, shown in Fig. 1 C, adopt and electroplate or the CVD method, in Damascus through hole 104, fill the copper metal, and adopt chemico-mechanical polishing (CMP) technique, make the top of copper metal concordant with the top of interlayer dielectric layer 103, form the first metal layer 105.
Next, shown in Fig. 1 D, at interlayer dielectric layer 103 and deposition one deck the second etching stop layer 106 above the first metal layer 105, material can be but be not limited to silicon nitride.Then form the first passivation layer 107 on the surface of the second etching stop layer 106.Adopt the 3rd mask plate (not shown), use the dry etching method, etching the first passivation layer 107 and the second etching stop layer 106 form the first through hole 108 successively.
Then, shown in Fig. 1 E, at the first through hole 108 interior deposition one deck tantalum nitrides 109, then at the surface deposition layer of metal layer of the first through hole 108 and the first passivation layer 107, material is chosen as aluminium.Then form one deck titanium nitride layer on the surface of aluminum metal.Adopt the 4th mask plate (not shown), successively titanium nitride layer and metal level are carried out etching, form the figuratum aluminum cushion layer 110 of tool and titanium nitride layer 111.
Next, shown in Fig. 1 F, the mode on the surface of titanium nitride layer 111 and the first passivation layer with CVD forms the second passivation layer 112, adopts the CVD method to form layer protective layer 113 on the surface of the second passivation layer, and material can be but be not limited to silicon nitride.Adopt the 5th mask plate (not shown), successively protective layer 113 and the second passivation layer 112 are carried out etching, form the second through hole 114, expose titanium nitride layer 111, in order to carry out the follow-up techniques such as detection.
Yet the manufacture method of this traditional interconnection structure is so that the cost of manufacture of semiconductor device is higher.This be because, the price of the mask that adopts in the interconnection process is very expensive, and generally can use five masks in traditional interconnection process, this has increased the cost of making semiconductor device greatly, changing lamina membranacea has also increased the step that technique is made.And owing to need to carry out multiple etching technique, not only more improved the cost of manufacture of semiconductor device, make product not have competitiveness, more can cause potential harm to the structure of semiconductor device owing to etching technics, such as plasma damage etc., this can reduce the yields of semiconductor device, destroys the overall performance of semiconductor device.
Therefore, need a kind of method, can make better the interconnection structure in the semiconductor device, its production cost is descended, work simplification in order to improve the overall performance of semiconductor device, improves yields.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to make better the interconnection structure in the semiconductor device, the present invention proposes the manufacture method of interconnection structure in a kind of semiconductor device, comprise step: provide a front end device layer; Surface at described front end device layer forms one deck etching stop layer; Surface at described etching stop layer forms one deck interlayer dielectric layer; Adopt the first mask that described interlayer dielectric layer and described etching stop layer are carried out etching, form the first through hole; In described the first through hole, form the first metal layer; Surface at described the first metal layer and described interlayer dielectric layer forms the First Transition layer; Form the second metal level on the surface of described First Transition layer; Form the second transition zone on the surface of described the second metal level; Adopt the second mask, successively etching the second transition zone, the second metal level and First Transition layer; Surface at described interlayer dielectric layer and described the second transition zone forms one deck passivation layer; Adopt the 3rd mask etching passivation layer above described the second transition zone, form the passivation layer through hole.
Preferably, also comprise,
Surface at described passivation layer also forms layer protective layer, when adopting described the 3rd mask to carry out etching described passivation layer and described protective layer is carried out etching together.
Preferably, the material of described the second metal level is aluminium.
Preferably, the material of described First Transition layer is tantalum nitride, and the material of described the second transition zone is titanium nitride.
Preferably, described front end device layer includes a conductor layer, and the below that described conductor layer is positioned at described the first metal layer contacts with described the first metal layer.
Preferably, the second transition zone after the described etching, described the second metal level and described First Transition layer cover described the first metal layer and the described interlayer dielectric layer of part.
The present invention also provides a kind of semiconductor device, comprising: the front end device layer; One deck etching stop layer that forms on the surface of described front end device layer; One deck interlayer dielectric layer that forms on the surface of described etching stop layer; The first through hole that connects described etching stop layer upper and lower surface and connect described interlayer dielectric layer upper and lower surface; The first metal layer that in described the first through hole, forms; The First Transition layer that forms on the surface of described the first metal layer and the described interlayer dielectric layer of part; The second metal level that forms on the surface of described First Transition layer; The second transition zone in described the second layer on surface of metal formation; The passivation layer that forms on the surface of described interlayer dielectric layer and described the second transition zone; On described the second transition zone and connect the passivation layer through hole of described passivation layer upper and lower surface.
Preferably, also comprise,
The layer protective layer that also forms on the surface of described passivation layer also has the protective layer through hole that run through passivation layer consistent with the passivation layer lead to the hole site.
Preferably, the material of described the second metal level is aluminium.
Preferably, the material of described First Transition layer is tantalum nitride, and the material of described the second transition zone is titanium nitride.
Preferably, the conductor layer that described front end device layer includes, the described conductor layer below that is positioned at described the first metal layer contacts with described the first metal layer.
Preferably, described the second transition zone, described the second metal level and described First Transition layer cover described the first metal layer and the described interlayer dielectric layer of part.
According to the present invention, can make better the interconnection structure in the semiconductor device, its production cost is descended, work simplification in order to improve the overall performance of semiconductor device, improves yields.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 F is the cross-sectional view of the semiconductor device of traditional making interconnection structure;
Fig. 2 A to 2E is the cross-sectional view according to the making semiconductor interconnect structure of the embodiment of one aspect of the invention;
Fig. 3 is that making is according to the process chart of the making semiconductor interconnect structure of the embodiment of one aspect of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explanation the present invention adopts new process to make semiconductor device in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
With reference to Fig. 2 A to Fig. 2 E, the method according to the making semiconductor interconnect structure of the embodiment of one aspect of the invention is shown.
Shown in Fig. 2 A, provide a front end device layer 201.This front end device layer 201 comprises formed device architecture layer in the preorder technique, such as metal interconnect structure layer that forms at substrate etc., wherein substrate can be chosen as silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, it also can be silicon-on-insulator (SOI), the material that can also comprise other, such as indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.Be formed with a conductor layer 200 in the front end device layer 201.Conductor layer 200 is the metal levels that need to be drawn out to device surface, copper for example, and conductor layer 200 is positioned at the below of the first metal layer that next will deposit and contacts with the first metal layer.。Surface at front end device layer 201 forms one deck etching stop layer 202, and material can be chosen as silicon nitride, and generation type can be chosen as the CVD method.Then, form one deck interlayer dielectric layer 203 on the surface of etching stop layer 202, material can be but be not limited to a kind of or its combination in silica, carborundum, silicon nitride, carbon silicon oxide compound, the nitrogen-doped silicon carbide.
Shown in Fig. 2 B, adopt the first mask plate (not shown), interlayer dielectric layer 203 and etching stop layer 202 are carried out etching, form the first through hole 204, namely connect the first through hole 204 of interlayer dielectric layer 203 upper and lower surfaces and etching stop layer 202 upper and lower surfaces, make interlayer dielectric layer 203 and etching stop layer 202 have patterns of openings.
Shown in Fig. 2 C, adopt CVD or PVD method, in the first through hole 204, form the first metal layer 205, material is chosen as copper.Surface at the first metal layer 205 forms First Transition layer 206, and thickness is approximately 500～1000 dusts, is preferably 850 dusts.First Transition layer 206 can be individual layer or multilayer, can adopt PVD (physical vapour deposition (PVD)), CVD, vacuum evaporation, pulsed laser deposition (PLD) or other existing plated film mode to form.Material can be but be not limited to tantalum nitride.For example, select the standby First Transition layer 203 of PVD legal system, the employing metal tantalum is target, and the atmosphere of deposition is the mist of argon gas and nitrogen, at 100～120 degrees centigrade of lower tantalum nitrides that form.The effect of First Transition layer 206 be can make the first metal layer 205 take copper as material and second metal level 207 take aluminium as material that next will form between form good transition, and stopped the mutual diffusion between copper metal and the aluminum metal.The material that forms one deck the second metal level 207, the second metal levels 207 on the surface of First Transition layer 206 is chosen as aluminium, and thickness is approximately 5000～8000 dusts.Then form the second transition zone 208 on the surface of the second metal level 207, material can be but be not limited to titanium nitride, and generation type can be PVD, CVD, vacuum evaporation, pulsed laser deposition or other existing plated film mode.The second transition zone 208 can protect better the second metal level 207.Then at the surface of the second transition zone 208 coating one deck photoresist layer, adopt the second mask plate (not shown), form figuratum the first photoresist layer 209 of tool by patterns such as exposure imagings.
Shown in Fig. 2 D, take the first photoresist layer 209 as mask, etching the second transition zone 208, the second metal level 207 and First Transition layer 206 form figuratum the second transition zone 208 ' of tool, figuratum the second metal level 207 ' of tool and the figuratum First Transition layer 206 ' of tool successively.The second transition zone 208 ' after the etching, the second metal level 207 ' and First Transition layer 206 ' cover described the first metal layer 205 and the described interlayer dielectric layer 203 of part.Used lithographic method adopts dry etching.Then, adopt the ashing mode to remove the first photoresist layer 209.
Shown in Fig. 2 E, surface at the second transition zone 208 ' and interlayer dielectric layer 203 forms one deck passivation layer 210, generation type is CVD method or PVD method, and thickness is approximately 7000～10000 dusts, and material can be but be not limited to silicon nitride, silica, silicon oxynitride, polyimides etc.Passivation layer 210 can be individual layer or sandwich construction, for example, using plasma chemical vapour deposition (CVD) (PECVD), sandwich construction comprises silicon nitride, silica and/or silicon oxynitride.Then, form layer protective layer 211 on the surface of passivation layer 210 with CVD or PVD mode, material can be but be not limited to silicon nitride.Then; adopt the 3rd mask (not shown); utilize the dry etching method successively protective layer 211 and passivation layer 210 to be carried out etching; form the second through hole 212 in the top of the second transition zone 208 '; the second through hole 212 that namely runs through passivation layer 210 and protective layer 211; make passivation layer 210 and protective layer 211 have patterns of openings; the hole of running through passivation layer 210 is the passivation layer through hole; the hole of running through protective layer 211 is the protective layer through hole, and passivation layer through hole and protective layer through hole have consisted of the second through hole 212 jointly.Then, carry out follow-up packaging technology, in order to finish the making of whole chip.
Interconnection structure according to the present embodiment making, three mask plates have only been adopted, the first mask plate that adopts when namely forming the first through hole, the second mask plate that adopts when making figuratum the first photoresist layer 209 of tool and the 3rd mask plate that adopts when forming the second through hole 212, this has saved two mask plates compared with five mask plates that adopt in the traditional handicraft, has greatly saved cost of manufacture.And because the minimizing of the mask plate that adopts so that associated processing step reduces, has reduced cost of manufacture more.
The present invention adopts copper in the aluminium substitution traditional handicraft as the top layer metallic layer in the interconnection structure, be the first metal layer 105 in the traditional handicraft, this is so that top layer metallic layer and passivation layer associativity are better, and this is conducive to follow-up packaging technology, and because the characteristic of aluminium itself is easier to patterning.The present embodiment merges making with the aluminum cushion layer in the traditional manufacturing technique and top layer metallic layer, be in the traditional handicraft the first metal layer 105 and aluminum cushion layer 110 to realize with the second metal level 207 in the present embodiment, this has greatly reduced processing step, saved cost of manufacture, shortened the production cycle, made output higher.
The flow chart of Fig. 3 shows making and adopts according to an embodiment of the invention the process chart that improves technique making semiconductor interconnect structure.In step 301, provide a front end device layer.In step 302, form one deck etching stop layer on the surface of front end device layer, form one deck interlayer dielectric layer on the surface of etching stop layer.In step 303, adopt the first mask plate that interlayer dielectric layer and etching stop layer are carried out etching, form the first through hole.In step 304, in the first through hole, form the first metal layer, form the First Transition layer on the surface of the first metal layer, form one deck the second metal level on the surface of First Transition layer, form the second transition zone on the surface of the second metal level.In step 305, at the surface of the second transition zone coating one deck photoresist layer, form figuratum the first photoresist layer of tool by patterns such as exposure imagings.In step 306, take the first photoresist layer as mask, successively etching the second transition zone, the second metal level and First Transition layer.In step 307, adopt the ashing mode to remove the first photoresist layer.In step 308, form one deck passivation layer on the surface of the second transition zone and interlayer dielectric layer, form layer protective layer on the surface of passivation layer.In step 309, adopt the 3rd mask successively protective layer and passivation layer to be carried out etching, form the second through hole.
Adopt the semiconductor device of the semiconductor interconnect structure that new process makes to can be applicable in the multiple integrated circuit (IC) according to having of as above embodiment manufacturing.For example be memory circuitry according to IC of the present invention, such as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, such as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or any other circuit devcies.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. method of making semiconductor device comprises step:
One front end device layer is provided;
Surface at described front end device layer forms one deck etching stop layer;
Surface at described etching stop layer forms one deck interlayer dielectric layer;
Adopt the first mask that described interlayer dielectric layer and described etching stop layer are carried out etching, form the first through hole;
In described the first through hole, form the first metal layer;
Surface at described the first metal layer and described interlayer dielectric layer forms the First Transition layer;
Form the second metal level on the surface of described First Transition layer;
Form the second transition zone on the surface of described the second metal level;
Adopt the second mask, successively etching the second transition zone, the second metal level and First Transition layer;
Surface at described interlayer dielectric layer and described the second transition zone forms one deck passivation layer;
Adopt the 3rd mask etching passivation layer above described the second transition zone, form the passivation layer through hole.
2. method as claimed in claim 1 also comprises,
Surface at described passivation layer also forms layer protective layer, when adopting described the 3rd mask to carry out etching described passivation layer and described protective layer is carried out etching together.
3. method as claimed in claim 1 is characterized in that, the material of described the second metal level is aluminium.
4. method as claimed in claim 1 is characterized in that, the material of described First Transition layer is tantalum nitride, and the material of described the second transition zone is titanium nitride.
5. method as claimed in claim 1 is characterized in that, described front end device layer includes a conductor layer, and the below that described conductor layer is positioned at described the first metal layer contacts with described the first metal layer.
6. method as claimed in claim 1 is characterized in that, the second transition zone after the described etching, described the second metal level and described First Transition layer cover described the first metal layer and the described interlayer dielectric layer of part.
7. semiconductor device comprises:
The front end device layer;
One deck etching stop layer that forms on the surface of described front end device layer;
One deck interlayer dielectric layer that forms on the surface of described etching stop layer;
The first through hole that connects described etching stop layer upper and lower surface and connect described interlayer dielectric layer upper and lower surface;
The first metal layer that in described the first through hole, forms;
The First Transition layer that forms on the surface of described the first metal layer and the described interlayer dielectric layer of part;
The second metal level that forms on the surface of described First Transition layer;
The second transition zone in described the second layer on surface of metal formation;
The passivation layer that forms on the surface of described interlayer dielectric layer and described the second transition zone;
On described the second transition zone and connect the passivation layer through hole of described passivation layer upper and lower surface.
8. device as described in claim 7 also comprises,
The layer protective layer that also forms on the surface of described passivation layer also has the protective layer through hole that run through passivation layer consistent with the passivation layer lead to the hole site.
9. device as described in claim 7 is characterized in that, the material of described the second metal level is aluminium.
10. device as described in claim 7 is characterized in that, the material of described First Transition layer is tantalum nitride, and the material of described the second transition zone is titanium nitride.
11. device is characterized in that as described in claim 7, described front end device layer includes a conductor layer, and the below that described conductor layer is positioned at described the first metal layer contacts with described the first metal layer.
12. device is characterized in that as described in claim 7, described the second transition zone, described the second metal level and described First Transition layer cover described the first metal layer and the described interlayer dielectric layer of part.
13. an integrated circuit that comprises the semiconductor device of making by method as claimed in claim 1, wherein integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array and radio circuit.
14. an electronic equipment that comprises the semiconductor device of making by method as claimed in claim 1, wherein electronic equipment is selected from personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| US20220344554A1 (en) * | 2019-08-30 | 2022-10-27 | Boe Technology Group Co., Ltd. | Backplane, backlight source, display device and manufacturing method of backplane |
| CN111128934B (en) * | 2019-12-16 | 2021-08-24 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad structure and device comprising aluminum pad structure |
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