CN102148754A - Loading method and device for FPGA (field programmable gate array) logic editions - Google Patents
Loading method and device for FPGA (field programmable gate array) logic editions Download PDFInfo
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Abstract
The invention discloses a loading method and a device for FPGA (field programmable gate array) logic editions. An FPGA (field programmable gate array) logic edition used for hardware detecting and an FPGA (field programmable gate array) logic edition used for message forwarding are split; the FPGA (field programmable gate array) logic edition used for hardware detecting is loaded preferentially; after the hardware detecting function of the FPGA (field programmable gate array) logic edition used for hardware detecting is completely actuated, the FPGA (field programmable gate array) logic edition used for message forwarding is loaded; therefore, the FPGA (field programmable gate array) logic edition used for message forwarding after being loaded on a FPGA chip can obtain more space resources, and realize the purposes of leading a communication device to support more service demands and improving the forwarding performance of the communication device as well as the space resource utilization rate of the FPGA chip under the premise that the space resources of the FPGA chip is fixed.
Description
Technical field
The present invention relates to communication technical field, particularly a kind of loading method of fpga logic version and equipment.
Background technology
In the existing communication equipment; usually can adopt universal cpu (Central Processing Unit; central processing unit), NP (Network Processor; network processing unit) and ASIC (Application SpecificIntegrated Circuit, application-specific integrated circuit (ASIC)) as the message forwarding engine.But there is corresponding defective respectively in such forwarding mechanism:
When (1) adopting universal cpu to do forwarding engine, can be subject to the disposal ability of CPU, even adopt the strongest polycaryon processor of present industry, its transfer capability is also limited.
(2) adopt NP to do forwarding engine, be subject to programming resource and the programming complexity of NP, only can satisfy the forwarding high-performance of simple application scene, can't satisfy the professional high-performance of band and transmit demand.
(3) adopt ASIC to do forwarding engine, its specific aim is very strong, only can satisfy specific use occasion, and in addition, the cycle of developing a ASIC also can be very long, and early stage, development cost was too high.
This shows, develop a high-performance, multiple services communication equipment fast,, always have such or such deficiency if adopt above-mentioned three kinds of schemes.Therefore, seek other designs and satisfy the demands, become trend and inevitable.
FPGA (Field Programmable Gate Array, field programmable gate array) technology, compare and aforesaid three kinds of technology, therefore performance with better programmable features and Geng Gao, adopts fpga chip to do forwarding engine on communication equipment, not only can have high-performance, and, can satisfy the demand that complicated business is transmitted equally, its know-why schematic diagram is as shown in Figure 1.
In actual applications, adopt fpga chip as follows as the operation principle of the forwarding engine of communication equipment:
At first, according to the forwarding and the business demand of communication equipment, software programming fpga logic version.
After the system start-up, CPU is loaded into fpga chip inside with the fpga logic version and enables, and fpga chip will get up by the design work of fpga logic version.
After interface card is received message, be submitted to fpga chip, inner each the module cooperative work of fpga chip is finished message and is transmitted.
In above-mentioned whole repeating process, do not need the participation of CPU or other softwares, satisfied high performance forwarding demand.
In realizing process of the present invention, the inventor finds that there is following problem at least in prior art:
Increasing of the quantity of the business demand that need satisfy along with communication equipment, the size of fpga logic version will increase accordingly, and the space resources of the shared fpga chip of fpga logic version also can be many more thereupon.
In application process, the business demand specification of communication equipment (quantity of the business demand that communication equipment can satisfy) is The more the better naturally, and like this, the requirement specification of communication equipment and the space resources of fpga chip just become a pair of implacable contradiction.
Under the certain prerequisite of the space resources of fpga chip, can only satisfy the requirement specification that the space resources of this fpga chip can bear, if this communication equipment wants to realize more business demand, just can only upgrade has the fpga chip of more space resourcess, and the upgrading fpga chip will cause the significantly raising of equipment cost.
Therefore, how under the certain prerequisite of the space resources amount of fpga chip, in communication equipment, realize more business demand, just become the insurmountable difficult problem of prior art scheme.
Summary of the invention
The invention provides a kind of loading method and equipment of fpga logic version, in order to solve under the certain situation of the space resources of fpga chip, the problem of the more business demand of carrying of how utilizing space resources efficiently.
For achieving the above object, one aspect of the present invention provides a kind of loading method of fpga logic version, is applied to comprise in the communication equipment of fpga chip, and described method may further comprise the steps at least:
Described communication equipment is loaded into default FPGA test logic version in the described fpga chip, and by described FPGA test logic version described communication equipment self is carried out hardware detection;
Described communication equipment is preserved the object information of described hardware detection;
Described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted.
Preferably, described default FPGA test logic version is specially the one or more fpga logic versions that are used for realizing the relevant hardware of described fpga chip and described communication equipment is carried out state-detection;
Described default FPGA forwarding logic version is specially the fpga logic version that is used for carrying out according to the business demand of described communication equipment corresponding message forwarding.
Preferably, when described default FPGA test logic version was specially a plurality of fpga logic version, described method was specially:
Described communication equipment is loaded into a FPGA test logic version in described a plurality of FPGA test logic versions in the described fpga chip, and the FPGA test logic version by current loading carries out relevant hardware to described communication equipment and detects;
Described communication equipment is preserved the object information of described hardware detection;
Described communication equipment continues other FPGA test logic versions in described a plurality of FPGA test logic versions are loaded in the described fpga chip, carries out other hardware detection;
Until described communication equipment after all FPGA test logic versions have finished relevant hardware and detect in respectively according to described a plurality of FPGA test logic versions, described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted.
Preferably, when described default FPGA test logic version was specially a plurality of fpga logic version, described method was specially:
Described communication equipment is loaded into the whole FPGA test logic versions in described a plurality of FPGA test logic versions in the described fpga chip, and each the FPGA test logic version by current loading carries out the relevant hardware detection to described communication equipment respectively;
Described communication equipment is preserved the object information of described hardware detection;
Described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted.
Preferably, described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted, is specifically comprised:
Described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip;
The object information of the described hardware detection that described communication equipment will be preserved is written in the corresponding register series of described fpga chip;
Described fpga chip disposes self corresponding RAM controller according to the object information in the described register series;
Described communication equipment enables described FPGA forwarding logic version, and the received message of described communication equipment is transmitted.
On the other hand, the present invention also provides a kind of communication equipment, comprises fpga chip, and described communication equipment comprises:
Memory module is used to store FPGA test logic version and FPGA forwarding logic version;
Load-on module, the FPGA test logic version that is used for described memory module is stored is loaded into described fpga chip, after described FPGA test logic version was finished hardware detection, the FPGA forwarding logic version that described memory module is stored was loaded in the described fpga chip;
Processing module, the FPGA test logic version that is used for being loaded into by described load-on module described fpga chip carries out hardware detection, the object information of described hardware detection is saved in the described memory module, and after the FPGA forwarding logic version that described load-on module is stored described memory module is loaded in the described fpga chip, the described hardware detection result who stores according to described memory module disposes described fpga chip, by described FPGA forwarding logic version the message that described communication equipment receives is transmitted.
Preferably, the FPGA test logic version that described memory module is stored is specially the one or more fpga logic versions that are used for realizing the relevant hardware of described fpga chip and described communication equipment is carried out state-detection;
The FPGA forwarding logic version that described memory module is stored is specially the fpga logic version that is used for carrying out according to the business demand of described communication equipment corresponding message forwarding.
Preferably, when the FPGA test logic version of storing when described memory module was specially a plurality of fpga logic version, described load-on module specifically was used for:
A FPGA test logic version in a plurality of FPGA test logic versions that described memory module is stored is loaded in the described fpga chip, after described FPGA test logic version is finished hardware detection, continue other FPGA test logic versions in described a plurality of FPGA test logic versions are loaded in the described fpga chip, after all FPGA test logic versions had all been finished the relevant hardware detection in described a plurality of FPGA test logic versions, the FPGA forwarding logic version that described memory module is stored was loaded in the described fpga chip.
Preferably, when the FPGA test logic version of storing when described memory module was specially a plurality of fpga logic version, described load-on module specifically was used for:
Whole FPGA test logic versions in a plurality of FPGA test logic versions that described memory module is stored are loaded in the described fpga chip, after all FPGA test logic versions were finished hardware detection, the FPGA forwarding logic version that described memory module is stored was loaded in the described fpga chip.
Preferably, after the FPGA forwarding logic version that described load-on module is stored described memory module is loaded in the described fpga chip,
Described processing module, the object information that specifically is used for described hardware detection that described memory module is preserved writes the corresponding register series of described fpga chip, so that described fpga chip disposes corresponding RAM controller in the described fpga chip according to the object information in the described register series, and after the layoutprocedure of described fpga chip is finished, enable described FPGA forwarding logic version, the received message of described communication equipment is transmitted.
Compared with prior art, the present invention has the following advantages:
By using technical scheme of the present invention, the fpga logic version that will be used for hardware detection splits with the fpga logic version that is used for the message forwarding, the preferential fpga logic version that is used for hardware detection that loads, after the function executing of its hardware detection finishes, just be used for the loading of the fpga logic version of message forwarding, thereby, the fpga logic version that can be used in the message forwarding is after being loaded into fpga chip, obtain the more space resource, be implemented under the certain prerequisite of the space resources amount of fpga chip, make communication equipment can support the purpose of more business demand, improve the forwarding performance of communication equipment and the space resources utilance of fpga chip.
Description of drawings
Fig. 1 is the know-why schematic diagram of FPGA technology in the prior art;
Fig. 2 is the schematic flow sheet of the loading method of a kind of fpga logic version proposed by the invention;
Fig. 3 is the schematic diagram of the loading flow process of the fpga logic version in the communication equipment of prior art;
Fig. 4 is for loading for the first time the schematic flow sheet of fpga logic version in the technical scheme of embodiment of the invention proposition;
Fig. 5 is for loading for the second time the schematic flow sheet of fpga logic version in the technical scheme of embodiment of the invention proposition;
Fig. 6 is the structural representation of a kind of communication equipment proposed by the invention.
Embodiment
As stated in the Background Art, in the loading strategy of the fpga logic version of the fpga chip in the existing communication equipment, need to be loaded in the fpga chip whole fpga logic versions is disposable, but in fact, in the fpga logic version, except comprising the necessary pairing content of function such as forwarding and business, also having comprised a part must exist in logic, but only need to carry out the pairing content of function once, such function comprises the fpga chip self check, DDR (Double Data Rate, Double Data Rate) RAM (Random Access Memory, random asccess memory) self check, DDR Training (training) etc., after this part function is carried out once when system start-up, just or else can carry out, be seized of a part of space resources but its pairing content is fixing in fpga chip, this has caused the waste of the space resources of limited fpga chip undoubtedly.
For convenience of description, below, this part above-mentioned function is called the logic testing function.The content of the pairing fpga logic version of logic testing function in actual applications, can take the space resources of fpga chip about 15～20%.Fall taking of this segment space resource if can save, and this part space resources is offered the necessary pairing contents of function such as forwarding and business, will improve the space resources utilance of fpga chip greatly.
Based on such thinking, the present invention improves the utilance of space resource in the fpga chip effectively by using the repeatedly loading technique of fpga logic version.
As shown in Figure 2, the schematic flow sheet of the loading method of a kind of fpga logic version that proposes for the present invention, this method is applied to comprise in the communication equipment of fpga chip, specifically may further comprise the steps:
Step S201, communication equipment are loaded into default FPGA test logic version in the fpga chip, and by FPGA test logic version communication equipment self are carried out hardware detection.
Step S202, communication equipment are preserved the object information of hardware detection.
Step S203, communication equipment are loaded into default FPGA forwarding logic version in the fpga chip, dispose this fpga chip according to the object information of the hardware detection of preserving, and by FPGA forwarding logic version the received message of communication equipment are transmitted.
In the process that this step is carried out, the FPGA forwarding logic version that is loaded in the fpga chip has been finished being loaded into the covering of the FPGA test logic version in the fpga chip among the step S201.
In above-mentioned processing procedure, in advance existing complete fpga logic version is divided into two types, i.e. FPGA test logic version and FPGA forwarding logic version, wherein:
(1) FPGA test logic version
It is the fpga logic version that the pairing content of aforesaid logic testing function is formed, in the application of reality, the pairing properties collection of all types of logic testing functions can be generated a fpga logic version together, as FPGA test logic version, also can be respectively the logic testing function of one or more types be generated corresponding fpga logic version, promptly generated a plurality of FPGA test logic versions.
In actual applications, FPGA test logic version specifically is that one or a plurality of fpga logic version can be adjusted according to actual needs, and such variation does not influence protection scope of the present invention.
Consider that the performed function of FPGA test logic version all is based on the measuring ability of the hardware components of communication equipment and fpga chip, so above-mentioned FPGA test logic version specifically can detect the strategy generation according to the hardware configuration information and the relevant hardware of communication equipment.
(2) FPGA forwarding logic version
Being the fpga logic version that the pairing content of aforesaid message forwarding capability is formed, is the required fpga logic version of Core Feature of fpga chip, is specially the fpga logic version that business demand generated according to this communication equipment.
Further, because FPGA test logic version may be a fpga logic version, also may be a plurality of fpga logic versions, therefore, also can there be corresponding difference in corresponding processing procedure, wherein, if FPGA test logic version is a fpga logic version, so, can handle accordingly according to above-mentioned step S201 and step S202, and if FPGA test logic version is made up of a plurality of fpga logic versions, so, in concrete enforcement scene, the concrete processing procedure of above-mentioned step S201 and step S202 can be divided into following two kinds of situations according to the difference of the loading strategy of FPGA test logic version:
Situation one, a plurality of FPGA test logic versions are loaded several times
In this kind situation, corresponding processing procedure is as follows:
At first, communication equipment is loaded into a FPGA test logic version in a plurality of FPGA test logic versions in the fpga chip, and the FPGA test logic version by current loading carries out relevant hardware to communication equipment and detects.
After hardware detection was finished, communication equipment was preserved the object information of this time hardware detection.
Then, communication equipment continues other FPGA test logic versions in a plurality of FPGA test logic versions are loaded in the fpga chip, carries out other hardware detection.
Above-mentioned process is equivalent to all carry out once at each the FPGA test logic version in a plurality of FPGA test logic versions the operation of above-mentioned step S201 and step S202, promptly according to each FPGA test logic version communication equipment is carried out corresponding hardware detection respectively.
In concrete implementation procedure, can adjust according to actual needs for the order that loads each FPGA test logic version, such variation does not influence protection scope of the present invention.
Communication equipment respectively according to a plurality of FPGA test logic versions in all FPGA test logic versions all finished after relevant hardware detects, this communication equipment is carried out aforesaid step S203, default FPGA forwarding logic version is loaded in the fpga chip, object information according to the hardware detection of preserving disposes relevant hardware in this fpga chip, by FPGA forwarding logic version the received message of communication equipment is transmitted.
Situation two, with disposable loading of a plurality of FPGA test logic versions
In this kind situation, corresponding processing procedure is as follows:
Communication equipment is disposable being loaded in the fpga chip of whole FPGA test logic versions in a plurality of FPGA test logic versions, and each the FPGA test logic version by current loading carries out relevant hardware to communication equipment and detects respectively.
Communication equipment is preserved the object information of hardware detection.
Above-mentioned process is equivalent to simultaneously each the FPGA test logic version in a plurality of FPGA test logic versions be carried out above-mentioned step S201 and the operation of step S202, promptly carries out the corresponding hardware detection of a plurality of FPGA test logic versions synchronously.
And after all FPGA test logic versions have all been finished the relevant hardware detection, this communication equipment is carried out aforesaid step S203, communication equipment is loaded into default FPGA forwarding logic version in the fpga chip, object information according to the hardware detection of preserving disposes relevant hardware in this fpga chip, by FPGA forwarding logic version the received message of communication equipment is transmitted.
In concrete enforcement scene, further comprise in the processing procedure of aforesaid step S203 the layoutprocedure of the object information of the hardware detection of having preserved, specify as follows:
Communication equipment is loaded into default FPGA forwarding logic version in the fpga chip.
Communication equipment is the object information of the hardware detection of preserving, and writes in the fpga chip in the relevant register sequence.
The internal logic of fpga chip further disposes corresponding RAM controller in this fpga chip according to the object information in the register series.
Communication equipment enables FPGA forwarding logic version, and the received message of communication equipment is transmitted.
Compared with prior art, the present invention has the following advantages:
By using technical scheme of the present invention, the fpga logic version that will be used for hardware detection splits with the fpga logic version that is used for the message forwarding, the preferential fpga logic version that is used for hardware detection that loads, after the function executing of its hardware detection finishes, just be used for the loading of the fpga logic version of message forwarding, thereby, the fpga logic version that can be used in the message forwarding is after being loaded into fpga chip, obtain the more space resource, be implemented under the certain prerequisite of the space resources amount of fpga chip, make communication equipment can support the purpose of more business demand, improve the forwarding performance of communication equipment and the space resources utilance of fpga chip.
In order further to set forth technological thought of the present invention, existing in conjunction with concrete application scenarios, technical scheme of the present invention is described.
Clearer in order to describe, the loading flow process of the fpga logic version that in the follow-up explanation loading flow process and the embodiment of the invention of the fpga logic version in the existing communication equipment is proposed compares explanation, for convenience of description, in follow-up explanation, the situation complete fpga logic version is divided into a FPGA test logic version and a FPGA forwarding logic version that the embodiment of the invention is concrete is the explanation that example is carried out handling process, can be for a plurality of FPGA test logic versions with reference to aforesaid explanation, at this repeated description no longer.
At first, when a communication equipment carries out Default Value, two fpga logic versions of software development:
One is FPGA test logic version, the completion logic test function.
Another is a FPGA forwarding logic version, finishes the regular traffic forwarding capability, compares with complete fpga logic version, and this FPGA forwarding logic version has been rejected the logic testing function in the complete fpga logic version.
Two above-mentioned fpga logic versions can be stored in the interior storage resources space of this communication equipment in advance; physical memory as this communication equipment; the storage resources space of inner other hardware of buffer memory or this communication equipment (as the local internal memory of CPU etc.) in, the variation of concrete memory location can't influence protection scope of the present invention.
When starting, communication equipment loads above-mentioned fpga logic version at twice in system:
Load for the first time FPGA test logic version, completion logic test function;
Load for the second time FPGA forwarding logic version, cover FPGA test logic version, do normal professional the forwarding.
Now the loading flow process of the fpga logic version that the loading flow process and the embodiment of the invention of the fpga logic version in the existing communication equipment proposed compares, the realization principle of describing the secondary loading technique in detail with and advanced.
As shown in Figure 3, be the schematic diagram of the loading flow process of the fpga logic version in the communication equipment of prior art, the technical scheme of wherein not using the embodiment of the invention and being proposed, concrete processing procedure is as follows:
CPU in step S301, the communication equipment is loaded into fpga chip with the fpga logic version.
Test module in step S302, the fpga chip is done fpga chip self check and DDR RAM self check according to the fpga logic version, and does the DDR training.
Test module in step S303, the fpga chip is write the result of fpga chip self check and DDR RAM self check in the register series of appointment, and the training result of DDR training is configured to the RAM controller.
CPU in step S304, the communication equipment reads the register series of appointment, gets access to the result of fpga chip self check and DDR RAM self check.
CPU in step S305, the communication equipment enables to transmit relevant logic with business in the fpga logic version, and the forwarding module in the fpga chip is started working.
This shows, for existing implementation, on fpga chip, only to step S303, use the test module that carries out self check and DDR training process at step S302, behind step S305, then can not use, but this test module is still taking the space resources in the fpga chip, estimate according to experience, there is 20% the tested module of space resources to take in the fpga chip approximately, and this part space resources is beginning to carry out not recurring after business is transmitted any effect, therefore, this space resources to fpga chip causes waste to a certain degree.
For fear of the waste of above-mentioned space resources, the embodiment of the invention has proposed the loading method of the fpga logic version in a kind of concrete application scenarios, at twice the fpga logic version is loaded, and concrete processing procedure is as follows:
At first, as shown in Figure 4, for loading for the first time the schematic flow sheet of fpga logic version in the technical scheme of embodiment of the invention proposition, in this loading procedure, communication equipment has loaded FPGA test logic version in fpga chip.
The CPU of step S401, communication equipment is loaded into fpga chip with FPGA test logic version.
Step S402, FPGA test logic version are done self check and DDR training to fpga chip and DDR RAM.
Step S403, FPGA test logic version write fpga chip self-detection result, DDR RAM self-detection result and DDR training result the register series of appointment.
The CPU of step S404, communication equipment reads register series, and the object information that will be stored in wherein stores the local internal memory of CPU into.
So far, test phase in the fpga chip is all finished, and corresponding test result information also has been extracted the local internal memory that stores CPU into, FPGA test logic version will be die in subsequent treatment, therefore, CPU covers FPGA test logic version loading FPGA forwarding logic version in follow-up process in fpga chip, space resources in the fpga chip is used for FPGA forwarding logic version fully, and the implementation space resources effective is utilized.
As shown in Figure 5, for loading for the second time the schematic flow sheet of fpga logic version in the technical scheme of embodiment of the invention proposition, in this loading procedure, communication equipment has loaded FPGA forwarding logic version in fpga chip.
The CPU of step S405, communication equipment is loaded into fpga chip with FPGA forwarding logic version.
The CPU of step S406, communication equipment reads its local internal memory, and the DDR training result of wherein storing is written to register series.
Internal logic on step S407, the fpga chip reads the DDR training result in the register series, and disposes the RAM controller in view of the above.
The CPU of step S408, communication equipment enables to be carried in the FPGA forwarding logic version on the fpga chip, makes FPGA forwarding logic version begin to carry out normal professional the forwarding.
Can see that the difference between the FPGA forwarding logic version that loads for the second time and the existing complete fpga logic version is to have rejected the logic testing function, therefore, the more space resource can be used for professional the forwarding in the fpga chip, infer according to the standard that aforesaid logic testing function takies 20% space resources, be equivalent in the professional repeating process of reality, save the space resources of fpga chip nearly 20%, thereby, under the certain prerequisite of the space resources amount of fpga chip, make communication equipment can support more business demand.
Compared with prior art, the present invention has the following advantages:
By using technical scheme of the present invention, the fpga logic version that will be used for hardware detection splits with the fpga logic version that is used for the message forwarding, the preferential fpga logic version that is used for hardware detection that loads, after the function executing of its hardware detection finishes, just be used for the loading of the fpga logic version of message forwarding, thereby, the fpga logic version that can be used in the message forwarding is after being loaded into fpga chip, obtain the more space resource, be implemented under the certain prerequisite of the space resources amount of fpga chip, make communication equipment can support the purpose of more business demand, improve the forwarding performance of communication equipment and the space resources utilance of fpga chip.
In order to realize technical scheme of the present invention, based on aforesaid explanation, the invention allows for a kind of communication equipment, comprise fpga chip in this communication equipment, its structural representation as shown in Figure 6, this communication equipment specifically comprises:
In the application of reality; above-mentioned memory module 61 is specifically as follows the storage resources space in this communication equipment; physical memory as this communication equipment; the storage resources space of inner other hardware of buffer memory or this communication equipment (as the local internal memory of CPU etc.) in, the variation of concrete form can't influence protection scope of the present invention.
Load-on module 62, the FPGA test logic version that is used for memory module 61 is stored is loaded into fpga chip, after FPGA test logic version is finished hardware detection, the FPGA forwarding logic version that memory module 61 is stored is loaded in the fpga chip, in concrete application scenarios, load-on module 62 is equivalent to the CPU of communication equipment in the described handling process of aforesaid Fig. 4.
In concrete application scenarios, above-mentioned processing module 63 is equivalent to the local logic of the fpga chip in the aforesaid handling process shown in Figure 4, realizes corresponding processing capacity by the logical versions that loads in this fpga chip,
In concrete application scenarios, FPGA test logic version that memory module 61 is stored and FPGA forwarding logic version are similarly existing complete fpga logic version are split the formed fpga logic version in back, corresponding specific explanations is with reference to the explanation of preamble, at this repeated description no longer.
Same, because FPGA test logic version may be a fpga logic version, also may be a plurality of fpga logic versions, therefore, also can there be corresponding difference in corresponding processing procedure, if FPGA test logic version is made up of a plurality of fpga logic versions, so, in concrete enforcement scene, according to the difference of the loading strategy of FPGA test logic version, the concrete processing procedure of load-on module 62 can be divided into following two kinds of situations:
A FPGA test logic version in a plurality of FPGA test logic versions that situation one, load-on module 62 are stored memory module 61 is loaded in the fpga chip, after FPGA test logic version is finished hardware detection, continuation is loaded into other FPGA test logic versions in a plurality of FPGA test logic versions in the fpga chip, after all FPGA test logic versions had all been finished the relevant hardware detection in a plurality of FPGA test logic versions, the FPGA forwarding logic version that memory module 61 is stored was loaded in the fpga chip.
Whole FPGA test logic versions in a plurality of FPGA test logic versions that situation two, load-on module 62 are stored memory module 61 are loaded in the fpga chip, after all FPGA test logic versions were finished hardware detection, the FPGA forwarding logic version that memory module 61 is stored was loaded in the fpga chip.
In concrete application scenarios, after the FPGA forwarding logic version that load-on module 62 is stored memory module 61 is loaded in the fpga chip, the object information that processing module 63 specifically is used for hardware detection that memory module 61 is preserved writes the corresponding register series of fpga chip, so that this fpga chip disposes corresponding RAM controller in this fpga chip according to the object information in the register series, further, processing module 63 also is used for after the layoutprocedure of fpga chip is finished, enable FPGA forwarding logic version, the received message of this communication equipment is transmitted.。
Compared with prior art, the present invention has the following advantages:
By using technical scheme of the present invention, the fpga logic version that will be used for hardware detection splits with the fpga logic version that is used for the message forwarding, the preferential fpga logic version that is used for hardware detection that loads, after the function executing of its hardware detection finishes, just be used for the loading of the fpga logic version of message forwarding, thereby, the fpga logic version that can be used in the message forwarding is after being loaded into fpga chip, obtain the more space resource, be implemented under the certain prerequisite of the space resources amount of fpga chip, make communication equipment can support the purpose of more business demand, improve the forwarding performance of communication equipment and the space resources utilance of fpga chip.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by hardware, also can realize by the mode that software adds necessary general hardware platform.Based on such understanding, technical scheme of the present invention can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) each implements the described method of scene to carry out the present invention.
It will be appreciated by those skilled in the art that accompanying drawing is a preferred schematic diagram of implementing scene, module in the accompanying drawing or flow process might not be that enforcement the present invention is necessary.
It will be appreciated by those skilled in the art that the module in the device of implementing in the scene can be distributed in the device of implementing scene according to implementing scene description, also can carry out respective change and be arranged in the one or more devices that are different from this enforcement scene.The module of above-mentioned enforcement scene can be merged into a module, also can further split into a plurality of submodules.
The invention described above sequence number is not represented the quality of implementing scene just to description.
More than disclosed only be several concrete enforcement scene of the present invention, still, the present invention is not limited thereto, any those skilled in the art can think variation all should fall into protection scope of the present invention.
Claims (10)
1. the loading method of an on-site programmable gate array FPGA logical versions is applied to comprise in the communication equipment of fpga chip, it is characterized in that described method may further comprise the steps at least:
Described communication equipment is loaded into default FPGA test logic version in the described fpga chip, and by described FPGA test logic version described communication equipment self is carried out hardware detection;
Described communication equipment is preserved the object information of described hardware detection;
Described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted.
2. the method for claim 1 is characterized in that,
Described default FPGA test logic version is specially the one or more fpga logic versions that are used for realizing the relevant hardware of described fpga chip and described communication equipment is carried out state-detection;
Described default FPGA forwarding logic version is specially the fpga logic version that is used for carrying out according to the business demand of described communication equipment corresponding message forwarding.
3. method as claimed in claim 2 is characterized in that, when described default FPGA test logic version was specially a plurality of fpga logic version, described method was specially:
Described communication equipment is loaded into a FPGA test logic version in described a plurality of FPGA test logic versions in the described fpga chip, and the FPGA test logic version by current loading carries out relevant hardware to described communication equipment and detects;
Described communication equipment is preserved the object information of described hardware detection;
Described communication equipment continues other FPGA test logic versions in described a plurality of FPGA test logic versions are loaded in the described fpga chip, carries out other hardware detection;
Until described communication equipment after all FPGA test logic versions have finished relevant hardware and detect in respectively according to described a plurality of FPGA test logic versions, described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted.
4. method as claimed in claim 2 is characterized in that, when described default FPGA test logic version was specially a plurality of fpga logic version, described method was specially:
Described communication equipment is loaded into the whole FPGA test logic versions in described a plurality of FPGA test logic versions in the described fpga chip, and each the FPGA test logic version by current loading carries out the relevant hardware detection to described communication equipment respectively;
Described communication equipment is preserved the object information of described hardware detection;
Described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted.
5. as any described method in the claim 1 to 4, it is characterized in that, described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip, object information according to the described hardware detection of preserving disposes described fpga chip, by described FPGA forwarding logic version the received message of described communication equipment is transmitted, is specifically comprised:
Described communication equipment is loaded into default FPGA forwarding logic version in the described fpga chip;
The object information of the described hardware detection that described communication equipment will be preserved is written in the corresponding register series of described fpga chip;
Described fpga chip disposes self corresponding RAM controller according to the object information in the described register series;
Described communication equipment enables described FPGA forwarding logic version, and the received message of described communication equipment is transmitted.
6. a communication equipment comprises fpga chip, it is characterized in that, described communication equipment comprises:
Memory module is used to store FPGA test logic version and FPGA forwarding logic version;
Load-on module, the FPGA test logic version that is used for described memory module is stored is loaded into described fpga chip, after described FPGA test logic version was finished hardware detection, the FPGA forwarding logic version that described memory module is stored was loaded in the described fpga chip;
Processing module, the FPGA test logic version that is used for being loaded into by described load-on module described fpga chip carries out hardware detection, the object information of described hardware detection is saved in the described memory module, and after the FPGA forwarding logic version that described load-on module is stored described memory module is loaded in the described fpga chip, the described hardware detection result who stores according to described memory module disposes described fpga chip, by described FPGA forwarding logic version the message that described communication equipment receives is transmitted.
7. communication equipment as claimed in claim 6 is characterized in that,
The FPGA test logic version that described memory module is stored is specially the one or more fpga logic versions that are used for realizing the relevant hardware of described fpga chip and described communication equipment is carried out state-detection;
The FPGA forwarding logic version that described memory module is stored is specially the fpga logic version that is used for carrying out according to the business demand of described communication equipment corresponding message forwarding.
8. communication equipment as claimed in claim 7 is characterized in that, when the FPGA test logic version of storing when described memory module was specially a plurality of fpga logic version, described load-on module specifically was used for:
A FPGA test logic version in a plurality of FPGA test logic versions that described memory module is stored is loaded in the described fpga chip, after described FPGA test logic version is finished hardware detection, continue other FPGA test logic versions in described a plurality of FPGA test logic versions are loaded in the described fpga chip, after all FPGA test logic versions had all been finished the relevant hardware detection in described a plurality of FPGA test logic versions, the FPGA forwarding logic version that described memory module is stored was loaded in the described fpga chip.
9. communication equipment as claimed in claim 7 is characterized in that, when the FPGA test logic version of storing when described memory module was specially a plurality of fpga logic version, described load-on module specifically was used for:
Whole FPGA test logic versions in a plurality of FPGA test logic versions that described memory module is stored are loaded in the described fpga chip, after the FPGA test logic version that has was finished hardware detection more, the FPGA forwarding logic version that described memory module is stored was loaded in the described fpga chip.
10. as any described communication equipment in the claim 6 to 9, it is characterized in that, after the FPGA forwarding logic version that described load-on module is stored described memory module is loaded in the described fpga chip,
Described processing module, the object information that specifically is used for described hardware detection that described memory module is preserved writes the corresponding register series of described fpga chip, so that described fpga chip disposes corresponding RAM controller in the described fpga chip according to the object information in the described register series, and after the layoutprocedure of described fpga chip is finished, enable described FPGA forwarding logic version, the received message of described communication equipment is transmitted.
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| CN113157635B (en) * | 2019-09-25 | 2024-01-05 | 支付宝(杭州)信息技术有限公司 | Method and device for realizing contract call on FPGA |
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