CN102154670A - Method for electroplating copper - Google Patents
Method for electroplating copper Download PDFInfo
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- CN102154670A CN102154670A CN2011100645559A CN201110064555A CN102154670A CN 102154670 A CN102154670 A CN 102154670A CN 2011100645559 A CN2011100645559 A CN 2011100645559A CN 201110064555 A CN201110064555 A CN 201110064555A CN 102154670 A CN102154670 A CN 102154670A
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Abstract
The invention discloses a method for electroplating copper. In the method, stage-type electroplating technique is adopted for treatment, namely, the electroplating technique for treatment is carried out in different stages under the conditions of different current densities, rotating speeds of a silicon wafer, flow rates of electroplate liquid and technical positions of the silicon wafer, so that high filling speed can be guaranteed, the step height with a large size and depth figure is effectively reduced compared with an area without the figure, the thickness of a copper film needed by the electroplating technique can be indirectly reduced on the premise of guaranteeing a chemically mechanical polishing process window, the electroplating technique time and the chemically mechanical polishing process time are further reduced, and the chemical materials are saved.
Description
Technical field
The present invention relates to the semiconductor process techniques field, relate in particular to a kind of Electrocoppering method.
Background technology
Along with individual devices becomes more and more littler, the travelling speed of unicircuit is more and more faster, the conventional aluminum processing procedure can't meet the demands, therefore, copper interconnection technology develops into the semiconductor integrated circuit interconnection technique of main flow, the copper electroplating technology then surpasses traditional film-forming process such as PVD, CVD, becomes the main technique of preparation copper film in the copper interconnection technology.
Simultaneously, along with the notion intensification of Internet of Things, radio frequency chip becomes the focus in market gradually.For the chip of traditional cmos process preparation, its high frequency performance is comparatively general, needs to use the mode that adds coil inductance to improve the high frequency performance of device.And the copper-connection inductance can be realized the radio-frequency devices of high Q value, high stability, therefore is one of effective way that obtains the high-performance radio-frequency chip.
Damascus electroplating technology of prior art is mainly paid close attention to the nothing cavity filling effect of small size figure, the general staged electroplating technology that on identical silicon chip technology position, silicon chip rotating speed and electroplate liquid flow velocity, adopts current density progressively to raise, described staged electroplating technology mainly comprises following several stages:
Starting stage, the galvanized starting stage is adopted low current density, and to obtain surface electroplating effect uniformly, repairing copper seed layer is that high current density is prepared;
Subordinate phase, galvanized subordinate phase adopts higher current density, to obtain fast electroplating effect from bottom to top, filling perforation and to guarantee not have the cavity seamless fast;
Final stage, galvanized final stage adopt high current density to add thick copper layer rapidly, provide process window to CMP (Chemical Mechanical Polishing) process.
But existing staged electroplating technology technology lacks control for the figure of large size (5～100 microns), because the electro-coppering sedimentation rate of large size figure is slower, therefore the bench height with respect to no graphics field increases.And for CMP (Chemical Mechanical Polishing) process, the large size figure with respect to the bench height of no graphics field determined should the zone the throwing amount of crossing, bench height is big more, it is also big more to cross the throwing amount, therefore must increase copper layer thickness controlled the throwing amount, thereby meet design requirement (copper layer thickness that keeps in the figure is up to standard), this has just increased the burden of electroplating technology and CMP (Chemical Mechanical Polishing) process.
Because the copper-connection inductance mainly is the figure of large size (1～50 micron), the big degree of depth (1～5 micron), need the copper film of several micron thickness, therefore will increase the burden of electroplating technology and CMP (Chemical Mechanical Polishing) process significantly.
Therefore, be necessary the existing plating process for copper is improved.
Summary of the invention
The object of the present invention is to provide a kind of Electrocoppering method, to reduce large size, big degree of depth integrated circuit pattern zone bench height with respect to the copper coating of no graphics field.
For addressing the above problem, the present invention proposes a kind of Electrocoppering method, be used for the integrated circuit pattern of large size, the big degree of depth is formed plated copper film, this method adopts interim electroplating technology to handle, and carries out electroplating technology stage by stage and handle under different current densities, silicon chip speed of rotation, electroplate liquid flow velocity and silicon chip technology locality condition.
Optionally, the processing condition the treatment stage of during described interim electroplating technology is handled each are:
Silicon chip technology position: 2～10 millimeters, current density: 0.2～8 ampere/square decimeter, the silicon chip speed of rotation: 5～50 rev/mins, the electroplate liquid flow velocity: 4～20 liters/minute, the time: 3～500 seconds.
Optionally, described interim electroplating technology is handled and is divided the treatment stage of comprising two, is respectively starting stage and terminal stage.
Optionally, the silicon chip position of described starting stage is higher than the silicon chip position of described terminal stage, the silicon chip speed of rotation of described starting stage is lower than the silicon chip speed of rotation of described terminal stage, the electroplate liquid flow velocity of described starting stage is lower than the electroplate liquid flow velocity of described terminal stage, and the current density of described starting stage is lower than the current density of described terminal stage.
Optionally, the processing condition of described starting stage are specially:
Time: 10～50 seconds, current density: 0.8～3 ampere/square decimeter, the silicon chip speed of rotation: 5～30 rev/mins, the electroplate liquid flow velocity: 4～10 liters/minute, silicon chip technology position: 5～10 millimeters.
Optionally, the processing condition of described terminal stage are specially:
Time: 30～500 seconds, current density: 3～8 amperes/square decimeter, the silicon chip speed of rotation: 30～50 rev/mins, the electroplate liquid flow velocity: 10～20 liters/minute, silicon chip technology position: 2～5 millimeters.
Optionally, described interim electroplating technology is handled and is also comprised a transitory stage, described transitory stage is between described starting stage and described terminal stage, the current density of described transitory stage is lower than the current density of described starting stage, and the silicon chip position of described transitory stage, silicon chip speed of rotation and electroplate liquid flow velocity are identical with silicon chip position, silicon chip speed of rotation and the electroplate liquid flow velocity of described terminal stage.
Optionally, the processing condition of described transitory stage are specially:
Time: 3～10 seconds, current density: 0.2～0.8 ampere/square decimeter, the silicon chip speed of rotation: 30～50 rev/mins, the electroplate liquid flow velocity: 10～20 liters/minute, silicon chip technology position: 2～5 millimeters.
Compared with prior art, Electrocoppering method provided by the invention is handled by adopting interim electroplating technology, in different current densities, the silicon chip speed of rotation, carrying out electroplating technology under electroplate liquid flow velocity and the silicon chip technology locality condition stage by stage handles, thereby when guaranteeing high fill rate, reduced large size effectively, big degree of depth figure is with respect to the bench height of no graphics field, on the prerequisite that guarantees the CMP (Chemical Mechanical Polishing) process window, reduced the required copper film thickness of electroplating technology indirectly, and then shortened electroplating technology time and CMP (Chemical Mechanical Polishing) process time, and the use of saving chemical consumptive material.
Description of drawings
The synoptic diagram of the processing parameter the treatment stage of each of the Electrocoppering method that Fig. 1 provides for first embodiment of the invention;
The synoptic diagram of the processing parameter the treatment stage of each of the Electrocoppering method that Fig. 2 provides for second embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the Electrocoppering method that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only be used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of Electrocoppering method is provided, this method is handled by adopting interim electroplating technology, in different current densities, the silicon chip speed of rotation, carrying out electroplating technology under electroplate liquid flow velocity and the silicon chip technology locality condition stage by stage handles, thereby when guaranteeing high fill rate, reduced large size effectively, big degree of depth figure is with respect to the bench height of no graphics field, on the prerequisite that guarantees the CMP (Chemical Mechanical Polishing) process window, reduced the required copper film thickness of electroplating technology indirectly, and then shortened electroplating technology time and CMP (Chemical Mechanical Polishing) process time, and the use of saving chemical consumptive material; And this technological process does not influence the quality of copper coating, and every processing performance of copper interconnecting line touches the mark.
Embodiment 1
Please refer to Fig. 1, the synoptic diagram of the processing parameter the treatment stage of each of the Electrocoppering method that Fig. 1 provides for first embodiment of the invention, in conjunction with Fig. 1, the Electrocoppering method that the embodiment of the invention provides, be used for the integrated circuit pattern of large size, the big degree of depth is formed plated copper film, this method adopts interim electroplating technology to handle, and carries out electroplating technology stage by stage and handle under different current densities, silicon chip speed of rotation, electroplate liquid flow velocity and silicon chip technology locality condition.Thereby when guaranteeing high fill rate, reduced large size, big degree of depth figure bench height effectively with respect to no graphics field, on the prerequisite that guarantees the CMP (Chemical Mechanical Polishing) process window, reduced the required copper film thickness of electroplating technology indirectly, and then shortened electroplating technology time and CMP (Chemical Mechanical Polishing) process time, and the use of saving chemical consumptive material.
Further, the processing condition the treatment stage of during described interim electroplating technology is handled each are:
Silicon chip technology position: 2～10 millimeters, current density: 0.2～8 ampere/square decimeter, the silicon chip speed of rotation: 5～50 rev/mins, the electroplate liquid flow velocity: 4～20 liters/minute, the time: 3～500 seconds.
Further, described interim electroplating technology is handled and is divided the treatment stage of comprising two, is respectively starting stage and terminal stage.
Further, the silicon chip position of described starting stage is higher than the silicon chip position of described terminal stage, the silicon chip speed of rotation of described starting stage is lower than the silicon chip speed of rotation of described terminal stage, the electroplate liquid flow velocity of described starting stage is lower than the electroplate liquid flow velocity of described terminal stage, and the current density of described starting stage is lower than the current density of described terminal stage.
Below above-mentioned two stages are specifically described respectively:
The processing condition of described starting stage are: high silicon chip technology position, medium current density, low silicon chip speed of rotation, low electroplate liquid flow velocity, shown in each parameter in the stage among Fig. 1 one; Because for the small size figure, large size, the step covering power of the PVD technology of the integrated circuit pattern of the big degree of depth itself is just very good, thicker blocking layer and copper seed layer have good continuity, thereby compare with existing Damascus technique, the Electrocoppering method that the embodiment of the invention provides need not adopt the electroplating technology pre-treatment of low current density, its starting stage directly uses higher current density that copper seed layer is thickeied fast, simultaneously, low silicon chip speed of rotation, low electroplate liquid flow velocity and high silicon chip technology position make silicon chip surface be in the low mass transfer state, help the diffusion on the copper surface of electroplate liquid in different integrated circuit patterns, thereby under higher current density, obtain high-quality copper coating.
Wherein, the processing condition of described starting stage preferably are: the time: 10～50 seconds, and current density: 0.8～3 ampere/square decimeter, the silicon chip speed of rotation: 5～30 rev/mins, the electroplate liquid flow velocity: 4～10 liters/minute, silicon chip technology position: 5～10 millimeters.
The processing condition of described terminal stage are: low silicon chip technology position, high current density, high silicon chip speed of rotation, high electroplate liquid flow velocity, shown in each parameter in the stage among Fig. 1 three; Described terminal stage adopts high current density, under the high mass transfer pattern of high silicon chip speed of rotation, high electroplate liquid flow velocity and low silicon chip technology position, the diffusibility of the cupric ion in the electroplate liquid strengthens, this helps the longitudinal diffusion of cupric ion to integrated circuit pattern structure depths, provide enough replenishing to the cupric ion loss under the high deposition rate, thereby can keep the interior high deposition rate of integrated circuit pattern of large size, the big degree of depth, help the redistribution of additive in the different graphic structure simultaneously.In terminal stage, electroplating technology fills up the figure of large size, the big degree of depth, and provides enough copper thickness to CMP (Chemical Mechanical Polishing) process.
Wherein, the processing condition of described terminal stage preferably are: the time: 30～500 seconds, and current density: 3～8 amperes/square decimeter, the silicon chip speed of rotation: 30～50 rev/mins, the electroplate liquid flow velocity: 10～20 liters/minute, silicon chip technology position: 2～5 millimeters.
Need to prove that the size of each parameter among Fig. 1 is relative value, and wherein each parameter has independently scale.
Embodiment 2
Please refer to Fig. 2, the synoptic diagram of the processing parameter the treatment stage of each of the Electrocoppering method that Fig. 2 provides for second embodiment of the invention, in conjunction with Fig. 2, different with above-mentioned first embodiment is, the interim electroplating technology that second embodiment of the invention provides is handled and is also comprised a transitory stage, described transitory stage is between described starting stage and described terminal stage, the current density of described transitory stage is lower than the current density of described starting stage, the silicon chip position of described transitory stage, the silicon chip position of silicon chip speed of rotation and electroplate liquid flow velocity and described terminal stage, silicon chip speed of rotation and electroplate liquid flow velocity are identical.
Below above-mentioned three phases is specifically described respectively:
The processing condition of described starting stage are: high silicon chip technology position, medium current density, low silicon chip speed of rotation, low electroplate liquid flow velocity, shown in each parameter in the stage among Fig. 2 one; Because for the small size figure, large size, the step covering power of the PVD technology of the integrated circuit pattern of the big degree of depth itself is just very good, thicker blocking layer and copper seed layer have good continuity, thereby compare with existing Damascus technique, the Electrocoppering method that the embodiment of the invention provides need not adopt the electroplating technology pre-treatment of low current density, its starting stage directly uses higher current density that copper seed layer is thickeied fast, simultaneously, low silicon chip speed of rotation, low electroplate liquid flow velocity and high silicon chip technology position make silicon chip surface be in the low mass transfer state, help the diffusion on the copper surface of electroplate liquid in different integrated circuit patterns, thereby under higher current density, obtain high-quality copper coating.
Wherein, the processing condition of described starting stage preferably are: the time: 10～50 seconds, and current density: 0.8～3 ampere/square decimeter, the silicon chip speed of rotation: 5～30 rev/mins, the electroplate liquid flow velocity: 4～10 liters/minute, silicon chip technology position: 5～10 millimeters.
The processing condition of described transitory stage are: low silicon chip technology position, low current density, high silicon chip speed of rotation, high electroplate liquid flow velocity, shown in each parameter in the stage among Fig. 2 two; Described transitory stage is the transitory stage of electroplating technology, by increasing silicon chip speed of rotation and electroplate liquid flow velocity, and reduction silicon chip technology position, make silicon chip surface enter the state that transports of high mass transfer, owing to the integrated circuit pattern for large size, the big degree of depth, various additives can freely enter in the different graphic structure and obtain balance, under high mass transfer pattern, the diffusibility of additive strengthens, and helps the competition each other of accelerator and leveling agent, thereby obtains better leveling effect; Simultaneously, this stage is used low current density, can protect the copper surface not corroded by electroplate liquid on the one hand, helps the redistribution of additive in the different graphic structure on the other hand.
Wherein, the processing condition of described transitory stage preferably are: the time: 3～10 seconds, and current density: 0.2～0.8 ampere/square decimeter, silicon chip speed of rotation: 30～50 rev/mins, the electroplate liquid flow velocity: 10～20 liters/minute, silicon chip technology position: 2～5 millimeters.
The processing condition of described terminal stage are: low silicon chip technology position, high current density, high silicon chip speed of rotation, high electroplate liquid flow velocity, shown in each parameter in the stage among Fig. 2 three; Described terminal stage adopts high current density, under the high mass transfer pattern of high silicon chip speed of rotation, high electroplate liquid flow velocity and low silicon chip technology position, the diffusibility of the cupric ion in the electroplate liquid strengthens, this helps the longitudinal diffusion of cupric ion to integrated circuit pattern structure depths, provide enough replenishing to the cupric ion loss under the high deposition rate, thereby can keep the interior high deposition rate of integrated circuit pattern of large size, the big degree of depth.In terminal stage, electroplating technology fills up the figure of large size, the big degree of depth, and provides enough copper thickness to CMP (Chemical Mechanical Polishing) process.
Wherein, the processing condition of described terminal stage preferably are: the time: 30～500 seconds, and current density: 3～8 amperes/square decimeter, the silicon chip speed of rotation: 30～50 rev/mins, the electroplate liquid flow velocity: 10～20 liters/minute, silicon chip technology position: 2～5 millimeters.
Need to prove that the size of each parameter among Fig. 2 is relative value, and wherein each parameter has independently scale.
Need to prove, the low current density of the medium current density of starting stage, transitory stage, the high current density of terminal stage in the embodiment of the invention, be intended to show the relative size relation of each stage current density in a given range, promptly in given scope, the current density of starting stage is greater than the current density of transitory stage, but less than the current density of terminal stage; Other processing parameter situation is done similar explanation.
In sum, the invention provides a kind of Electrocoppering method, this method is handled by adopting interim electroplating technology, in different current densities, the silicon chip speed of rotation, carrying out electroplating technology under electroplate liquid flow velocity and the silicon chip technology locality condition stage by stage handles, thereby when guaranteeing high fill rate, reduced large size effectively, big degree of depth figure is with respect to the bench height of no graphics field, on the prerequisite that guarantees the CMP (Chemical Mechanical Polishing) process window, reduced the required copper film thickness of electroplating technology indirectly, and then shortened electroplating technology time and CMP (Chemical Mechanical Polishing) process time, and the use of saving chemical consumptive material.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. Electrocoppering method, be used for the integrated circuit pattern of large size, the big degree of depth is formed plated copper film, it is characterized in that, this method adopts interim electroplating technology to handle, and carries out electroplating technology stage by stage and handle under different current densities, silicon chip speed of rotation, electroplate liquid flow velocity and silicon chip technology locality condition.
2. Electrocoppering method as claimed in claim 1 is characterized in that, the processing condition the treatment stage of during described interim electroplating technology is handled each are:
Silicon chip technology position: 2～10 millimeters, current density: 0.2～8 ampere/square decimeter, the silicon chip speed of rotation: 5～50 rev/mins, the electroplate liquid flow velocity: 4～20 liters/minute, the time: 3～500 seconds.
3. Electrocoppering method as claimed in claim 2 is characterized in that, described interim electroplating technology is handled and divided the treatment stage of comprising two, is respectively starting stage and terminal stage.
4. Electrocoppering method as claimed in claim 3, it is characterized in that, the silicon chip position of described starting stage is higher than the silicon chip position of described terminal stage, the silicon chip speed of rotation of described starting stage is lower than the silicon chip speed of rotation of described terminal stage, the electroplate liquid flow velocity of described starting stage is lower than the electroplate liquid flow velocity of described terminal stage, and the current density of described starting stage is lower than the current density of described terminal stage.
5. Electrocoppering method as claimed in claim 4 is characterized in that, the processing condition of described starting stage are specially:
Time: 10～50 seconds, current density: 0.8～3 ampere/square decimeter, the silicon chip speed of rotation: 5～30 rev/mins, the electroplate liquid flow velocity: 4～10 liters/minute, silicon chip technology position: 5～10 millimeters.
6. Electrocoppering method as claimed in claim 4 is characterized in that, the processing condition of described terminal stage are specially:
Time: 30～500 seconds, current density: 3～8 amperes/square decimeter, the silicon chip speed of rotation: 30～50 rev/mins, the electroplate liquid flow velocity: 10～20 liters/minute, silicon chip technology position: 2～5 millimeters.
7. as claim 4 or 6 described Electrocoppering methods, it is characterized in that, described interim electroplating technology is handled and is also comprised a transitory stage, described transitory stage is between described starting stage and described terminal stage, the current density of described transitory stage is lower than the current density of described starting stage, and the silicon chip position of described transitory stage, silicon chip speed of rotation and electroplate liquid flow velocity are identical with silicon chip position, silicon chip speed of rotation and the electroplate liquid flow velocity of described terminal stage.
8. Electrocoppering method as claimed in claim 7 is characterized in that, the processing condition of described transitory stage are specially:
Time: 3～10 seconds, current density: 0.2～0.8 ampere/square decimeter, the silicon chip speed of rotation: 30～50 rev/mins, the electroplate liquid flow velocity: 10～20 liters/minute, silicon chip technology position: 2～5 millimeters.
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Cited By (2)
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| CN104703391A (en) * | 2014-06-10 | 2015-06-10 | 上海美维电子有限公司 | Circuit board and production method thereof |
| CN107502935A (en) * | 2017-07-26 | 2017-12-22 | 武汉新芯集成电路制造有限公司 | A kind of method of electro-coppering |
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| US20040231996A1 (en) * | 2003-05-20 | 2004-11-25 | Novellus Systems, Inc. | Electroplating using DC current interruption and variable rotation rate |
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| CN104703391A (en) * | 2014-06-10 | 2015-06-10 | 上海美维电子有限公司 | Circuit board and production method thereof |
| CN107502935A (en) * | 2017-07-26 | 2017-12-22 | 武汉新芯集成电路制造有限公司 | A kind of method of electro-coppering |
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