CN102163418A - Serial transmission device - Google Patents
Serial transmission device Download PDFInfo
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- CN102163418A CN102163418A CN2010101182282A CN201010118228A CN102163418A CN 102163418 A CN102163418 A CN 102163418A CN 2010101182282 A CN2010101182282 A CN 2010101182282A CN 201010118228 A CN201010118228 A CN 201010118228A CN 102163418 A CN102163418 A CN 102163418A
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Abstract
The invention relates to a serial transmission device, comprising a plurality of data transmission devices which are connected in series. Each data transmission device in serial connection comprises a multi-bit latch, a shifting cache and a switching module, wherein the multi-bit latch is used for providing parallel data, the shifting cache is used for receiving and outputting the parallel data to the multi-bit latch according to a bolt locking signal, and the switching module is used for providing a received data signal and a received time signal to the shifting cache, providing a latching signal to the multi-bit latch before a first clock period (containing a plurality of clocks) is finished after a synchronization signal is received as well as stopping providing of the latch signal to the multi-bit latch and providing a synchronization signal to a data transmission device of the next level before a second clock period is started.
Description
Technical field
The present invention relates to a kind of transmitting device, particularly a kind of serial transmission device.
Background technology
Controller and peripheral device or controller and the communications pattern between the controller can be divided into parallel transmission (Parallel Communication) communicate by letter with serial transmission (SerialCommunication) that communicate by letter.Wherein, serial transmission communication at most only needs three transmission lines (clock cable, data signal line and latch signal line) can transmit and received signal.The serial transmission mode is a mode of transmitting a bit data by a clock signal, in regular turn the serial data of input is passed to the transmitting device of connection.After this serial data all transfers to each transmitting device connected in series, then by a latch signal to latch and to produce a plurality of parallel output signals.
Serial transmission communication can be applicable to various electronic display units, for example with light emitting diode as the traffic signals sign of light emitting source or large board etc.Large board usually is to be arranged by the light emitting diode more than ten thousand to form, and therefore needs a plurality of data transmission devices connected in series to control the illuminated message of described these light emitting diodes.Serial transmission communication also can be applicable to the regional light source control technology (Local DimmingTechnology) of the LED backlight of LCD TV, with the brightness of the diode backlight of dynamic control regional area.
Fig. 1 shows the synoptic diagram of an existing serial transmission device.As shown in Figure 1, this serial transmission device 100 comprises a plurality of data transmission devices connected in series 110, and wherein each data transmission device 110 all comprises a multibit latch 120, an offset buffer 130, clock signal input terminal CLK, a data-signal input end SDI, a data-signal output terminal SDO, a latch signal input end LA and parallel output terminal OUT
1To OUT
NEach offset buffer 130 all comprises N buffer connected in series, wherein a first order buffer is connected to data-signal input end SDI, one afterbody buffer is connected to data-signal output terminal SDO, and each buffer all is connected to clock signal input terminal CLK.Each multibit latch 120 all comprises N latch, and it is connected to each buffer of corresponding offset buffer 130 individually.
For each data transmission device 110, when each clock signal arrives clock signal input terminal CLK, from first order buffer of the serial input data of data-signal input end SDI displacement to its offset buffer 130, and each buffer of this offset buffer 130 with temporary data shift to the next stage buffer.Because the data of each clock period in described data transmission device 110 only are shifted one,, need N clock period all serial data inputs could be finished altogether therefore for comprising the data transmission device 110 of N bit shift buffer 130.
Fig. 2 shows the signal waveforms according to this serial transmission device 100.Refer again to Fig. 1, if this serial transmission device 100 comprises M data transmission device 110 connected in series, then always total M * N buffer connected in series.Because described data transmission device 110 is with relay mode Data transmission, so need M * N clock period all serial datas could be imported described data transmission device 110 altogether.As shown in Figure 2, after treating that all serial data inputs are finished, then a latch signal that is provided by a controller 190 is to described multibit latch 120, to described multibit latch 120, described multibit latch 120 then is connected to the described parallel output terminal OUT of each data transmission device 110 with data latching that described data transmission device 110 is kept in
1To OUT
NWith also line output as described data transmission device 110.
The characteristic of broadcast transmitted pattern is all imported for each data transmission device 110 and is obtained identical data.With regard to broadcast transmitted, this serial transmission device 100 need wait for that still M * N clock period could finish the input of identical data, and can't reach with N clock period and finish the purpose of renewal immediately.On the other hand, because data transmission device 110 is with relay mode Data transmission, though the input data of the top n position of this serial transmission device 100 have been filled up first order offset buffer 130, so need to arrive to afterbody offset buffer 130 through repeatedly changing hand.In other words, this first order offset buffer 130 needs to export the serial input data that is received to its next stage offset buffer 130 in regular turn, can't reach the effect that then exports corresponding multibit latch 120 when obtaining data to.
In view of the above, industry needs a kind of serial transmission device, the position of its data transmission device can more early export the data that received to corresponding multibit latch near controller more, and this serial transmitting device also must possess broadcast mode, can N clock period the N bit data be sent on the N bit shift buffer of all data transmission devices simultaneously.
Summary of the invention
The object of the present invention is to provide a kind of serial transmission device, it can provide the data that received as parallel output signal in real time.And when broadcast mode, also can decrease in the required clock period of input serial data signal.
One embodiment of serial transmission device of the present invention comprises a plurality of data transmission devices connected in series.Described data transmission device connected in series comprises a multibit latch, an offset buffer and all die change pieces.This multibit latch is in order to provide a parallel data.This offset buffer is in order to accept output one parallel data to this multibit latch according to a latch signal.A data-signal that this handover module receives in order to provide and a clock signal are to this offset buffer, and one first clock period (comprising a plurality of clocks) after receiving a synchronous signal finish prerequisite confession one latch signal to this multibit latch, and before a second clock cycle begins, stop to provide this latch signal to this multibit latch and the data transmission device of a synchronous signal to next stage is provided.
One embodiment of serial transmission device of the present invention comprises a plurality of data transmission devices connected in series.Described data transmission device connected in series comprises a multibit latch, an offset buffer and all die change pieces.This multibit latch is in order to provide a parallel data.This offset buffer is in order to accept output one parallel data to this multibit latch according to a latch signal.A data-signal that this handover module receives in order to provide and a clock signal are to this offset buffer, and the end of one first clock period (comprising a plurality of clocks) after receiving synchronous signal prerequisite supplies a latch signal to this multibit latch, and before a second clock cycle begins, stop to provide this data-signal and this clock signal that this data-signal and this clock signal data transmission device to next stage is provided to this offset buffer.
The another embodiment of serial transmission device of the present invention comprises a plurality of data transmission devices connected in series.Described data transmission device connected in series comprises a multibit latch, an offset buffer and all die change pieces.This multibit latch is in order to provide a parallel data.This offset buffer is in order to accept output one parallel data to this multibit latch according to a latch signal.This handover module determines its mode of operation according to a control signal, and comprises a synchronous signal input part, a synchronous signal output part, a data-signal input end, a data-signal output terminal, a clock signal input part, a clock signal output part and a latch signal output terminal.This synchronous signal input end is in order to receive a synchronous signal.This synchronous signal output end is connected to the synchronous signal input end of this synchronous signal input end and next stage data transmission device.This data-signal input end is in order to receive a data-signal.This data-signal output terminal is connected to the data-signal input end of this offset buffer and next stage data transmission device.This clock signal input terminal is in order to receive a clock signal.This clock signal output terminal is connected to the clock signal input terminal of this offset buffer and next stage data transmission device.This latch signal output terminal is connected to this multibit latch.
Sketch out technical characterictic of the present invention above, thus make detailed description hereinafter be obtained preferable understanding.Other technical characterictic that constitutes the protection domain of claims of the present invention will be described in hereinafter.Those skilled in the art of the technical field of the invention should understand, and hereinafter the notion of Jie Shiing can be used as the basis with specific embodiment and quite easily revised or design other structure or manufacture method and realize the purpose identical with the present invention.Those skilled in the art in the technical field of the invention should understand, and the construction of this class equivalence also can't break away from the spirit and scope of the present invention that claims of the present invention propose.
Description of drawings
Fig. 1 shows the synoptic diagram of an existing serial transmission device;
Fig. 2 shows the signal waveforms of an existing serial transmission device;
Fig. 3 shows the synoptic diagram according to the serial transmission device of one embodiment of the invention;
Fig. 4 shows the signal waveforms according to the serial transmission device of one embodiment of the invention;
Fig. 5 shows the synoptic diagram of serial transmission device according to another embodiment of the present invention;
Fig. 6 shows the signal waveforms of serial transmission device according to another embodiment of the present invention; And
Fig. 7 shows the synoptic diagram of serial transmission device according to still another embodiment of the invention.
[primary clustering symbol description]
100 serial transmission devices
110 data transmission devices
120 multibit latches
130 offset buffers
190 controllers
300 serial transmission devices
310 data transmission devices
320 multibit latches
330 offset buffers
340 handover modules
390 controllers
500 serial transmission devices
510 data transmission devices
520 multibit latches
530 offset buffers
540 handover modules
590 controllers
700 serial transmission devices
710 data transmission devices
720 multibit latches
730 offset buffers
740 handover modules
790 controllers
Embodiment
The present invention is a kind of serial transmission device in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed composition will be proposed in following description.Apparently, the execution of the present invention specific details that is not defined in those skilled in the art and had the knack of.On the other hand, well-known composition or step are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, and its description with claims is as the criterion.
Fig. 3 shows the synoptic diagram of the serial transmission device of one embodiment of the invention.This serial transmission device 300 comprises a plurality of data transmission devices connected in series 310, and wherein each data transmission device 310 all comprises a multibit latch 320, an offset buffer 330, all die change piece 340, one synchronous signal input part SYI, a synchronous signal output part SYO, a data-signal input end SDI, a data-signal output terminal SDO, a clock signal input part CKI, a clock signal output part CKO and parallel output terminal OUT
1To OUT
NThis multibit latch 320 comprises N latch, and in order to described parallel output terminal OUT to be provided
1To OUT
NLine output data in the lump.This offset buffer 330 comprises N buffer connected in series, and exports a parallel data to this multibit latch 320 according to a latch signal.This handover module 340 is in order to the connection status of switching this synchronous signal input end SYI, this synchronous signal output end SYO, this data-signal input end SDI, this data-signal output terminal SDO, this clock signal input terminal CKI and this clock signal output terminal CKO and produce a latch signal LA.
As shown in Figure 3, the synchronous signal input end SYI of described data transmission device 310 is connected to the synchronous signal output end SYO of upper level data transmission device 310, data-signal input end SDI is connected to the data-signal output terminal SDO of upper level data transmission device 310, and clock signal input terminal CKI is connected to the clock signal output terminal CKO of upper level data transmission device 310.Wherein, the synchronous signal input end SYI of one first order data transmission device 310 is in order to receive the synchronous signal that a controller 390 is provided, data-signal input end SDI is in order to receiving the serial datum signal that this controller 390 is provided, and clock signal input terminal is in order to receive the clock signal that this controller 390 is provided.In addition, the handover module 340 of each data transmission device 310 provides serial data signal and the clock signal that is received to the offset buffer 330 of this data transmission device 310 and the data transmission device 310 of next stage.
Fig. 4 shows the signal waveforms according to this serial transmission device 300, wherein SYI1 represents the signal that the synchronous signal input end SYI of first order data transmission device 310 is imported, the signal that on behalf of the synchronous signal output end SYO of first order data transmission device 310, SYO1 exported, and the rest may be inferred.When at normal mode, described data transmission device 310 operates in a three-way serial mode.At this moment, whether described data transmission device 310 is temporary in its offset buffer 330 with the serial data signal that is received and depends on whether receive a synchronous signal.When this serial transmission device 300 began to receive serial data signal, 390 of this controllers provided a synchronous signal, serial datum signal and a clock signal.After first order data transmission device 310 received this synchronizing signal, the serial data signal that then begins to be received cooperated the clock signal that is received to be temporary in its corresponding offset buffer 330.After treating for one first clock period (comprising N clock), 340 of the handover modules of this first order data transmission device 310 provide the multibit latch 320 of a latch signal to this first order data transmission device 310, latch in the multibit latch 320 of this first order data transmission device 310 with the serial data that the offset buffer 330 of this first order data transmission device 310 is kept in.Before a second clock cycle began, 340 of the handover modules of this first order data transmission device 310 provided the data transmission device 310 of a synchronous signal to next stage, and stop to provide this latch signal to this first order multibit latch 320.In the present embodiment, because the figure place of described multibit latch 320 and described offset buffer 330 is all N, so this first clock period and this second clock cycle are equal.In other words, this first order data transmission device 310 latched serial data that its offset buffer 330 kept in its multibit latch 320, and the data transmission device 310 of a synchronous signal to next stage is provided simultaneously after N clock period.
In like manner, 310 of second level data transmission devices begin will be received serial data signal cooperate the clock signal that is received to be temporary in the second level offset buffer 330.After treating N clock period, 310 of this second level data transmission devices latch serial data that its offset buffer 330 kept in its multibit latch 320, and the data transmission device 310 of a synchronous signal to next stage is provided simultaneously.As shown in Figure 3, if this serial transmission device 300 comprises M data transmission device 310, then after M * N clock period, this serial transmission device 300 is just finished the input of all serial datas.
Again with reference to figure 1, existing serial transmission device 100 is in the required data of top n clock period input afterbody data transmission device 110, and the serial transmission device 300 of present embodiment is in the required data of top n clock period input first order data transmission device 310.Simultaneously, than existing serial transmission device 100, the serial transmission device 300 of present embodiment can provide the parallel output data of top n position N clock period, and provide N+1 position to 2N parallel output data 2N clock period, so the present invention has more the ability of real-time update.If the serial transmission device 300 of present embodiment is applied to light emitting diode, that is utilize parallel output data that this serial transmission device 300 provided control signal as a plurality of light emitting diodes, than existing serial transmission device 100, the part that this serial transmission device 300 is provided update functions in regular turn can make its light emitting diode of controlling present more comfortable visual effect.
When if this serial transmission device 300 operates in a broadcast mode, for example receive a control signal, described data transmission device 310 operates in a three-line parallel pattern, this moment, the described handover module 340 of described data transmission device 310 directly provided the synchronizing signal that the received data transmission device 310 to next stage, and did not stop to provide latch signal to described multibit latch 320.In other words, each data transmission device 310 is temporary in the serial input signals that is received its offset buffer 330 simultaneously, and is latching data that described offset buffer 330 kept in after N clock period simultaneously in described multibit latch 320.In view of the above, this serial transmission device 300 can just be finished the input of the control signal of broadcasting N clock period, the control signal input of broadcasting could be finished than 100 M * N the required clock period of existing serial transmission device, the present invention can significantly reduce the required time.If the serial transmission device 300 of present embodiment is applied to light emitting diode, comprehensive fine adjustment function at described light emitting diode, for example comprehensive light source control technology (global dimming technology) or following steering order (write command), the serial transmission device 300 of present embodiment all can reach the purpose of renewal rapidly.
Though the described multibit latch 320 of the serial transmission device 300 of present embodiment and the figure place of described offset buffer 330 equate that serial transmission device of the present invention is not limited to this kind embodiment, and should reach in other kind form.For example, the figure place of described multibit latch 320 can be a plurality of integral multiples of the figure place of described offset buffer 330, and for example P doubly.At this moment, to each data transmission device 310, top n is after cycle length, 340 of this handover modules provide a latch signal with the data that latch this offset buffer 330 and kept in the top n position of this multibit latch 320.After 2N cycle length, 340 of this handover modules provide another latch signal with the data that latch this offset buffer 330 and kept in N+1 to 2N of this multibit latch 320.The rest may be inferred, and after P * N cycle length, 310 of this data transmission devices are finished the serial signal input, and this handover module 340 then provides the data transmission device 310 of a synchronous signal to next stage.In view of the above, this clock period is a P * N clock.
Fig. 5 shows the synoptic diagram of serial transmission device according to another embodiment of the present invention.This serial transmission device 500 comprises a plurality of data transmission devices connected in series 510, and wherein each data transmission device 510 all comprises a multibit latch 520, an offset buffer 530, all die change pieces 540, a data-signal input end SDI, a data-signal output terminal SDO, a clock signal input part CKI, a clock signal output part CKO and parallel output terminal OUT
1To OUT
NThis multibit latch 520 comprises N latch, and in order to described parallel output terminal OUT to be provided
1To OUT
NLine output data in the lump.This offset buffer 530 comprises N buffer connected in series, and exports a parallel data to this multibit latch 520 according to a latch signal.This handover module 540 is in order to the connection status of switching this data-signal input end SDI, this data-signal output terminal SDO, this clock signal input terminal CKI and this clock signal output terminal CKO and produce a latch signal LA.
As shown in Figure 5, the data-signal input end SDI of described data transmission device 510 is connected to the data-signal output terminal SDO of upper level data transmission device 510, and clock signal input terminal CKI is connected to the clock signal output terminal CKO of upper level data transmission device 510.Wherein, the data-signal input end SDI of the data transmission device 510 of a first order data transmission device 510 is in order to receiving the serial datum signal that a controller 590 is provided, and clock signal input terminal is in order to receive the clock signal that this controller 590 is provided.When original state, all described handover modules 540 all switch the clock signal that received and serial data signal to described offset buffer 530.
Fig. 6 shows the signal waveforms according to this serial transmission device 500, wherein SDI2 represents the signal that the data-signal input end SDI of second level data transmission device 510 is imported, the signal that on behalf of the data-signal output terminal SDO of first order data transmission device 510, SDO1 exported, the signal that on behalf of the clock signal input terminal CKI of second level data transmission device 510, CKI2 imported, the signal that on behalf of the clock signal output terminal CKO of first order data transmission device 510, CKO1 exported, and the rest may be inferred.When at normal mode, described data transmission device 510 operates in a two-wire serial pattern.At this moment, whether described data transmission device 510 is temporary in its offset buffer 530 with the serial data signal that is received and depends on whether receive a clock signal.When this serial transmission device 500 began to receive serial data signal, 590 of this controllers provided a serial datum signal and a clock signal.After first order data transmission device 510 received this clock signal, the serial data signal that then begins to be received cooperated the clock signal that is received to be temporary in its offset buffer 530.After treating for one first clock period (comprising N clock), 540 of the handover modules of this first order data transmission device 510 provide the multibit latch 520 of a latch signal to this first order data transmission device 510, latch in the multibit latch 520 of this first order data transmission device 510 with the serial data that the offset buffer 530 of this first order data transmission device 510 is kept in.Before the second clock cycle for the treatment of begins, serial data signal that 540 switchings of the handover module of this first order data transmission device 510 are received and clock signal then stop to provide this serial data signal and clock signal to this offset buffer 530 to the data transmission device 510 of next stage.In the present embodiment, because the figure place of described multibit latch 520 and described offset buffer 530 is all N, so this first clock period and this second clock cycle are equal.In other words, this first order data transmission device 510 is after N clock period, then latch serial data that its offset buffer 530 kept in its multibit latch 520, and this serial data signal and this clock signal data transmission device 510 to next stage is provided simultaneously.
In like manner, second level data transmission device 510 begin will be received serial data signal cooperate the clock signal that is received to be temporary in its offset buffer 530.After treating N clock period, 510 of this second level data transmission devices latch serial data that its offset buffer 530 kept in its multibit latch 520, and switch this serial data signal and this clock signal data transmission device 510 to next stage simultaneously.As shown in Figure 6, if this serial transmission device 500 comprises M data transmission device 510, then after M * N clock period, this serial transmission device 500 is just finished the input of all serial datas.
Be similar to the serial transmission device 300 of Fig. 3, the serial transmission device 500 of present embodiment is in the required data of top n clock period input first order data transmission device 510, and can provide the parallel output data of top n position N clock period, and provide the parallel output data of N+1 to the 2N position 2N clock period, and have more the ability of real-time update.
On the other hand, because after M * N clock period, all handover modules 540 all switch the clock signal that received and the serial data signal data transmission device 510 to next stage.At this moment, can import a reset signal to this serial transmission device 500 to reset to original state, in order to the input of next record serial data signal, this reset signal can be that special clock signal and serial data signal or its combination definition form.
When if this serial transmission device 500 operates in a broadcast mode, for example receive a control signal, described data transmission device 510 operates in a two-wire serial pattern, and this moment, 540 of the described handover modules of described data transmission device 510 provided the clock signal that received and the serial data signal data transmission device 510 to described offset buffer 530 and next stage simultaneously.In other words, each data transmission device 510 is temporary in the serial input signals that is received its offset buffer 530 simultaneously, and is latching data that described offset buffer 530 kept in after N clock period simultaneously in described multibit latch 520.In view of the above, this serial transmission device 500 can N clock period with regard to the input of the control signal of finishing broadcasting and significantly reduce the required time.
Be similar to the serial transmission device 300 of Fig. 3, though the described multibit latch 520 of the serial transmission device 500 of present embodiment and the figure place of described offset buffer 530 equate, but serial transmission device of the present invention is not limited to this kind embodiment, and should reach in other kind form.For example, the figure place of described multibit latch 520 can be a plurality of integral multiples of the figure place of described offset buffer 530, and reaches the function of the serial transmission device 300 that is similar to Fig. 3.
Fig. 7 shows the synoptic diagram of serial transmission device according to still another embodiment of the invention.This serial transmission device 700 comprises a plurality of data transmission devices connected in series 710, and wherein each data transmission device 710 all comprises a multibit latch 720, an offset buffer 730, all die change piece 740, one synchronous signal input part SYI, a synchronous signal output part SYO, a data-signal input end SDI, a data-signal output terminal SDO, a clock signal input part CKI, a clock signal output part CKO, two signal input end CTL1 and CTL2 and parallel output terminal OUT
1To OUT
NThis multibit latch 720 comprises N latch, and in order to described parallel output terminal OUT to be provided
1To OUT
NLine output data in the lump.This offset buffer 730 comprises N buffer connected in series, and exports a parallel data to this multibit latch 720 according to a latch signal.This handover module 740 is in order to the connection status of switching this synchronous signal input end SYI, this synchronous signal output end SYO, this data-signal input end SDI, this data-signal output terminal SDO, this clock signal input terminal CKI and this clock signal output terminal CKO and produce a latch signal LA.
This serial transmission device 700 determines its mode of operation according to a controller 790 provides to the control signal of described signal input end CTL1 and CTL2.For example, if this signal input end CTL1 be input as 1 and the input of this signal input end CTL2 also be 1, then this serial transmission device 700 operates in a three-way serial mode.At this moment, the class of operation of this serial transmission device 700 is similar to the normal mode of the serial transmission device 300 of Fig. 3.If this signal input end CTL1 be input as 1 and this signal input end CTL2 be input as 0, then this serial transmission device 700 operates in a three-line parallel pattern.At this moment, the class of operation of this serial transmission device 700 is similar to the broadcast mode of the serial transmission device 300 of Fig. 3.If this signal input end CTL1 be input as 0, and this signal input end CTL2 be input as 1, then this serial transmission device 700 operates in a two-wire serial pattern.At this moment, the class of operation of this serial transmission device 700 is similar to the normal mode of the serial transmission device 500 of Fig. 5.If this signal input end CTL1 is input as 0, and the input of this signal input end CTL2 also is 0, then this serial transmission device 700 operates in a two wires parallel schema.At this moment, the class of operation of this serial transmission device 700 is similar to the broadcast mode of the serial transmission device 500 of Fig. 5.In view of the above, this serial transmission device 700 can be arranged in pairs or groups various dissimilar controllers and can be reached purpose of the present invention equally.
In sum, serial transmission device of the present invention can provide the data that received as parallel output signal in real time.And when broadcast mode, also can decrease in the required clock period of input serial data signal.Simultaneously, serial transmission device of the present invention can be arranged in pairs or groups various dissimilar controllers and still can be reached purpose of the present invention.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still may be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by claims of the present invention.
Claims (24)
1. serial transmission device comprises:
A plurality of data transmission devices connected in series, it respectively comprises:
One multibit latch is in order to latch a parallel data;
One offset buffer provides this parallel data to this multibit latch according to a latch signal; And
All die change pieces, provide the data-signal that received and a clock signal to this offset buffer, and after one first clock period that receives a synchronous signal, provide a latch signal to this multibit latch, and begin prerequisite for the data transmission device of a synchronous signal, and stop to provide this latch signal to this multibit latch to next stage in a second clock cycle that receives this synchronizing signal.
2. serial transmission device according to claim 1, wherein the figure place of this multibit latch equals the figure place of this offset buffer.
3. serial transmission device according to claim 1, wherein the figure place of this multibit latch is a plurality of integral multiples of the figure place of this offset buffer.
4. serial transmission device according to claim 1, wherein if a data transmission device is in a broadcast mode, its handover module then directly provides the synchronizing signal that the received data transmission device to next stage, and does not stop to provide this latch signal to its multibit latch.
5. serial transmission device according to claim 4, wherein whether this data transmission device enters this broadcast mode according to a control signal decision that receives.
6. serial transmission device according to claim 1, the parallel data of wherein said multibit latch output is the light emitting diode control signal.
7. serial transmission device comprises:
A plurality of data transmission devices connected in series, it respectively comprises:
One multibit latch is in order to latch a parallel data;
One offset buffer provides this parallel data to this multibit latch according to a latch signal; And
All die change pieces, provide the data-signal that received and a clock signal to this offset buffer, and provide a latch signal to this multibit latch in one first clock period, and before a second clock cycle begins, stop to provide this data-signal and this clock signal, and provide this data-signal and this clock signal data transmission device to next stage to this offset buffer.
8. serial transmission device according to claim 7, wherein the figure place of this multibit latch equals the figure place of this offset buffer.
9. serial transmission device according to claim 7, wherein the figure place of this multibit latch is a plurality of integral multiples of the figure place of this offset buffer.
10. serial transmission device according to claim 7, wherein if a data transmission device is in a broadcast mode, its handover module then directly provides the data-signal that received and the clock signal data transmission device to its offset buffer and next stage, and does not stop to provide latch signal to its multibit latch.
11. serial transmission device according to claim 10, wherein whether this data transmission device enters this broadcast mode according to a control signal decision that receives.
12. serial transmission device according to claim 7 when wherein receiving a reset signal as if a data transmission device, is then reseted its handover module in original state.
13. serial transmission device according to claim 12 wherein if the input clock signal of a data transmission device is maintained at an identity logic position standard during one set time, judges that then it receives a reset signal.
14. serial transmission device according to claim 7, the parallel data of wherein said multibit latch output is the light emitting diode control signal.
15. a serial transmission device comprises:
A plurality of data transmission devices connected in series, it respectively comprises:
One multibit latch is in order to latch a parallel data;
One offset buffer provides this parallel data to this multibit latch according to a latch signal; And
All die change pieces determine its mode of operation according to a control signal, and this handover module comprises:
One synchronous signal input part is in order to receive a synchronous signal;
One synchronous signal output part is connected to the synchronous signal input end of this synchronous signal input end and next stage data transmission device;
One data-signal input end is in order to receive a data-signal;
One data-signal output terminal is connected to the data-signal input end of this offset buffer and next stage data transmission device;
One clock signal input part is in order to receive a clock signal;
One clock signal output part is connected to the clock signal input terminal of this offset buffer and next stage data transmission device; And
One latch signal output terminal is connected to this multibit latch.
16. serial transmission device according to claim 15, wherein the figure place of this multibit latch equals the figure place of this offset buffer.
17. serial transmission device according to claim 15, wherein the figure place of this multibit latch is a plurality of integral multiples of the figure place of this offset buffer.
18. serial transmission device according to claim 15, wherein when a data transmission device operates in a three-way serial mode, its handover module provides the data-signal that received and the clock signal data transmission device to next stage, and one first clock period after receiving a synchronous signal provides a latch signal to this multibit latch, and before a second clock cycle that receives this synchronizing signal begins, provide the data transmission device of a synchronous signal to next stage, and stop to provide this latch signal to this multibit latch.
19. serial transmission device according to claim 15, wherein when a data transmission device operates in a three-line parallel pattern, its handover module provides the data-signal, clock signal and the synchronizing signal that the are received data transmission device to next stage, and each first clock period after receiving this synchronizing signal provides a latch signal to this multibit latch.
20. serial transmission device according to claim 15, wherein when a data transmission device operates in a two-wire serial pattern, its handover module provides the data-signal that received and clock signal to this offset buffer, and provide a latch signal to this multibit latch in each first clock period, and before a second clock cycle begins, stop to provide this data-signal and this clock signal, and provide this data-signal and this clock signal data transmission device to next stage to this offset buffer.
21. serial transmission device according to claim 15, wherein when a data transmission device operates in a two wires parallel schema, its handover module provides the data-signal that received and the clock signal data transmission device to this offset buffer and next stage, and provides a latch signal to this multibit latch in each first clock period.
22. serial transmission device according to claim 15 when wherein receiving a reset signal as if a data transmission device, is then reseted its handover module in original state.
23. serial transmission device according to claim 22 wherein if the input clock signal of a data transmission device is maintained at an accurate set time of an identity logic position, judges that then it receives a reset signal.
24. serial transmission device according to claim 15, the parallel data of wherein said multibit latch output is the light emitting diode control signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101182282A CN102163418A (en) | 2010-02-23 | 2010-02-23 | Serial transmission device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101182282A CN102163418A (en) | 2010-02-23 | 2010-02-23 | Serial transmission device |
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| CN102163418A true CN102163418A (en) | 2011-08-24 |
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| CN2010101182282A Pending CN102163418A (en) | 2010-02-23 | 2010-02-23 | Serial transmission device |
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| WO2022218129A1 (en) * | 2021-04-14 | 2022-10-20 | 杭州视芯科技股份有限公司 | Led driving circuit, led display system, and display control method |
| CN115766332A (en) * | 2023-01-03 | 2023-03-07 | 杭州视芯科技股份有限公司 | Serial communication device, serial communication system, and serial communication method |
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Application publication date: 20110824 |