CN102184944A - Junction terminal structure of lateral power device - Google Patents
Junction terminal structure of lateral power device Download PDFInfo
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- CN102184944A CN102184944A CN2011101124008A CN201110112400A CN102184944A CN 102184944 A CN102184944 A CN 102184944A CN 2011101124008 A CN2011101124008 A CN 2011101124008A CN 201110112400 A CN201110112400 A CN 201110112400A CN 102184944 A CN102184944 A CN 102184944A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 66
- 229920005591 polysilicon Polymers 0.000 claims abstract description 66
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 230000005611 electricity Effects 0.000 claims description 16
- 239000002019 doping agent Substances 0.000 claims description 15
- 230000011218 segmentation Effects 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 230000035755 proliferation Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- 230000005684 electric field Effects 0.000 description 20
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 238000009826 distribution Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
The invention discloses a junction terminal structure of a lateral power device. The structure at least comprises three semiconductor doping regions, a side wall oxidation zone and a side wall field plate region, which are sequentially connected, wherein the side wall field plate region is positioned at the two ends of the device; the doping region positioned at one end is a first kind of conducting type and forms a channel region (or the anode) of the device; the doping region positioned at the other end is a second kind of conducting type and forms a drain electrode region (or the cathode) of the device; the semiconductor doping region positioned in the middle is the second kind of conducting type and forms a drift region of the device; the lower part of the drift region is connected with an epitaxial layer; the upper part of the drift region is connected with a field oxide layer; the side of the drift region is connected with an oxidation zone; polysilicon is etched and deposited in the side wall oxidation zones of a source area and a drain area to form a slope-shaped or multi-step shaped three-dimensional (3D) field plate; the field plate is in electric contact with a grid electrode and a drain electrode respectively; and the side wall field plate is required to extend into the surface of a substrate to enter the substrate. When a PN diode, a lateral diffused metal oxide semiconductor (LDMOS) or a lateral insulated gate bipolar transistor (LIGBT) is manufactured through the structure, the structure has the advantages of high breakdown voltage, low on resistance, simple process, low cost and the like.
Description
Technical field
The invention belongs to semiconductor power device technology and field of semiconductor technology, relate in particular to the lateral power knot terminal technology of high-power and high-voltage applications, as horizontal proliferation field-effect transistor LDMOS, horizontal high-voltage diode, landscape insulation bar double-pole-type transistor LIGBT etc.
Background technology
As everyone knows, in the design process of lateral power, must take all factors into consideration influencing each other of factors such as puncture voltage, conducting resistance, process complexity and reliability, make it reach a comparatively reasonably compromise.The common raising of performance in a certain respect tends to cause the degeneration of others performance, and puncture voltage and conducting resistance promptly exist such contradictory relation.How when improving puncture voltage, the constant of conducting resistance can be kept or the focus that conducting resistance is research always can be reduced as best one can.
For conventional lateral power, influenced owing to tie the edge curvature effect, puncture voltage can be had a greatly reduced quality than theoretical value, and particularly performance is particularly evident under the situation of shallow junction diffusion and small curve.For addressing this problem, the article that people such as A.S.Grove delivered in March, 1967 " surface field is to the influence of plane PN junction puncture voltage " (IEEE TransElectron Devices, vol.ED-14, field plate techniques has been proposed pp.157-162) at first, originally it is used to reduce the PN junction peak electric field,, technology simple in structure because of it and integrated circuit technology are compatible fully and effect is obvious, so obtained rapidly using widely in the discrete junction device of high pressure, power MOS (Metal Oxide Semiconductor) device, high-voltage power integrated circuit.The basic structure of field plate as shown in Figure 1, on Semiconductor substrate 100, carry out twice doping respectively and form the first kind conductiving type semiconductor area 102 and the second class conductiving type semiconductor area 104, promptly constitute PN junction, on silicon dioxide layer 120 above this PN junction, cover layer of metal layer 110, we claim that this metal level is the metal field plate, if at the suitable voltage of field plate upper offset, to induce interface charge at the upper surface of silicon, the electric field that these interface charges produce can weaken the peak value electric field of PN junction greatly, thereby improves puncture voltage.
United States Patent (USP) 6468837 applies to field plate techniques in RESURF (the reduced surface field) device, and has provided technologic performing step, and its structure as shown in Figure 2.It is mainly by lightly doped first kind conductive type epitaxial layer semiconductor regions 100, the semiconductor regions 102 of first kind conduction type, the semiconductor regions 101 of heavily doped first kind conduction type, the semiconductor regions 103,105 of the second class conduction type, the more lightly doped second class conductiving type semiconductor area 104 (Resurf implantation region), cover the oxygen district, field 120 on the semiconductor regions 104, development length surpasses above grid field plate 110 composition such as grade of half length of oxygen.This structure and the difference of common Resurf LDMOS device are that mainly grid has extended one section field plate, knot field, edge surface peak is inhibited, thereby has improved puncture voltage.Yet for this common planar field plate, an outstanding problem of existence is that the field plate boundary will form high peak electric field, thereby has limited the further raising of puncture voltage.
In order to solve the problem of the high peak electric field in field plate edge, the article that people such as K.Brieger delivered in May, 1988 " a kind of analytic approximation of optimization field plate profile " (IEEE TransElectron Devices, Vol.35, pp.684-688) show when the oxidated layer thickness of field plate below increases continuously with certain gradient by Theoretical Calculation the earliest in, can eliminate the peak electric field of field plate below fully, so proposed the notion of oblique field plate.Though yet tiltedly field plate can be realized surface field fully uniformly, but is difficult to make, and is especially incompatible with integrated circuit technology.United States Patent (USP) 753930 has provided the LDMOS structure of multi-ladder field plate structure, as shown in Figure 3.Different with conventional LDMOS is, is increasing stair-stepping oxide layer 120 and polysilicon field plate 110 near drain terminal, and the field plate of minimum single order carries out electricity with the source end again and is connected.The Electric Field Distribution of this structure lower surface drift region is more even, and voltage endurance is improved to a certain extent.Yet the shortcoming of this method is to need a plurality of additional masking versions and multistep additional process to make the multi-ladder field plate, has increased process complexity, has improved cost.
A kind of lateral power structure of segmentation field plate has been proposed, as shown in Figure 4 in the United States Patent (USP) 7230313.The distinguishing feature of this structure is to have multistage to separate the field plate 110,112,114,116 of certain distance on surface oxide layer 120.Each field plate is biased different voltage by the potential-divider network that is connected and composed by many resistance, can make the peak electric field at each field plate edge be tending towards identical, i.e. critical breakdown electric field, thus puncture voltage is improved.But to the lateral power of this structure, potential-divider network more complicated and be not easy to regulate.
Above-mentioned various structures all are to reach at power device surface preparation field plate to regulate surperficial effect of electric field, but the preparation technology of the multistage scalariform of image surface, skewed field plate is very complicated, and effect is not very desirable.
Summary of the invention
Technical problem: the purpose of this invention is to provide the junction termination structures in the another kind of lateral power, adopt this structure, not only can realize any physical dimension and the arbitrarily preparation of the oblique field plate of the multi-ladder field plate of ladder number and arbitrary shape at sidewall, thereby bring into play the field action that falls of field plate fully, farthest improve breakdown characteristics, can also suppress the body internal electric field simultaneously, the optimal value of drift region concentration is improved, thereby the reduction conducting resistance increases operating current.In addition, this structure fabrication technology only need increase a mask can realize being difficult in the conventional planar field plate multi-ladder field plate of realization and the tiltedly preparation of field plate, the basic compatibility fully of its technology and standard CMOS process, thus reduce manufacturing cost.
Technical scheme: the junction termination structures of lateral power of the present invention comprises area, semiconductor regions with first kind conduction type, semiconductor regions with second class conduction type of high-dopant concentration, separate by a semiconductor regions and an avris sidewall oxide arranged side by side between the two with second class conduction type of low doping concentration, semiconductor regions has constituted the drift region of power device, sidewall oxide is near the two ends photoetching deposit first slope shape polysilicon field plate, the second slope shape polysilicon field plate, this two slope shapes polysilicon field plate respectively with grid, drain electrode electricity connects.
Semiconductor regions is as the semiconductor regions of the second class conduction type with low doping concentration of drift region, and its concentration is uniform.
Sidewall oxide is positioned at the semiconductor regions avris as the drift region, and its vertical depth surpasses drift region thickness, enters area inside.
The vertical depth of the first slope shape polysilicon field plate, the second slope shape polysilicon field plate need surpass the thickness as the semiconductor regions of drift region, enters area inside.
Area is a semi-conducting material, perhaps is silicon dioxide oxide layer SOI.
The first slope shape polysilicon field plate, the second slope shape polysilicon field plate can also separate the segmentation field plate of shape for multistage scalariform or multistage, and the segmentation field plate is floating empty, or by the different voltage of potential-divider network biasing.
Sidewall oxide is a silicon dioxide.
The concrete form of described lateral power is horizontal proliferation field-effect transistor LDMOS, horizontal PN diode, landscape insulation bar double-pole-type transistor LIGBT or lateral thyristor.
Beneficial effect: sidewall field plate structure of the present invention can adopt following prepared.At first etching and filled sidewall oxide layer, this step can utilize the dielectric isolation operation to finish, without any need for additional masking version and additional process, next photoetching field plate figure, the shape of figure is determined that by numerical simulation results its degree of depth should be slightly larger than the thickness of top layer silicon, then carries out the polysilicon deposit, form field plate, can finish the processing of LDMOS subsequently according to standard CMOS process.This shows that this technology is one and the compatible fully process program of standard CMOS process, only need to increase a photoetching, by adjusting the mask figure, can finish the oblique field plate of side direction arbitrary shape, the ladder field plate of any ladder or the making of various types of floating barnyard plates.Device by the preparation of this method is the scalable surface field not only, simultaneously can the control agent internal electric field, reach the effect that significantly improves puncture voltage, and the drift region concentration figure of merit also obtained bigger lifting, and the I-V characteristic is better.
Description of drawings
Fig. 1 is a plane PN junction field plate structure schematic diagram.
Fig. 2 is a RESURF LDMOS planar field plate structural representation.
Fig. 3 is a plane multi-ladder field plate structure LDMOS schematic diagram.
Fig. 4 is a kind of improved segmentation field plate structure lateral power structural representation.
Fig. 5 is the oblique field plate structure LDMOS of the sidewall structure three-dimensional view that has of the present invention.Semiconductor regions 101 with first kind conduction type of high-dopant concentration constitutes the channel region of LDMOS, semiconductor regions 103 with second class conduction type of high-dopant concentration constitutes the drain terminal of LDMOS, be connected side by side with sidewall oxide 120 with the semiconductor regions 102 that has than the second class conduction type of light dope concentration between source end and the drain terminal, semiconductor regions 102 is as the drift region, form slope shape field plate 110 near source electrode and drain electrode two ends photoetching deposit polysilicon in the sidewall oxide 120,112, field plate 110 is connected with grid 131 electricity, and field plate 112 is connected with drain electrode 132 electricity.
Fig. 6 a is the vertical view with the oblique field plate structure LDMOS of sidewall of the present invention.
Fig. 6 b is the sectional view with the oblique field plate structure LDMOS of sidewall along AB line among Fig. 6 a of the present invention.
Fig. 6 c is the sectional view with the oblique field plate structure LDMOS of sidewall along CD line among Fig. 6 a of the present invention.
Fig. 7 a is the vertical view with the oblique field plate structure transverse p/n junction of sidewall of the present invention.
Fig. 7 b is the sectional view with the oblique field plate structure transverse p/n junction of sidewall along AB line among Fig. 7 a of the present invention.
Fig. 8 a is the vertical view with sidewall multi-ladder field plate structure LDMOS of the present invention.Different with Fig. 6 is that the sidewall field plate at two ends has been made symmetrical multistage scalariform respectively.
Fig. 8 b is the sectional view with sidewall multi-ladder field plate structure LDMOS along AB line among Fig. 8 a of the present invention.
Fig. 9 a is a kind of form with the floating barnyard plate structure LDMOS of sidewall of the present invention.Different with Fig. 6 is, the sidewall field plate is made into the floating empty shape of segmentation, and the field plate spacing is begun to be contracted to gradually by the source end in the middle of the drift region, increases the formation symmetry shape gradually toward drain terminal again, and each section field plate length is consistent with width.
Fig. 9 b is the sectional view of Fig. 9 a along the AB line.
Figure 10 a is the another kind of form with the floating barnyard plate structure LDMOS of sidewall of the present invention.The same with Fig. 9, the avris field plate is made into the floating empty shape of segmentation, but each section field plate width begins to be decreased to gradually the middle part, drift region from the source end, increases the formation symmetry shape gradually toward the drain terminal direction again, and the field plate spacing does not change.
Figure 10 b is the sectional view of Figure 10 a along the AB line.
Figure 11 a is the oblique field plate structure LIGBT of the sidewall vertical view that has of the present invention.
Figure 11 b is the sectional view of Figure 11 a along the AB line.
Figure 12 is that conventional Resurf structure and the oblique field plate Resurf of sidewall of the present invention structure lateral power equipotential lines distribute, longitudinal electric field distributes and the puncture voltage comparison diagram.
Figure 13 is conventional Resurf structure and the oblique field plate Resurf of sidewall of the present invention structure lateral power I-V output characteristic curve figure.
Embodiment
The invention provides the junction termination structures in a kind of lateral power.Fig. 5 is the 3D view of this structure, and Fig. 6 a is the vertical view of this structure, and Fig. 6 b is the sectional view of this structure along AB line among Fig. 6 a, and Fig. 6 c is the sectional view of this structure along CD line among Fig. 6 a.As can be seen, it is in silica-based on the area 100 of first kind conduction type, the semiconductor regions 101 of the first kind conduction type by twice highly doped formation high-dopant concentration, the semiconductor regions 103 of the second class conduction type of high-dopant concentration, the two semiconductor regions 102 by the second class conduction type of light dope concentration links to each other, semiconductor regions 102 is used as the drift region, the sidewall use oxygen of semiconductor regions 102 is filled and is formed sidewall oxide 120 arranged side by side with it simultaneously, and sidewall oxide 120 extends vertically up in the area 100.Form the first slope shape polysilicon field plate 110, the second slope shape polysilicon field plate 112 at two ends photoetching deposit polysilicon near sidewall oxide 120, the first slope shape polysilicon field plate 110 is connected with grid 131 electricity, the second slope shape polysilicon field plate 112 is connected with drain electrode 132 electricity, and the upper surface that the first slope shape polysilicon field plate 110, the second slope shape polysilicon field plate 112 also will extend vertically up to above area 100 enters in the area 100.
The junction termination structures of lateral power comprises area 100, semiconductor regions 101 with first kind conduction type, semiconductor regions 103 with second class conduction type of high-dopant concentration, separate by a semiconductor regions 102 and an avris sidewall oxide 120 arranged side by side between the two with second class conduction type of low doping concentration, semiconductor regions 102 has constituted the drift region of power device, sidewall oxide 120 is near the two ends photoetching deposit first slope shape polysilicon field plate 110, the second slope shape polysilicon field plate 112, this two slope shapes polysilicon field plate respectively with grid 131,132 electricity that drain connect.
Need to prove
(1) CONCENTRATION DISTRIBUTION of the semiconductor regions 102 of the described second class conduction type with low doping concentration is uniform.
(2) material of described sidewall oxide 120 is a silicon dioxide.
(3) described sidewall oxide 120, the first slope shape polysilicon field plate 110, the second slope shape polysilicon field plate (112) all need vertical extent to enter area 100 inside, to play the effect that suppresses the body internal electric field.
(4) described area 100 can be lightly doped semiconductor (a body silicon), also can be silicon dioxide oxide layer (SOI).
(5) promptly the first slope shape polysilicon field plate 110, the second slope shape polysilicon field plate 112 both can have been made sidewall ramp shape to described sidewall field plate region, also can make sidewall multistage trapezoidal (as Fig. 8), can also make multiple side wall segment field plate type (as Fig. 9,10), the segmentation field plate can also can be biased different voltage for floating empty shape.
(6) described sidewall field plate structure can be used in combination with the common plane field plate, better falls an effect to reach.
(7) described field plate structure can also be used for horizontal PN diode (as Fig. 7), LIGBT (as Figure 11), lateral thyristor constant power device, with breakdown characteristics and the on state characteristic that improves device simultaneously.
Operation principle of the present invention:
Figure 12 is that the equipotential lines of the conventional RESURF structure sketched the contours according to preliminary simulation results and the oblique field plate Resurf of sidewall 3D structure distributes, longitudinal electric field distributes and the puncture voltage comparison diagram.The structural parameters of two kinds of structures are identical, and the drift region CONCENTRATION DISTRIBUTION is then optimized.By Figure 12 a as can be seen, intensive for conventional RESURF structure, middle sparse in the surperficial equipotential lines at two ends, drift region, thus cause two ends very high peak electric field to occur, reduced puncture voltage.And for the oblique field plate structure of the 3D among Figure 12 b, the drift region equipotential lines distributes and is close to evenly, and surface field is approximately constant, thereby makes puncture voltage obtain increasing substantially.Figure 12 c is that the identical longitudinal electric field that adds drain terminal below under the bias condition distributes, as can be seen, because the shielding action of field plate, the longitudinal electric field of the oblique field plate of 3D distributes also more even than conventional RESURF structure, peak value electric field on its top layer silicon/oxygen buried layer interface is also lower, and this explanation 3D field plate also has vertically withstand voltage effect of improvement.The oblique field plate structure of 3D is pressed with significantly than the breakdown potential of conventional RESURF structure and promotes as can be seen from Figure 12 d, and the drift region concentration figure of merit is also higher.
Figure 13 has compared the IV characteristic curve of above two kinds of structures.As can be seen, the linear zone resistance of the oblique field plate structure of 3D is far smaller than conventional RESURF structure, and its saturation current also is higher than conventional RESURF structure far away simultaneously.The optimum drift region concentration that its reason can ascribe the 3D field plate structure to is increased dramatically than conventional RESURF structure.
According to lateral power structure provided by the invention, can produce the oblique field plate of sidewall, multi-ladder field plate, the segmentation field plate structure lateral power of characteristic good, be exemplified below:
1) has the LDMOS of the oblique field plate of sidewall, as Fig. 5, Fig. 6.It comprises the area 100 of first kind conduction type, the semiconductor regions 101 of the first kind conduction type by twice highly doped formation high-dopant concentration, and the semiconductor regions 103 of the second class conduction type of high-dopant concentration is respectively as source region and drain region.The two semiconductor regions 102 by the second class conduction type of light dope concentration links to each other, semiconductor regions 102 is used as the drift region, its CONCENTRATION DISTRIBUTION formula is uniform, the avris use oxygen of semiconductor regions 102 is filled formation sidewall oxide arranged side by side with it 120 simultaneously, sidewall oxide 120 links to each other with semiconductor regions 101,103, and extends vertically up in the area 100.Form the first slope shape polysilicon field plate 110, the second slope shape polysilicon field plate 112 at sidewall oxide 120 near both sides photoetching deposit polysilicon, the first slope shape polysilicon field plate 110 is connected with grid 131 electricity, the second slope shape polysilicon field plate 112 is connected with drain electrode 132 electricity, and the upper surface that the first slope shape polysilicon field plate 110, the second slope shape polysilicon field plate 112 also will extend to more than area 100 enters in the area 100.
2) has the LDMOS of sidewall multi-ladder field plate, as shown in Figure 8.It comprises the area 100 of first kind conduction type, the semiconductor regions 101 of the first kind conduction type by twice highly doped formation high-dopant concentration, and the semiconductor regions 103 of the second class conduction type of high-dopant concentration is respectively as source end and drain terminal.The two semiconductor regions 102 by the second class conduction type of light dope concentration links to each other, semiconductor regions 102 is used as the drift region, its CONCENTRATION DISTRIBUTION formula is uniform, the avris use oxygen of semiconductor regions 102 is filled formation sidewall oxide arranged side by side with it 120 simultaneously, sidewall oxide 120 links to each other with semiconductor regions 101,103, and extends vertically up in the semiconductor regions 100.Close both sides photoetching deposit polysilicon at sidewall oxide 120 forms the first stairstepping polysilicon field plate 110, the second stairstepping polysilicon field plate 112 of multistage scalariform back-to-back, the first stairstepping polysilicon field plate 110 is connected with grid 131 electricity, the second stairstepping polysilicon field plate 112 is connected with drain electrode 132 electricity, and the upper surface that the first stairstepping polysilicon field plate 110, the second stairstepping polysilicon field plate 112 also will extend to more than area 100 enters in the area 100.
3) has the LDMOS of side wall segment field plate, as shown in Figure 9.It comprises the area 100 of first kind conduction type, the semiconductor regions 101 of the first kind conduction type by twice highly doped formation high-dopant concentration, and the semiconductor regions 103 of the second class conduction type of high-dopant concentration is respectively as source end and drain terminal.The two semiconductor regions 102 by the second class conduction type of light dope concentration links to each other, semiconductor regions 102 is used as the drift region, its CONCENTRATION DISTRIBUTION formula is uniform, the avris use oxygen of semiconductor regions 102 is filled formation sidewall oxide arranged side by side with it 120 simultaneously, sidewall oxide 120 links to each other, and extends vertically up in the semiconductor regions 100 with the semiconductor regions 101 of first kind conduction type, the semiconductor regions 103 of the second class conduction type.At first rectangle polysilicon field plate 110, second rectangle conformal polysilicon field plate 112, three rectangle polysilicon field plate 114, four rectangle polysilicon field plate 116, five rectangle polysilicon field plate 118, six rectangle polysilicon field plate 117, seven rectangle polysilicon field plate 115, eight rectangle polysilicon field plate 113, the nine rectangle polysilicon field plate 111 of sidewall oxide 120 from the source end to drain terminal photoetching deposit segmentation, the segmentation field plate distributes and is symmetry shape, spacing narrows down to sidewall oxide 120 middle parts gradually from the source end between field plate, increases gradually toward the drain terminal direction again.The first rectangle polysilicon field plate 110 is connected with grid 131 electricity, and the 9th rectangle polysilicon field plate 111 is connected with drain electrode 132 electricity, and the upper surface that each section field plate all will extend vertically up to above area 100 enters in the area 100.
4) has the LDMOS of another kind of form side wall segment field plate, as shown in figure 10.It comprises the area 100 of first kind conduction type, the semiconductor regions 101 of the first kind conduction type by twice highly doped formation high-dopant concentration, and the semiconductor regions 103 of the second class conduction type of high-dopant concentration is respectively as source end and drain terminal.The two semiconductor regions 102 by the second class conduction type of light dope concentration links to each other, semiconductor regions 102 is used as the drift region, its CONCENTRATION DISTRIBUTION formula is uniform, the avris use oxygen of semiconductor regions 102 is filled formation sidewall oxide arranged side by side with it 120 simultaneously, sidewall oxide 120 links to each other with semiconductor regions 101,103, and extends vertically up in the semiconductor regions 100.The first rectangle polysilicon field plate 110 from the source end to drain terminal photoetching deposit segmentation in sidewall oxide 120, the second rectangle polysilicon field plate 112, the 3rd rectangle polysilicon field plate 114, the 4th rectangle polysilicon field plate 116, the 5th rectangle polysilicon field plate 115, the 6th rectangle polysilicon field plate 113, the 7th rectangle polysilicon field plate 111, the segmentation field plate distributes and is symmetry shape, spacing is constant between field plate, field plate self width is contracted to sidewall oxide 120 middle parts gradually from the source end, increases gradually toward the drain terminal direction again.The first rectangle polysilicon field plate 110 is connected with grid 131 electricity, and the 7th rectangle polysilicon field plate 111 is connected with drain electrode 132 electricity, and the upper surface that each section field plate all will extend vertically up to above area 100 enters in the area 100.
Need to prove, the lateral direction power transistor structure that the present invention proposes is except can being applied to top LDMOS device, also can be used for other unlisted lateral powers such as transverse diffusion p N knot, lateral thyristor, sidewall field plate type can be adjusted according to actual needs, perhaps be used, to reach better electric field modulation effect with planar field plate.
Claims (8)
1. the junction termination structures of a lateral power, it is characterized in that: it comprises area (100), semiconductor regions (101) with first kind conduction type, semiconductor regions (103) with second class conduction type of high-dopant concentration, separate by a semiconductor regions (102) and an avris sidewall oxide (120) arranged side by side between the two with second class conduction type of low doping concentration, semiconductor regions (102) has constituted the drift region of power device, sidewall oxide (120) is near the two ends photoetching deposit first slope shape polysilicon field plate (110), the second slope shape polysilicon field plate (112), this two slope shapes polysilicon field plate respectively with grid (131), drain electrode (132) electricity connects.
2. the junction termination structures of lateral power according to claim 1, it is characterized in that: semiconductor regions (102) is as the semiconductor regions of the second class conduction type with low doping concentration of drift region, and its concentration is uniform.
3. the junction termination structures of lateral power according to claim 1, it is characterized in that: sidewall oxide (120) is positioned at semiconductor regions (102) avris as the drift region, and its vertical depth surpasses drift region thickness, enters area (100) inside.
4. the junction termination structures of lateral power according to claim 1 and 2, it is characterized in that: the vertical depth of the first slope shape polysilicon field plate (110), the second slope shape polysilicon field plate (112) need surpass the thickness as the semiconductor regions (102) of drift region, enters area (100) inside.
5. lateral power according to claim 4 is characterized in that: area (100) is a semi-conducting material, perhaps is silicon dioxide oxide layer SOI.
6. the junction termination structures of lateral power according to claim 4, it is characterized in that: the first slope shape polysilicon field plate (110), the second slope shape polysilicon field plate (112) can also separate the segmentation field plate of shape for multistage scalariform or multistage, the segmentation field plate is floating empty, or by the different voltage of potential-divider network biasing.
7. the junction termination structures of horizontal lateral power according to claim 1, it is characterized in that: sidewall oxide (120) is a silicon dioxide.
8. the junction termination structures of lateral power according to claim 1 is characterized in that: the concrete form of described lateral power is horizontal proliferation field-effect transistor LDMOS, laterally PN diode, landscape insulation bar double-pole-type transistor LIGBT or lateral thyristor.
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| CN103996710A (en) * | 2013-02-18 | 2014-08-20 | 飞兆半导体公司 | Ldmos device with double-sloped field plate |
| CN104241132A (en) * | 2013-06-18 | 2014-12-24 | 北大方正集团有限公司 | Ldmos and manufacturing method thereof |
| CN108376701A (en) * | 2017-02-01 | 2018-08-07 | 富士电机株式会社 | Semiconductor device |
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| CN114429987B (en) * | 2022-04-01 | 2022-06-03 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN115863406A (en) * | 2023-03-02 | 2023-03-28 | 广州粤芯半导体技术有限公司 | Lateral diffusion metal oxide semiconductor device |
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