CN102222691A - High drive-current three-dimensional multiple-gate transistor and manufacturing method thereof - Google Patents
High drive-current three-dimensional multiple-gate transistor and manufacturing method thereof Download PDFInfo
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- CN102222691A CN102222691A CN 201010145465 CN201010145465A CN102222691A CN 102222691 A CN102222691 A CN 102222691A CN 201010145465 CN201010145465 CN 201010145465 CN 201010145465 A CN201010145465 A CN 201010145465A CN 102222691 A CN102222691 A CN 102222691A
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Abstract
The invention provides a high drive-current three-dimensional multiple-gate transistor and a manufacturing method thereof. The transistor includes a silicon substrate; an isolation layer which is formed on a surface of the silicon substrate; a plurality of gates which are vertically arranged on a surface of the isolation layer (insulating layer). Each gate comprises a Si-fin; a SiGe channel which is formed on an outside of the silicon fin; a Hi-K gate dielectric layer which is formed on the outside of the silicon germanium channel layer; a protection layer which is through a thermal treatment and is formed on a top of the Si-fin, the SiGe channel and the Hi-K gate dielectric layer. The high drive-current three-dimensional multiple-gate transistor and the manufacturing method thereof accord with development trend of a three dimensional and multiple gate structure in semiconductor industry. Compared to the silicon channel of present N/PMOS, a brand new three-dimensional metal gate structure, which contains the SiGe channel and the Hi-K gate dielectric layer, can achieve higher drive current liquidity. Practical value is high.
Description
Technical field
The present invention is relevant with CMOS (Complementary Metal Oxide Semiconductor) (CMOS), is meant three-dimensional multiple-gate transistor of a kind of high drive current and method for making thereof especially.
Background technology
The micro of CMOS (Complementary Metal Oxide Semiconductor) (CMOS) size can bring two big benefits, the one, the raising of element function, the 2nd, the reduction of power consumption.Yet nowadays this trend but reached the limit, the problem of aspect such as the copper-connection in the element has caused crosstalking, power consumption and resistance-capacitance (RC) delay.
In general, the micro of CMOS (Complementary Metal Oxide Semiconductor) size is that the gate pole oxidation layer of key is reached optimized purpose in the mode that reduces thickness.Yet, when time-histories enters nanometer nodes, traditional silicon dioxide can't be reached good passage control ability by continuing to reduce thickness again, its too high leakage current will make size dwindle downwards and become unsustainable, though the scheme of using silicon oxynitride is arranged at present, the generation evolution of right its limited dielectric coefficient and the CMOS (Complementary Metal Oxide Semiconductor) that can't effectively extend, each big CMOS (Complementary Metal Oxide Semiconductor) manufactory is all attempting the improvement that different several directions are reached element characteristic at present.For example, add local or comprehensive strain structure and promote the carrier transmission speed, with lift elements usefulness by silicon crystal lattice constant in the adaptability to changes change passage.Yet, depend merely on strain gauge technique and may still can't continue to reach 45nm or the following element efficiency of being expected of 32nm.And import the mode of high K dielectric matter and stable work function gate metal level, because charged carrier can penetrate dielectric medium by tunneling effect and form leakage current, importing high K dielectric matter replacement traditional Si O2 or SiON becomes one of feasible scheme, in the hope of reducing leakage current and reaching equivalent capacity with the control channel switch.
In addition, also have manufacturer to change 50 years in the past since accepted standard plane (two-dimensional, dual space) electric crystal framework all always, formed the framework of three-dimensional space (three-dimensional).For example, Infineon's science and technology (Infineon Technologies) has been delivered multiple-gate field effect electric crystal (Multi-gate field-effect transistor) technology, is one of solution in the face of numerous challenges in future.On the little integrated circuit that needs numerous functions again of area, the power that the single gate technology in the plane of comparable today (Planar single-gate) is consumed is much smaller.In a displaying of this new technology, the researcher of Infineon has tested and has adopted brand-new 65nm multiple-gate field effect electric crystal framework, first high complexity circuit of the manufacturing whole world, compare with the present single gate identical function that technology is produced and the product of usefulness, it is about 30% that its area almost will dwindle, the quiescent current of the new electric crystal of this class 1/10th before being.Calculating according to the researcher, compare with the 65nm technology of using at procedure for producing at present, so quiescent current will make the energy service efficiency and the battery life increase of the portable device of employing reach about one times, and following process technique (32nm and following technology) also will further significantly improve this ratio.
The 65nm circuit of being tested by the researcher of Infineon comprises above 3,000 active electric crystal, many results all confirm the excellence that three-dimensional space multiple-gate technology is the same with current various mature technologies, but with identical various functions, the energy that is consumed has only the conventional planar gate about half, in the technology generation in future, this advantage will be sure of can be more and more important.
So far, the CMOS (Complementary Metal Oxide Semiconductor) patent of relevant multiple-gate structure is a lot of, do not give unnecessary details one by one herein, and about the multiple-gate structure of all non-three-dimensional of patent of three-dimensional gate CMOS (Complementary Metal Oxide Semiconductor).In other words, San Wei multiple-gate CMOS (Complementary Metal Oxide Semiconductor) structure obviously is the semiconductor industry developing tendency in future.
Summary of the invention
Main purpose of the present invention is to provide three-dimensional multiple-gate transistor of a kind of high drive current and method for making thereof, its not only meet semiconductor industry not tomorrow three-dimensional, multiple-gate structural development trend; And brand-new three-dimensional gate structure can have higher drive current flowability compared to the silicon passage of existing N/PMOS, and practical value is excellent.
Goal of the invention of the present invention is achieved by following technical proposals:
The three-dimensional multiple-gate transistor of a kind of high drive current is characterized in that: comprise
One silicon base;
One separator is formed at this silicon base surface;
Several gates are vertically installed in this surface of insulating layer; Each gate comprises a silicon fin respectively; One SiGe channel layer is formed at this silicon fin outside; One high-k brake-pole dielectric layer is formed at this SiGe channel layer outside; One protective layer through heat treatment, is formed at this silicon fin, SiGe channel layer and high-k brake-pole dielectric layer top.
Described isolation series of strata are imbedded oxide layer.
Described protective layer adopts the silicon nitride material.
Also include one first hard mask layer, be formed at described protective layer surface.
Described each gate and insulation surface also are formed with a metal gate.
The transistorized method for making of the three-dimensional multiple-gate of a kind of high drive current is characterized in that: include following steps at least:
A) provide a fin formula half field effect electric crystal structure, several silicon fin that this fin formula half field effect electric crystal structure comprises a silicon base, is formed at a separator on silicon base surface and is vertically installed in surface of insulating layer;
B) deposition one protective layer is in the silicon fin top;
C) form one first hard mask layer in protective layer surface deposition and etching, patterning;
D) heat-treat, make this each silicon fin lateral wall form a sacrificial oxide layer respectively;
E) remove this each sacrificial oxide layer;
F) form a SiGe channel layer in this each silicon fin outside;
G) form a high-k brake-pole dielectric layer in this each SiGe channel layer outside;
H) deposition one gate metal level is in this each gate and insulation surface;
I) with this gate metal level etching, patterning.
In the described step c), the mode of described deposition is to utilize chemical vapour deposition technique; The mode of described etching, patterning is to utilize the reactive ion etching machine to carry out etching, be patterned into etch stop layer.
In the described step d), described heat treated mode is a thermal oxidation, and this sacrificial oxide layer is a silicon dioxide.
In the described step e), be to utilize the hydrofluoric acid or the buffer oxide layer etchant of dilution to remove described each sacrificial oxide layer.
In the described step f), be to form the SiGe channel layer in this each silicon fin outside with the building crystal to grow method.
The invention has the beneficial effects as follows: three-dimensional multiple-gate transistor of this high drive current and method for making thereof, its not only meet semiconductor industry not tomorrow three-dimensional, multiple-gate structural development trend, and, the brand-new 3-dimensional metal gate structure that comprises SiGe channel layer and high-k brake-pole dielectric layer can have higher drive current flowability compared to the silicon passage that has N/PMOS now, and practical value is very high.
Description of drawings
Fig. 1 is the generalized section of transistor preferred embodiment;
Fig. 2 is the making flow chart of transistor preferred embodiment;
Fig. 3 makes the generalized section one of flow process for the transistor preferred embodiment;
Fig. 4 makes the generalized section two of flow process for the transistor preferred embodiment;
Fig. 5 makes the generalized section three of flow process for the transistor preferred embodiment;
Fig. 6 makes the generalized section four of flow process for the transistor preferred embodiment.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described.
At first, as shown in Figure 1, the three-dimensional multiple-gate transistor 10 of the high drive current of a preferred embodiment of the present invention includes a silicon base 12, a separator 13 and several gates 14.
This separator 13, (Buried Oxide BOX), is formed at this silicon base 12 surfaces, is an insulating barrier, can reduce the parasitic capacitance phenomenon to imbed oxide layer.
This each gate 14 comprises a silicon fin (Si-fin) 22 respectively, is vertically installed in these insulating barrier 14 surfaces (above genus fin-shaped half field effect electric crystal structure); One SiGe channel layer (SiGechannel) 24 is formed at this silicon fin 22 outsides; One high-k (Hi-K) brake-pole dielectric layer 26 is formed at this SiGe channel layer 24 outsides; One protective layer 28 through silicon nitride (SiNx) material of heat treatment (Thermal treatment), is formed at this silicon fin 22, SiGe channel layer 24 and high-k brake-pole dielectric layer 26 tops.
In addition, the three-dimensional multiple-gate transistor 10 of this high drive current also includes one first hard mask layer 15, and this layer is a silicon dioxide, and etching is formed at this protective layer 28 surfaces; One gate metal level 16 is formed at respectively this gate 14 and separator 13 surfaces.
As shown in Figure 2, the method for making of the three-dimensional multiple-gate transistor 10 of this high drive current is as follows:
The 4th step 140 is heat-treated, and make these each silicon fin 22 lateral walls form a sacrificial oxide layer 31 respectively: this heat treated mode is a thermal oxidation; This sacrificial oxide layer 31 is a silicon dioxide.Referring to Fig. 4.
The 5th step 150 removes this each sacrificial oxide layer 30: utilize dilution hydrofluoric acid (Diluted HF, DHF) or buffer oxide layer etchant (HF+NH4F BOE) removes this each sacrificial oxide layer 31, forms depression position 32 in silicon fin 22 outsides.Referring to Fig. 5.
The 6th step 160 forms a SiGe channel layer 24 in the depression position 32 in these each silicon fin 22 outsides: form SiGe channel layer 24 with building crystal to grow method (Epi-growth) in this position 32 of respectively caving in.Referring to Fig. 6.
The 7th step 170, form a high-k brake-pole dielectric layer 26 in these each SiGe channel layer 24 outsides: utilize atomic deposition technique (Atomic Layer Deposition, ALD) or chemical vapor deposition (CVD) form high-k brake-pole dielectric layer 26 in each SiGe channel layer 24 outside.
The 8th step 180, deposition gate metal level 16 is in this each gate 14 and separator 13 surfaces.
The 9th step 190 is in these gate metal level 16 surface etchings, patterning: also utilize chemical vapour deposition technique and reactive ion etching technique to carry out etching, be patterned into etch stop layer.
Aforementioned etch stop layer mainly is in order to control etching degree.
With this, the three-dimensional multiple-gate transistor 10 of this high drive current of the present invention can obtain following characteristic at least:
The three-dimensional multiple-gate transistor 10 of this high drive current not only meet semiconductor industry not tomorrow three-dimensional, multiple-gate structural development trend, and obtain to reduce effects such as consumed power, the energy service efficiency that promotes portable device and battery life.And high-k (Hi-K)/metal gate will occupy the main flow less than the CMOS technology of 65nm.In addition; respectively this SiGe channel layer 24 has high relatively drive current flowability compared to the silicon passage of existing N/PMOS, and respectively the protective layer 28 of this gate 14 can use dilute hydrofluoric acid or buffer oxide layer etchant to remove protection silicon fin 22 in sacrificial oxide layer 30 and the gate metal level etching process in processing procedure.
As from the foregoing, three-dimensional multiple-gate transistor of high drive current provided by the present invention and method for making thereof, its not only meet semiconductor industry not tomorrow three-dimensional, multiple-gate structural development trend, and, the brand-new 3-dimensional metal gate structure that comprises SiGe channel layer and high-k brake-pole dielectric layer can have higher drive current flowability compared to the silicon passage that has N/PMOS now, and practical value is very high.
Claims (10)
1. the one kind high three-dimensional multiple-gate transistor of drive current is characterized in that: comprise
One silicon base;
One separator is formed at this silicon base surface;
Several gates are vertically installed in this surface of insulating layer; Each gate comprises a silicon fin respectively; One SiGe channel layer is formed at this silicon fin outside; One high-k brake-pole dielectric layer is formed at this SiGe channel layer outside; One protective layer through heat treatment, is formed at this silicon fin, SiGe channel layer and high-k brake-pole dielectric layer top.
2. the three-dimensional multiple-gate transistor of high drive current as claimed in claim 1, it is characterized in that: described isolation series of strata are imbedded oxide layer.
3. the three-dimensional multiple-gate transistor of high drive current as claimed in claim 1, it is characterized in that: described protective layer adopts the silicon nitride material.
4. the three-dimensional multiple-gate transistor of high drive current as claimed in claim 1 is characterized in that: also include one first hard mask layer, be formed at described protective layer surface.
5. the three-dimensional multiple-gate transistor of high drive current as claimed in claim 1, it is characterized in that: described each gate and insulation surface also are formed with a metal gate.
6. the transistorized method for making of the three-dimensional multiple-gate of one kind high drive current is characterized in that: include following steps at least:
A) provide a fin formula half field effect electric crystal structure, several silicon fin that this fin formula half field effect electric crystal structure comprises a silicon base, is formed at a separator on silicon base surface and is vertically installed in surface of insulating layer;
B) deposition one protective layer is in the silicon fin top;
C) form one first hard mask layer in protective layer surface deposition and etching, patterning;
D) heat-treat, make this each silicon fin lateral wall form a sacrificial oxide layer respectively;
E) remove this each sacrificial oxide layer;
F) form a SiGe channel layer in this each silicon fin outside;
G) form a high-k brake-pole dielectric layer in this each SiGe channel layer outside;
H) deposition one gate metal level is in this each gate and insulation surface;
I) with this gate metal level etching, patterning.
7. as the transistorized method for making of the three-dimensional multiple-gate of high drive current as described in the claim 6, it is characterized in that: in the described step c), the mode of described deposition is to utilize chemical vapour deposition technique; The mode of described etching, patterning is to utilize the reactive ion etching machine to carry out etching, be patterned into etch stop layer.
8. as the transistorized method for making of the three-dimensional multiple-gate of high drive current as described in the claim 6, it is characterized in that: in the described step d), described heat treated mode is a thermal oxidation, and this sacrificial oxide layer is a silicon dioxide.
9. as the transistorized method for making of the three-dimensional multiple-gate of high drive current as described in the claim 6, it is characterized in that: in the described step e), be to utilize the hydrofluoric acid or the buffer oxide layer etchant of dilution to remove described each sacrificial oxide layer.
10. as the transistorized method for making of the three-dimensional multiple-gate of high drive current as described in the claim 6, it is characterized in that: in the described step f), be to form SiGe channel layer in this each silicon fin outside with the building crystal to grow method.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103367432A (en) * | 2012-03-31 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Multi-grid field effect transistor and manufacturing method thereof |
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| US6458662B1 (en) * | 2001-04-04 | 2002-10-01 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed |
| CN1534745A (en) * | 2003-03-26 | 2004-10-06 | ̨������·����ɷ�����˾ | Structure of multi grid transistor and its manufacturing method |
| US20040195624A1 (en) * | 2003-04-04 | 2004-10-07 | National Taiwan University | Strained silicon fin field effect transistor |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN100517619C (en) * | 2005-10-27 | 2009-07-22 | 国际商业机器公司 | Structure and method of fabricating finfet with buried channel |
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Patent Citations (5)
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| US6458662B1 (en) * | 2001-04-04 | 2002-10-01 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed |
| CN1534745A (en) * | 2003-03-26 | 2004-10-06 | ̨������·����ɷ�����˾ | Structure of multi grid transistor and its manufacturing method |
| US20040195624A1 (en) * | 2003-04-04 | 2004-10-07 | National Taiwan University | Strained silicon fin field effect transistor |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN100517619C (en) * | 2005-10-27 | 2009-07-22 | 国际商业机器公司 | Structure and method of fabricating finfet with buried channel |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367432A (en) * | 2012-03-31 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Multi-grid field effect transistor and manufacturing method thereof |
| CN103367432B (en) * | 2012-03-31 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | Multiple gate field effect transistor and manufacture method thereof |
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Application publication date: 20111019 |