CN102231284A - Method for reducing power consumption of flash memory chip data writing operation - Google Patents
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Abstract
A method for reducing power consumption of flash memory chip data writing operation. Through a precoding processing, user data is changed, and corresponding precoding data redundancy is introduced; then the precoding is output to carry out an error correction code coding operation to generate corresponding error correcting code redundancy, so as to reduce power consumption of corresponding flash memory data writing; at last, the precoding is output and written into the flash memory chip together with the error correcting code redundancy. A flash memory chip reliability scope and a corresponding required error correcting code redundancy amount are given; when an estimated or detected flash memory chip reliability falls into the given flash memory chip reliability scope, a error correcting code redundancy amount can be obtained, so as to adjust error correcting code coding operation dynamically. Meanwhile, the required error correcting code redundancy amount is subtracted from a fixed redundancy storage space contained in a page itself, so as to obtain a precoding redundancy amount to adjust precoding operation dynamically. The power consumption of flash memory chip data writing operation is reduced effectively by utilizing a characteristic that the power consumption of flash memory chip data writing operation is directly related to the content of the written data.
Description
Technical field
The invention belongs to storer and Computer Architecture technical field, particularly a kind of method that reduces flash chip data write operation power consumption.
Background technology
As the solid-state non-volatile data storing technology of unique main flow, flash memory has become a ring with the fastest developing speed in the global semiconductor industrial system.Market intelligence showed in 2010, and the market of flash memory products has been broken through 20,000,000,000 dollars.Use flash memory can improve 10 to 100 times than the speed of conventional hard as the solid-state memory system of storage medium.Except the advantage on the speed, owing to do not have physical construction fully, solid-state memory system is all having significant advantage aspect anti-seismic performance, heating power consumption, use noise and the volume weight.Solid-state memory system mainly comprises a solid-state memory system controller and a plurality of flash chip.
Floating gate transistor is the essential information storage unit of flash chip.The threshold voltage of floating gate transistor can enter floating boom by the electronics of injection some and change.Therefore, by accurate control to number of electrons in the floating boom, each storage unit, promptly floating gate transistor can store a plurality of bit informations.Accurately the process of number of electrons is commonly called programming in the control floating boom.Before each storage unit can be programmed, all electronics in its floating boom must be removed, thereby it is minimum to make that its threshold voltage is changed to, and this process is called as wipes.In the process to information memory cell programming, industry uses a kind of method of gradual " programming-verification-programming again " with the accurate control of realization to number of electrons in the floating boom usually.Because flash chip uses the method for gradual " programming-verification-programming again " to finish data write operation, and each takes turns " programming-verification " operation can cause a large amount of bit line charge/discharges, so the flash chip data write operation consumes relatively large energy, and the power consumption of whole flash chip data-storage system is determined by the data write operation power consumption basically, does not also solve the method that reduces this operation power consumption at present effectively.
Summary of the invention
In order to overcome the deficiency that above-mentioned prior art exists, the object of the present invention is to provide a kind of method that the flash chip data write power consumption that reduces, utilize the data of flash chip to write power consumption and the directly related characteristics of institute's write data content, reduced flash chip write operation power consumption very effectively.
In order to achieve the above object, the technical solution adopted in the present invention is:
A kind ofly reduce the method that the flash chip data write power consumption, when at first the solid-state memory system controller writes flash chip with every frame user data, every frame user data is carried out precoding processing earlier, this precoding processing is that this frame user data is decomposed into more than one data block, set precoding redundancy capacity size and error correcting code redundancy capacity size by the solid-state memory system controller again, this precoding redundancy capacity size is not more than default precoding amount of redundancy limit value, the fixedly redundant storage spatial content size that this error correcting code redundancy capacity size is not more than the flash chip page to be written is removed the value of precoding redundancy capacity size, subsequently to the encode coded data block of the precoding redundancy that obtains having precoding redundancy capacity size of each data block, the coded data block that then this is had the precoding redundancy carries out the error correcting code encoding operation, obtain having the coded data block of precoding redundancy and the error correcting code redundancy of error correcting code redundancy capacity size thereof like this, to have the coded data block of precoding redundancy and error correcting code redundancy thereof at last and write in the specified page in the flash chip, the redundant and error correcting code redundancy of precoding wherein writes in the fixedly redundant storage space of this page.
The method that described solid-state memory system controller is set precoding redundancy capacity size and error correcting code redundancy capacity size is: at first by the solid-state memory system controller flash chip reliability and error correcting code redundancy capacity mapping table are set, this flash chip reliability and interior each clauses and subclauses flash chip reliability scope and its corresponding error correcting code redundancy capacity value of error correcting code redundancy capacity mapping table for presetting, solid-state memory system controller drives flash chip reliability is derived module and is derived real-time flash chip reliability subsequently, solid-state memory system controller drives error correcting code redundancy capacity locating module contrasts the flash chip reliability scope in each clauses and subclauses in this flash chip reliability and flash chip reliability and the precoding redundancy capacity mapping table, if this flash chip reliability belongs to the flash chip reliability scope in one of them clauses and subclauses, the error correcting code redundancy capacity size that the pairing error correcting code redundancy capacity of flash chip reliability scope value in these clauses and subclauses is just set for the solid-state memory system controller, and the fixedly redundant storage spatial content size of precoding redundancy capacity size just to be of picked at random the be not more than flash chip page to be written is removed the value of error correcting code redundancy capacity size.
The described step that each data block is encoded is as follows:
Step 1: at first the value of the first variable storage unit of solid-state memory system controller setting precoding redundancy capacity size is 0, the value of setting the second variable storage unit of precoding redundancy capacity size simultaneously is 0, and the value of setting the ternary storage unit in addition is the maximal value of number of machines;
Step 2: the data of the precoding redundancy capacity size that each section of solid-state memory system controller control data piece is continuous are carried out the XOR binary arithmetic to obtain data block behind the XOR with the value of the first variable storage unit;
Step 3: the solid-state memory system controller writes the required power consumption of flash chip by the value that power consumption module derives the data block behind the XOR and the first variable storage unit, if required power consumption is less than the value of ternary storage unit, the value of ternary storage unit is become required power consumption number, and the value of the second variable storage unit is become the value of the first variable storage unit;
Step 4: after the solid-state memory system controller increases progressively 1 with the value of the first variable storage unit, if the value of the first variable storage unit is less than the big or small bit value power of 2 precoding redundancy capacity at this moment, return in the step 2 and carry out, if the value of the first variable storage unit enters in the step 5 and carries out more than or equal to the big or small bit value power of 2 precoding redundancy capacity at this moment;
Step 5: the value of the second variable storage unit of solid-state memory system controller precoding at this moment redundancy capacity size is as the precoding redundancy, and the data of the continuous precoding redundancy capacity size of each section of control data piece carry out the XOR binary arithmetic to obtain coded data block with the precoding redundancy, and coded data block combines the coded data block that forms the precoding redundancy that has precoding redundancy capacity size with the precoding redundancy.
The method of described solid-state memory system controller setting precoding redundancy capacity is that the arithmetic unit derivation of solid-state memory system controller is the logarithm of truth of a matter bit sequence change pattern count value with 2, and this logarithm value is precoding redundancy capacity size.
The described step that each data block is encoded can also be as follows:
Step 1: at first to set the value of the first variable storage unit be 1 to the solid-state memory system controller, and the value of setting the second variable storage unit of precoding redundancy capacity size simultaneously is 1, and the value of setting the ternary storage unit in addition is the maximal value of number of machines;
Step 2: the value that the solid-state memory system controller is set the first variable storage unit is the sequence number of bit sequence change pattern, selects the bit sequence change pattern of this sequence number that data block is carried out the sequence alter operation to obtain sequence data block after changing;
Step 3: the solid-state memory system controller by power consumption module derive with sequence after changing the value of data block and the first variable storage unit write the required power consumption of flash chip, if required power consumption is less than the value of ternary storage unit, the value of ternary storage unit is become required power consumption number, and the value of the second variable storage unit is become the value of the first variable storage unit;
Step 4: after the solid-state memory system controller increases progressively 1 with the value of the first variable storage unit, if the value of the first variable storage unit is less than the big or small bit value power of 2 precoding redundancy capacity at this moment, return in the step 2 and carry out, if the value of the first variable storage unit enters in the step 5 and carries out more than or equal to the big or small bit value power of 2 precoding redundancy capacity at this moment;
Step 5: the value of the second variable storage unit of solid-state memory system controller precoding at this moment redundancy capacity size is as the precoding redundancy, the value of setting the second variable storage unit is the sequence number of bit sequence change pattern, select the bit sequence change pattern of this sequence number that data block is carried out the sequence alter operation to obtain coded data block, coded data block combines the coded data block that forms the precoding redundancy that has precoding redundancy capacity size with the precoding redundancy.
Change user data and introduce default data redundancy by precoding processing, its purpose writes power consumption for reducing corresponding flash data, then this precoding output is carried out the error correcting code encoding operation to produce corresponding error correcting code redundancy, at last precoding output is write a certain page in the flash chip with the error correcting code redundancy.A given above flash chip reliability scope and corresponding required error correcting code amount of redundancy, when the flash chip reliability of estimating or detect gained falls in a certain given reliability scope, can obtain corresponding required error correcting code amount of redundancy, dynamically adjust the error correcting code encoding operation with this.Simultaneously, deduct required error correcting code amount of redundancy in the contained fixedly redundant storage space of each page itself, the precoding amount of redundancy that can obtain being allowed is dynamically adjusted pre-encode operation with this.
Description of drawings
Accompanying drawing is a work structuring principle schematic of the present invention.
Embodiment
The present invention will be described in more detail below in conjunction with accompanying drawing.
As shown in drawings, reduce the method that the flash chip data write power consumption, when at first the solid-state memory system controller writes flash chip with every frame user data, every frame user data is carried out precoding processing earlier, this precoding processing is that this frame user data is decomposed into more than one data block, set precoding redundancy capacity size and error correcting code redundancy capacity size by the solid-state memory system controller again, this precoding redundancy capacity size is not more than default precoding amount of redundancy limit value, the fixedly redundant storage spatial content size that this error correcting code redundancy capacity size is not more than the flash chip page to be written is removed the value of precoding redundancy capacity size, subsequently to the encode coded data block of the precoding redundancy that obtains having precoding redundancy capacity size of each data block, the coded data block that then this is had the precoding redundancy carries out the error correcting code encoding operation, obtain having the coded data block of precoding redundancy and the error correcting code redundancy of error correcting code redundancy capacity size thereof like this, to have the coded data block of precoding redundancy and error correcting code redundancy thereof at last and write in the specified page in the flash chip, the redundant and error correcting code redundancy of precoding wherein writes in the fixedly redundant storage space of this page.
Described solid-state memory system controller is set the method for precoding redundancy capacity size and error correcting code redundancy capacity size at first by the solid-state memory system controller flash chip reliability and error correcting code redundancy capacity mapping table being set, this flash chip reliability and interior each clauses and subclauses flash chip reliability scope and its corresponding error correcting code redundancy capacity value of error correcting code redundancy capacity mapping table for presetting, solid-state memory system controller drives flash chip reliability is derived module and is derived real-time flash chip reliability subsequently, solid-state memory system controller drives error correcting code redundancy capacity locating module contrasts the flash chip reliability scope in each clauses and subclauses in this flash chip reliability and flash chip reliability and the precoding redundancy capacity mapping table, if this flash chip reliability belongs to the flash chip reliability scope in one of them clauses and subclauses, the error correcting code redundancy capacity size that the pairing error correcting code redundancy capacity of flash chip reliability scope value in these clauses and subclauses is just set for the solid-state memory system controller, and the fixedly redundant storage spatial content size of precoding redundancy capacity size just to be of picked at random the be not more than flash chip page to be written is removed the value of error correcting code redundancy capacity size.
The described step that each data block is encoded is as follows:
Step 1: at first the value of the first variable storage unit of solid-state memory system controller setting precoding redundancy capacity size is 0, the value of setting the second variable storage unit of precoding redundancy capacity size simultaneously is 0, and the value of setting the ternary storage unit in addition is the maximal value of number of machines;
Step 2: the data of the precoding redundancy capacity size that each section of solid-state memory system controller control data piece is continuous are carried out the XOR binary arithmetic to obtain data block behind the XOR with the value of the first variable storage unit;
Step 3: the solid-state memory system controller writes the required power consumption of flash chip by the value that power consumption module derives the data block behind the XOR and the first variable storage unit, if required power consumption is less than the value of ternary storage unit, the value of ternary storage unit is become required power consumption number, and the value of the second variable storage unit is become the value of the first variable storage unit;
Step 4: after the solid-state memory system controller increases progressively 1 with the value of the first variable storage unit, if the value of the first variable storage unit is less than the big or small bit value power of 2 precoding redundancy capacity at this moment, return in the step 2 and carry out, if the value of the first variable storage unit enters in the step 5 and carries out more than or equal to the big or small bit value power of 2 precoding redundancy capacity at this moment;
Step 5: the value of the second variable storage unit of solid-state memory system controller precoding at this moment redundancy capacity size is as the precoding redundancy, and the data of the continuous precoding redundancy capacity size of each section of control data piece carry out the XOR binary arithmetic to obtain coded data block with the precoding redundancy, and coded data block combines the coded data block that forms the precoding redundancy that has precoding redundancy capacity size with the precoding redundancy.
The method of described solid-state memory system controller setting precoding redundancy capacity is that the arithmetic unit derivation of solid-state memory system controller is the logarithm of truth of a matter bit sequence change pattern count value with 2, and this logarithm value is precoding redundancy capacity size.
The described step that each data block is encoded can also be as follows:
Step 1: at first to set the value of the first variable storage unit be 1 to the solid-state memory system controller, and the value of setting the second variable storage unit of precoding redundancy capacity size simultaneously is 1, and the value of setting the ternary storage unit in addition is the maximal value of number of machines;
Step 2: the value that the solid-state memory system controller is set the first variable storage unit is the sequence number of bit sequence change pattern, selects the bit sequence change pattern of this sequence number that data block is carried out the sequence alter operation to obtain sequence data block after changing;
Step 3: the solid-state memory system controller by power consumption module derive with sequence after changing the value of data block and the first variable storage unit write the required power consumption of flash chip, if required power consumption is less than the value of ternary storage unit, the value of ternary storage unit is become required power consumption number, and the value of the second variable storage unit is become the value of the first variable storage unit;
Step 4: after the solid-state memory system controller increases progressively 1 with the value of the first variable storage unit, if the value of the first variable storage unit is less than the big or small bit value power of 2 precoding redundancy capacity at this moment, return in the step 2 and carry out, if the value of the first variable storage unit enters in the step 5 and carries out more than or equal to the big or small bit value power of 2 precoding redundancy capacity at this moment;
Step 5: the value of the second variable storage unit of solid-state memory system controller precoding at this moment redundancy capacity size is as the precoding redundancy, the value of setting the second variable storage unit is the sequence number of bit sequence change pattern, select the bit sequence change pattern of this sequence number that data block is carried out the sequence alter operation to obtain coded data block, coded data block combines the coded data block that forms the precoding redundancy that has precoding redundancy capacity size with the precoding redundancy.
Claims (5)
1. one kind is reduced the method that the flash chip data write power consumption, it is characterized in that: when at first the solid-state memory system controller writes flash chip with every frame user data, every frame user data is carried out precoding processing earlier, this precoding processing is that this frame user data is decomposed into more than one data block, set precoding redundancy capacity size and error correcting code redundancy capacity size by the solid-state memory system controller again, this precoding redundancy capacity size is not more than default precoding amount of redundancy limit value, the fixedly redundant storage spatial content size that this error correcting code redundancy capacity size is not more than the flash chip page to be written is removed the value of precoding redundancy capacity size, subsequently to the encode coded data block of the precoding redundancy that obtains having precoding redundancy capacity size of each data block, the coded data block that then this is had the precoding redundancy carries out the error correcting code encoding operation, obtain having the coded data block of precoding redundancy and the error correcting code redundancy of error correcting code redundancy capacity size thereof like this, to have the coded data block of precoding redundancy and error correcting code redundancy thereof at last and write in the specified page in the flash chip, the redundant and error correcting code redundancy of precoding wherein writes in the fixedly redundant storage space of this page.
2. reduction flash chip data according to claim 1 write the method for power consumption, it is characterized in that: described solid-state memory system controller is set the method for precoding redundancy capacity size and error correcting code redundancy capacity size at first by the solid-state memory system controller flash chip reliability and error correcting code redundancy capacity mapping table being set, this flash chip reliability and interior each clauses and subclauses flash chip reliability scope and its corresponding error correcting code redundancy capacity value of error correcting code redundancy capacity mapping table for presetting, solid-state memory system controller drives flash chip reliability is derived module and is derived real-time flash chip reliability subsequently, solid-state memory system controller drives error correcting code redundancy capacity locating module contrasts the flash chip reliability scope in each clauses and subclauses in this flash chip reliability and flash chip reliability and the precoding redundancy capacity mapping table, if this flash chip reliability belongs to the flash chip reliability scope in one of them clauses and subclauses, the error correcting code redundancy capacity size that the pairing error correcting code redundancy capacity of flash chip reliability scope value in these clauses and subclauses is just set for the solid-state memory system controller, and the fixedly redundant storage spatial content size of precoding redundancy capacity size just to be of picked at random the be not more than flash chip page to be written is removed the value of error correcting code redundancy capacity size.
3. write the method for power consumption according to claim 1 or the described reduction flash chip of claim 2 data, it is characterized in that: the described step that each data block is encoded is as follows:
Step 1: solid-state memory system controller at first, the value of setting the first variable storage unit of precoding redundancy capacity size is 0, the value of setting the second variable storage unit of precoding redundancy capacity size simultaneously is 0, and the value of setting the ternary storage unit in addition is the maximal value of number of machines;
Step 2: the data of the precoding redundancy capacity size that each section of solid-state memory system controller control data piece is continuous are carried out the XOR binary arithmetic to obtain data block behind the XOR with the value of the first variable storage unit;
Step 3: the solid-state memory system controller writes the required power consumption of flash chip by the value that power consumption module derives the data block behind the XOR and the first variable storage unit, if required power consumption is less than the value of ternary storage unit, the value of ternary storage unit is become required power consumption number, and the value of the second variable storage unit is become the value of the first variable storage unit;
Step 4: after the solid-state memory system controller increases progressively 1 with the value of the first variable storage unit, if the value of the first variable storage unit is less than the big or small bit value power of 2 precoding redundancy capacity at this moment, return in the step 2 and carry out, if the value of the first variable storage unit enters in the step 5 and carries out more than or equal to the big or small bit value power of 2 precoding redundancy capacity at this moment;
Step 5: the value of the second variable storage unit of solid-state memory system controller precoding at this moment redundancy capacity size is as the precoding redundancy, and the data of the continuous precoding redundancy capacity size of each section of control data piece carry out the XOR binary arithmetic to obtain coded data block with the precoding redundancy, and coded data block combines the coded data block that forms the precoding redundancy that has precoding redundancy capacity size with the precoding redundancy.
4. reduction flash chip data according to claim 1 write the method for power consumption, it is characterized in that: the method for described solid-state memory system controller setting precoding redundancy capacity is that the arithmetic unit derivation of solid-state memory system controller is the logarithm of truth of a matter bit sequence change pattern count value with 2, and this logarithm value is precoding redundancy capacity size.
5. reduction flash chip data according to claim 4 write the method for power consumption, it is characterized in that: the described step that each data block is encoded can also be as follows:
Step 1: at first to set the value of the first variable storage unit be 1 to the solid-state memory system controller, and the value of setting the second variable storage unit of precoding redundancy capacity size simultaneously is 1, and the value of setting the ternary storage unit in addition is the maximal value of number of machines;
Step 2: the value that the solid-state memory system controller is set the first variable storage unit is the sequence number of bit sequence change pattern, selects the bit sequence change pattern of this sequence number that data block is carried out the sequence alter operation to obtain sequence data block after changing;
Step 3: the solid-state memory system controller by power consumption module derive with sequence after changing the value of data block and the first variable storage unit write the required power consumption of flash chip, if required power consumption is less than the value of ternary storage unit, the value of ternary storage unit is become required power consumption number, and the value of the second variable storage unit is become the value of the first variable storage unit;
Step 4: after the solid-state memory system controller increases progressively 1 with the value of the first variable storage unit, if the value of the first variable storage unit is less than the big or small bit value power of 2 precoding redundancy capacity at this moment, return in the step 2 and carry out, if the value of the first variable storage unit enters in the step 5 and carries out more than or equal to the big or small bit value power of 2 precoding redundancy capacity at this moment;
Step 5: the value of the second variable storage unit of solid-state memory system controller precoding at this moment redundancy capacity size is as the precoding redundancy, the value of setting the second variable storage unit is the sequence number of bit sequence change pattern, select the bit sequence change pattern of this sequence number that data block is carried out the sequence alter operation to obtain coded data block, coded data block combines the coded data block that forms the precoding redundancy that has precoding redundancy capacity size with the precoding redundancy.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112187412A (en) * | 2020-10-10 | 2021-01-05 | 中车青岛四方机车车辆股份有限公司 | Data transmission method and related device |
| CN116909937A (en) * | 2023-05-11 | 2023-10-20 | 深圳三地一芯电子股份有限公司 | Flash memory capacity optimization method, device, equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006013529A1 (en) * | 2004-08-02 | 2006-02-09 | Koninklijke Philips Electronics N.V. | Data storage and replay apparatus |
| JP2009211209A (en) * | 2008-02-29 | 2009-09-17 | Toshiba Corp | Semiconductor storage device, its control method, and error correction system |
| CN101964205A (en) * | 2010-09-17 | 2011-02-02 | 记忆科技(深圳)有限公司 | ECC (Error Correction Code) module dynamic multiplexing system and method based on solid state disk |
-
2011
- 2011-06-02 CN CN201110146489XA patent/CN102231284A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006013529A1 (en) * | 2004-08-02 | 2006-02-09 | Koninklijke Philips Electronics N.V. | Data storage and replay apparatus |
| JP2009211209A (en) * | 2008-02-29 | 2009-09-17 | Toshiba Corp | Semiconductor storage device, its control method, and error correction system |
| CN101964205A (en) * | 2010-09-17 | 2011-02-02 | 记忆科技(深圳)有限公司 | ECC (Error Correction Code) module dynamic multiplexing system and method based on solid state disk |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112187412A (en) * | 2020-10-10 | 2021-01-05 | 中车青岛四方机车车辆股份有限公司 | Data transmission method and related device |
| CN112187412B (en) * | 2020-10-10 | 2022-11-15 | 中车青岛四方机车车辆股份有限公司 | Data transmission method and related device |
| CN116909937A (en) * | 2023-05-11 | 2023-10-20 | 深圳三地一芯电子股份有限公司 | Flash memory capacity optimization method, device, equipment and storage medium |
| CN116909937B (en) * | 2023-05-11 | 2024-02-23 | 深圳三地一芯电子股份有限公司 | Flash memory capacity optimization method, device, equipment and storage medium |
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