CN102246307A - 具有增大的击穿电压特性的基于沟槽的功率半导体器件 - Google Patents

具有增大的击穿电压特性的基于沟槽的功率半导体器件 Download PDF

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CN102246307A
CN102246307A CN2009801492000A CN200980149200A CN102246307A CN 102246307 A CN102246307 A CN 102246307A CN 2009801492000 A CN2009801492000 A CN 2009801492000A CN 200980149200 A CN200980149200 A CN 200980149200A CN 102246307 A CN102246307 A CN 102246307A
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CN102246307B (zh
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约瑟夫·A·叶季纳科
丹尼尔·卡拉菲特
迪安·E·普罗布斯特
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Fairchild Semiconductor Corp
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Abstract

本发明公开了具有提供增大的击穿电压和其他益处的特征的示例性功率半导体器件。

Description

具有增大的击穿电压特性的基于沟槽的功率半导体器件
相关申请的引用
本申请要求于2008年12月8日提交的美国临时专利申请No.61/120818的权益，将其全部内容结合于此供参考。
背景技术
示例性功率半导体器件(功率半导体装置，power semiconductordevice)包括平面栅MOSFET晶体管、垂直栅MOSFET晶体管、绝缘栅双极晶体管(IGBT)、整流管和同步整流管。这些器件的槽栅多样性的典型实施包括在半导体芯片(裸芯片，die)顶面上形成的沟槽阵列，其中每个沟槽用屏蔽电极(shield electrode)和/或栅电极填充，这取决于功率器件的类型。沟槽定义平台(mesa)的对应阵列，每个平台布置(设置，dispose)在相邻沟槽之间。取决于在芯片上实现的器件，各种电极和/或掺杂区布置在平台的顶部。每个平台和它的相邻沟槽实现该器件的小实例(instance)，并且这些小实例并联耦接在一起从而提供整个功率半导体器件。整个器件具有其中期望电流流过该器件的ON状态(连通状态)、其中电流在器件中基本被阻断的OFF状态(断开状态)，以及其中由于在器件的导电电极之间施加过大断开电压导致的不期望电流流动的击穿状态。引发击穿的电压称为击穿电压(breakdown voltage)。每个平台和它的相邻沟槽被构造成提供一组期望的ON状态特性和击穿电压。在平台和沟槽的设计中，在实现良好ON状态特性、高击穿电压和改善的开关特性之间存在各种权衡(tradeoff)。
典型的功率半导体芯片具有其中布置有实现器件的平台和沟槽阵列的有源区、围绕该有源区的场终止区(field termination area)，以及其中可以提供互连和沟道截止(channel stop)的无源区(inactive area)。场终止区使有源区周围的电场最小化，并且不用于传导电流。理想地，人们希望器件的击穿电压由与有源区相关的击穿过程确定。然而，存在在显著较低电压下能够在场终止区和无源区中发生的各种击穿过程。这些击穿过程可称为被动击穿过程。
现有技术中为了设计具有比有源区更高的击穿电压的场终止区已经做出了许多努力。然而，这样的现有技术设计常常没有达到该目的，经常需要增加总芯片面积和芯片成本的折衷。
发明内容
本发明的发明人发现了基于沟槽的功率器件中寄生击穿条件可能首先发生的若干位置。本申请提供了对抗这些击穿条件并增大击穿电压的新颖性和创造性特征。
本文中描述的本发明示例性实施方式的各个方面可以单独使用或以任意组合使用。
附图说明
图1示出了包括根据本发明的若干特征的一种示例性半导体芯片的顶视图。
图2示出了根据本发明的图1的示例性半导体芯片的左上角的放大视图。
图3示出了根据本发明的图1的示例性半导体芯片的左侧的一部分的放大视图。
图4和图5示出了根据本发明的图1的示例性半导体芯片的一部分的第一剖面图和其在图5中的放大图。
图6示出了根据本发明的图1的示例性半导体芯片的变形的一部分的放大剖面图。
图7-14示出了根据本发明的图1的示例性半导体芯片及其可能的变形的各种放大剖面图。
图15示出了包括根据本发明的若干特征的另一种示例性半导体芯片的顶视图。
图16-19示出了根据本发明的图15的示例性半导体芯片及其可能的变形的各种放大剖面图。
图20示出了包括根据本发明的若干特征的另一种示例性半导体芯片的顶视图。
图21-29示出了根据本发明的图20的示例性半导体芯片及其可能的变形的各种放大剖面图。
图30示出包括根据本发明的若干特征的另一种示例性半导体芯片的顶视图。
图31示出了根据本发明的图30的示例性半导体芯片的放大剖面图。
图32-34示出了根据本发明的包括沟槽屏蔽肖特基势垒二极管器件(trench-shielded Schottky barrier diode device)的示例性半导体芯片的各种剖面图。
具体实施方式
在下文中将参考其中示出了本发明的示例性实施方式的附图更充分地描述根据本发明的技术。然而，本发明可以以不同形式具体体现，并且不应该解释为限于本文中例举的这些实施方式。相反，提供这些实施方式以使本申请公开内容充分完整，并向本领域技术人员充分传达本发明的范围。在附图中，为了清楚，可能夸大了层和区域的厚度。使用相同的标号来指代整个说明书中的相同元件。这些元件对于不同的实施方式可以具有不同的相互关系和不同的位置。
还应理解，当一个层称为在另一个层或衬底“上”时，它能够直接在其他层或衬底上，或者也可以存在插入层。还应理解，当一个元件例如层、区域或衬底称为在另一元件“上”，“连接至”、“电连接至”、“耦接至”或“电耦接至”另一元件时，它能够直接在其他元件上、连接或耦合至其他元件，或可以存在一个或更多插入元件。相反，当一个元件称为“直接在另一元件上”、“直接连接至”或“直接耦接至”另一元件或层时，没有插入元件或层存在。可以理解，本申请的权利要求可以修改为引述本说明书中描述的或者附图中示出的示例性关系，其支持由原始申请提供。本文中使用的术语“和/或”包括相关例举项目中的一个或多个的任意和全部组合。
本文中使用的术语仅用于本发明的举例说明的目的，而不应解释为限制本发明的含义或范围。如在本说明书中使用的，除非根据上下文明确表示特定情形，单数形式可以包括复数形式。同样，在本说明书中使用的表达“包含”和/或“包括”既不限定提及的形状、数量、步骤、行为、操作、构件、元件和/或这些的组，也不排除存在或添加一个或多个其他其他不同的形状、数量、步骤、行为、操作、构件、元件和/或这些的组，或添加这些。空间相关术语，例如“在上方”、“高于”、“较高”、“在下方”、“在下面”、“低于”、“较低”等等，可以在本文中使用，用于方便描述以描述如图中所示的一个元件或特征相对于一个元件或特征的关系。应当理解，这些空间相关术语用于涵盖除了图中示出的定向之外，在使用或操作中器件的不同取向。例如，如果图中器件翻转，那么描述为“低于”其他元件或特征或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将会定向为“在其他元件或特征上面”或“高于”其他元件或特征。因此，示例性术语“高于”可能涵盖高于和低于两种定向。
如本文使用的，术语例如“第一”、“第二”等用来描述各种构件、组件、区域、层和/或部分。然而，很明显，构件、组件、区域、层和/或部分不应由这些术语限定。这些术语仅用于区分一个构件、组件、区域、层或部分与另一构件、组件、区域、层或部分。因此，将要描述的第一构件、组件、区域、层或部分也可指第二构件、组件、区域、层或部分，而不背离本发明的范畴。
图1示出了包括根据本发明的若干特征的示例性半导体器件100的顶视图。器件100包括位于在芯片中部的有源器件区(装置区，device region)120。不失一般性，器件区120可实现一个垂直的、沟槽屏蔽的功率MOSFET器件。如下面更详细描述和示出的，该示例性MOSFET器件包括与平台(mesa)阵列交错(interleave)的沟槽阵列、布置在沟槽底部中的绝缘屏蔽电极(shield electrode)、布置在屏蔽电极上方的沟槽中的绝缘栅电极(gate electrode)、布置在平台中的源极区(source region)、布置在源极区上的源电极(source electrode)、以及布置在半导体器件背侧处的漏电极(drain electrode)。器件100进一步包括布置在器件区120上方并电耦接至源电极的源极金属层110(也称为导电层110)、以及布置在导电层110上方并与其电耦接且又电耦接至该功率MOSFET器件的源极区的源极焊盘(源极垫，source pad)111。源极焊盘111适合接收外部连接，例如提供源极电位的焊线(wire bond)或焊料凸点(solder bump)，并在每侧上可以具有150微米的尺寸。
在器件区120左右侧的每侧上，器件100进一步包括与布置在沟槽中的栅电极和屏蔽电极形成电接触的连接区(connection region)150。在每个连接区中，一条导电材料，称为栅极浇道(gate runner)，平行于器件区120的侧面布置并与其隔开。栅极浇道与沟槽中栅电极电接触，但与在沟槽之间交错的平台电绝缘。每个栅极浇道电耦接至位于在芯片底部的栅极焊盘(栅极垫，gate pad)112。栅极焊盘112适合接收外部连接，例如提供栅极电位的焊线或焊料凸点。同样在每个连接区150中，另一条导电材料，称为屏蔽浇道(shield runner)，平行于栅极浇道布置并与其隔开。屏蔽浇道与沟槽中的屏蔽电极形成电接触，但与它覆盖的平台的部分电隔离。屏蔽浇道通过在芯片顶部处的源极导电层的延伸而电耦接至源极导电层，或者电耦接至屏蔽焊盘并使用外部连接。
沟道截断环(channel stopper)布置在芯片周边处或附近，并通过间隙与屏蔽浇道和器件区120的顶部部分隔开。沟道截断环是常规的，并且可以包括遮盖且接触一条掺杂半导体区的金属的隔离环(isolated ring)，其围绕芯片周边形成一个环。必需注意，芯片100不包括在这种间隙中通常出现的常规场终止结构(field termination structure)。
图2示出了芯片100左上角的放大图，而图3示出了沿该芯片左侧的一部分的放大图。以上特征在这些图中更清晰地看到。图2和图3为接下来将要讨论的芯片100的许多剖面提供参考点。
图4是包括有源器件区120和第一场终止区的芯片100的一部分的剖面图。芯片100包括N+掺杂半导体衬底102、布置在半导体衬底102上的一个或多个外延生长半导体n-型层104(“外延半导体层”)、布置在无源(inactive)和第一场终止区中的外延半导体层104上方的氧化物层106、布置在氧化物层106上方的介电层(dielectric layer)107、布置在无源区左边部分的介电层107上方的栅极浇道、以及布置在第一场终止区中的介电层107上方的导电层110(源极金属层110)。如在现有技术中已知的，半导体区可以用p-型掺杂剂掺杂为p-导电型(或“p-型”)区，或用n-型掺杂剂掺杂为n-导电型(或“n-型”)区。在器件区120中，器件100进一步包括布置在外延半导体层中的多个沟槽122，以及在沟槽122之间交错(交替)的半导体材料的多个平台130。介电层107的部分覆盖沟槽122的顶部，并且源极金属层110在有源器件区120上方延伸并与平台130形成接触。沟槽122和平台130的结构参考图5在下面进行描述。在第一终止区中，器件100进一步包括第一末端沟槽(first end trench)222、布置在第一末端沟槽222和器件区120的最左边沟槽122之间的第一末端平台(first end mesa)230、以及布置在第一末端沟槽222左边的第二末端平台238。
图5是图4中示出的第一场终止区和器件区120的放大剖面图。每个沟槽122都具有衬有介电层123的相对侧壁(opposing sidewall)、布置在沟槽底部附近的侧壁之间的屏蔽电极124、布置在屏蔽电极124上方的介电层125、以及布置在该介电层上方且在沟槽侧壁之间的栅电极126。每个平台130包括布置在与层104顶面相邻的外延半导体层104中的p-型阱134、布置在与两个相邻沟槽122和外延半导体层104顶面相邻的p-型阱134中的一对源极(n+型)区136、以及布置在p-型阱134下方的N漂移区(drift region)132。(本文中描述的p-型阱、p-型区和p-掺杂区可以称为“第一导电型阱区”或“第二导电型阱区”，取决于讨论的上下文或权利要求的上下文内容)。在平台130的中心形成小沟槽，以允许源极金属层110与源极区136形成电接触，以及与在增强p+掺杂的小区域135处的p-阱134形成电接触。电子电流垂直传导通过器件，从源极区136，通过与栅极氧化物123相邻的p-型阱134的反转区(inverted region)，进一步通过漂移区132，并向下直到N+衬底102和漏极接触，其中在正常操作条件下电流量通过沟槽122中的栅电极126上的电位进行调制。屏蔽电极124电耦接至源极金属层110和源极区136的电位，并屏蔽p-型阱免于高电场。
当设定栅电极126上的电位以将器件置于断开状态(例如，通常大约为零伏的电位)时，在其中漏极电位相对源极电位为非常高的击穿条件期间，大量电流仍可流动。在该击穿条件中，在每个平台130的区域中形成高电场，并且这种高电场产生雪崩载流子(avalanche carrier)(空穴和电子二者)。出现这种击穿条件的电压称为击穿电压。可以通过选择屏蔽氧化物厚度、平台宽度和N-漂移区132的掺杂以使N-漂移区132正常地耗尽电子而升高平台的击穿电压。这引起在断开状态条件期间的电场沿平台的中线更均匀地分布(例如，正方形电场轮廓)，由此减小峰值电场(并由此增大能够产生雪崩载流子的电压)。N-漂移区132耗尽电子的条件称为“电荷平衡条件(charge-balanced condition)”。当平台宽度和N-漂移区132的掺杂的乘积(product)在1×1011cm-2到1×1013cm-2范围内时，通常能够实现电荷平衡条件。
理想地，人们希望通过与平台130相关的击穿过程来确定击穿电压。然而，各种寄生击穿机制在较低电压下在器件的各种场终止区中发生，并由此将器件的总体击穿电压的值布置为低于由平台130中的击穿过程引起的值。一种这样的电位寄生机制能够在设计有现有技术的终止区的器件区120的最外沟槽中的介电层123的薄部分处出现。没有紧接它的平台130，这个薄介电层将会暴露于耦接至漏极电位的n-型外延层的电位，并且大电场能够横跨该薄介电层形成，这能够在相对低电压下引起发生击穿
根据本发明的一个特征通过在器件区120的有源沟槽122的阵列的任一侧上布置末端沟槽222解决这种寄生击穿机制。沟槽222具有衬有介电层223的相对侧壁、布置在沟槽底部附近的侧壁之间的屏蔽电极124、布置在屏蔽电极124上方的介电层125、以及布置在介电层上方且在沟槽侧壁之间的栅电极226。然而，不同于沟槽122的介电层123，如沿着栅电极226的深度测量时，介电层223沿着面对n-型外延层的侧壁的厚度比沿着面对器件区120的沟槽122的侧壁的厚度更厚。在图中通过标号227表示较厚区。较厚的电介质减小介电层中的电场，并由此增大它的击穿电压。沟槽222可以具有与每个沟槽122相同的宽度，并且栅电极226可以具有小于栅电极126的宽度。
以上沟槽222、122与平台238、230和130在用于图4的剖面线指示附近的图3的顶视图中指示。沟槽和平台的类似布置在器件区120的相反侧上存在，如通过图2的顶视图中的这些标号指示的。尽管沟槽222对结合沟槽122和平台130的阵列(在该阵列的任一侧上)(例如，阵列的顶部和底部)，但它们不环绕该阵列或者具有结合该阵列右侧和左侧的部分。即，在沟槽122和平台130的末端处没有垂直终止沟槽。(应当注意，沟槽122和平台130连续以在栅极浇道下方伸展(延展，run))。有关于此，器件100不具有布置在沟槽122末端处的p-掺杂区。这些特征中的每一个都减小场终止区的尺寸，并使有源区能够被增大和/或使芯片尺寸能够被减小。尽管以上构造用于提供MOSFET器件的器件区120，但它也能够应用于其他器件类型，例如IGBT器件和整流管，特别是其中存在上述电荷平衡条件的那些器件。
再次参考图5，作为本发明的另一特征，到末端沟槽222左边的宽平台238可以可选地具有布置在它表面的p-型区239，其紧接介电层223。P-型区239可以与任何电位直接去耦合，并以浮置状态(floating state)保持，或者可以电耦接至源极金属层110和源极电位(例如，它可以接地)。在任一情况下，区239减小宽平台238右上角周围的电场，从而消除作为寄生击穿机制的来源的这个区域。当电耦接至源极电位时，p-型区239进一步屏蔽电介质223免于区域227中的漏极电位。P-型区239可以在制造p-型阱134的相同工艺期间进行制造。
作为本发明的另一特征，到末端沟槽222右边的平台230可以构造为p-n二极管而不是MOSFET晶体管。为此，它可以包括p-型阱134和增强的p+掺杂区135，但没有源极区136。在器件区120的MOSFET晶体管的正常操作期间，该p-n二极管偏置于断开状态。平台230在宽平台238和用来从第一有源平台130缓冲宽平台238中的电位的第一有源平台130之间提供另外的间距。这使第一平台130的电特性能够与内平台130基本相同。
图6示出了根据本发明的图1的示例性半导体芯片的一种变形的一部分的放大剖面图。图6中的放大剖面中的特征与图5的放大剖面中示出的那些特征相同，其中增加了另外的沟槽220、介质层221和屏蔽电极124。末端沟槽220具有衬有介电层221的相对侧壁、以及布置在侧壁之间(优选从外延半导体层顶部到沟槽底部附近)的屏蔽电极224。屏蔽电极224电耦接至源极金属层110，或者能够保持电浮置(电浮动，electricallyfloating)以采取浮置电位(floating potential)。屏蔽电极224对末端沟槽(end trench)222和栅电极226提供漏极电位的另外屏蔽。平台230’限定在沟槽220和222之间。P-掺杂区239可以包括在沟槽220和222之间的平台230’中，或者省略。而且，可以使用布置在平台230’中并从沟槽222延伸到沟槽220的p-掺杂区234中。连同区域234，p-掺杂区239’可以包括在沟槽220的左侧上。一对沟槽220在阵列的任一侧(例如，阵列的顶部和底部)上结合沟槽122、222以及平台130、230、230’的阵列，但它们不环绕该阵列或者不具有结合该阵列右侧和左侧的部分。这个特征减小场终止区的尺寸，并且使有源区能够被增大和/或芯片尺寸能够被减小。尽管以上构造用于提供MOSFET器件的器件区120，但它也能够应用于其他器件类型，例如IGBT器件和整流管，特别是其中存在上面描述的电荷平衡条件的那些器件。
图7示出了沿图3中定义的切割线7-7，紧邻器件区120的连接区150中的上文提及的沟槽和平台的剖面图。薄量的氧化物层106布置在平台130和230的每一个上方，并且介电层107布置在栅电极126和226、以及下面的氧化物层106上方。可选的末端沟槽220、屏蔽电极221以及介电层221以虚轮廓示出。关于在图4和图5中示出的剖面，对于p-掺杂区239关于其毗邻元件的构造没有变化。
图8示出了沿图3中定义的切割线8-8，在栅极浇道下方的连接区150中的上文提及的沟槽和平台的剖面图。薄量的氧化物层106布置在平台130和230的每一个上方。栅电极126和226的顶部通过导电立管(导电焊线槽，conductive riser)126R电耦接在一起。导电立管126R通过氧化物106的薄部分与平台130、230电隔离。在典型的实施方式中，立管126R和栅电极126、226由相同材料例如多晶硅形成。在在先剖面中，立管126R被移除。金属栅极浇道在通过电介质107的岛分隔开的栅电极126和226上的位置处与立管126R形成接触。可省去这些岛。栅电极126和226在该点处在沟槽中终止。可选的末端沟槽220、屏蔽电极221和介电层221以虚线轮廓示出。关于图4和图5中示出的剖面，对于p-掺杂区239关于其毗邻元件的构造没有变化。
图9示出了沿图3中定义的切割线9-9，在栅极浇道和屏蔽浇道之间的连接区150中的上文提及的沟槽和平台的剖面图。仅屏蔽电极124和224存在于沟槽122和222中，其中氧化物层106覆盖它们以及平台130和230。
图10示出了沿图3中定义的切割线10-10，在连接区150中的沟槽122的剖面图，其中切割线10-10垂直于切割线4-4、7-7、8-8和9-9。栅电极126和屏蔽电极124布置在沟槽中，其中栅电极126具有与栅极浇道形成电接触的立管126R，并且其中屏蔽电极124具有与屏蔽浇道形成电接触的立管部分124R。介电层125在屏蔽电极124和栅电极126之间沿它们面对的水平维度布置，介电层125S在电极124和126之间沿它们面对的侧边维度布置，以及电介质的角落贴片(转角贴片，corner patch)125C布置在栅电极126的外侧角落和屏蔽电极124的内侧角落之间。屏蔽电极124具有邻近介电材料的贴片123C布置的外侧角落，以及邻近介电材料的侧面层123S布置的垂直侧。
曲率半径效应(radius of curvature effect)显著增加邻接屏蔽电极和栅电极126外侧角落的区域中的电场。介电贴片123C的厚度通常足以防止介电材料的击穿。然而，介电贴片125C和栅电极126周围的介电侧面层125S相对较薄，并且能够是用于末端沟槽222(在图8中示出)的击穿源。包括可选的屏蔽电极224和末端沟槽220屏蔽介电贴片125C和介电侧面层125S免于耦接至半导体层104的漏极电位，并由此减小介电贴片125C和介电侧面层125S中的电场。由于曲率半径效应引起的击穿的另一可能区域，特别是对于高电压器件，在屏蔽立管部分124R末端处的介电侧面层123S中存在，如图10中通过点“A”指示的。通过在介电侧面层123S上方并以距离L1超过沟槽122的末端延伸顶侧屏蔽浇道金属(其为导电引线(conductive trace))，能够显著减轻这种电位击穿。距离L1可以等于或大于沟槽122的深度。对于较浅的电压器件应用，在点“A”处的击穿可能性非常小，并且顶侧屏蔽浇道金属不在介电侧面层123S上方或超过沟槽122的末端延伸，如图中通过边缘“B”指示的。这种构造导致产生更薄的屏蔽浇道和更小的芯片。
图11示出了沿图3中定义的切割线11-11，在连接区150中的平台130的剖面图，其中切割线11-11垂直于切割线4-4、7-7、8-8和9-9。p-掺杂阱134和用于栅电极126的立管126R在图右边示出。典型地，p-掺杂阱134电耦接至源极和屏蔽的电位，但对于其中区域用于场终止区中的一些情况下可以处于浮动状态。p-掺杂阱134具有在栅极立管126R(其是导电引线)处或在其下方终止的的末端。供参考，栅电极126和屏蔽电极124的轮廓以短划线示出。存在由于曲率半径效应导致的在p-掺杂阱134末端处发生击穿的可能性。然而，布置在p-掺杂阱134任一侧上的栅电极126和屏蔽电极124通常消耗邻近阱134末端的n-掺杂平台130的部分，由此显著减小阱134末端周围的电位和电场。然而，减小量的电场仍在阱134的末端周围存在，并且能够以径向方式(即，曲率半径效应)在阱134的末端处集中。然而，利用图11中示出的构造，阱134的末端基本上由栅极立管126R屏蔽，并且基本上减小了在该区域末端的曲率半径效应。具体地，导电立管126R引导在阱134末端处的平台130中存在的电场远离阱134的末端并朝向它自身，由此减小电场的径向集中。如果阱134的末端延伸到导电立管126R下部的左侧，那么将会丧失这种屏蔽。如果阱134的末端与导电立管126R下部的最远端侧(即，左侧)间隔开等于或大于阱134深度的距离L2，那么获得最佳的这种屏蔽效果。在优选的实施中，L2等于或大于阱134深度加上在阱134和导电立管126R之间的分隔距离，其中该分隔距离等于用于在图中示出的构造的氧化物层106的薄部分。
如上面提及的，布置在p-掺杂阱134任一侧上的栅电极126和屏蔽电极124通常消耗邻近阱134末端的n-掺杂平台130的部分，由此显著减小阱134末端周围的电位和电场。为实现这个益处，p-掺杂区的末端应与屏蔽电极124的末端、或沟槽122的末端间隔开至少距离L3，如图12中示出的。距离L3可以等于沟槽122的深度，或者可以等于沟槽122的深度和阱134的深度之间的差。阱134可以延伸超过栅极立管126R，如图13中示出的，并且阱134的末端进一步可以布置在屏蔽浇道(和场板(fieldplate))下面。如果屏蔽浇道布置在阱134末端附近或上方，则它能够以如之前参考图11描述的栅极立管126R提供屏蔽的方式提供屏蔽，从而减轻在阱134末端处的曲率半径效应。然而，对于低和中等电压施加，屏蔽浇道不需要布置在p掺杂阱134的末端上方。尽管优选没有其他p-掺杂区布置在阱134的末端和相邻沟槽的末端之间，但更轻度的p-掺杂区可以布置在阱134的末端和相邻沟槽的末端之间。如横跨平台宽度的剖面测量的，更轻度的p-掺杂区具有比阱134更低的掺杂剂量。换句话说，如横跨平台宽度的剖面测量的，更轻度的p-掺杂区具有由于掺杂剂导致的比阱134更低的整体改变。利用以上的构造，如在现有技术构造中完成的，不需要垂直于沟槽122末端伸展的终止沟槽。p-掺杂阱134末端的全部以上构造可以应用于沟槽屏蔽的肖特基势垒二极管器件，其中以上的间隔距离施加至肖特基金属的末端，或者如果类似于图6中示出的区域239’的p-掺杂区在肖特基金属的周边周围使用。采用这些发明性方面的沟槽屏蔽的肖特基势垒二极管器件的示例性实施方式在下面参考图32-34进行描述。
再次参考图10，可以看到，屏蔽浇道金属在处于或低于外延层104顶部表面的水平处与屏蔽电极124的立管部分124R的顶部表面形成电接触。这个特征也在图14中示出，其为垂直于图10的剖面。如图14中看到的，通过穿过介电层107和氧化物层106形成的接触开口形成从屏蔽浇道金属到立管部分124R的接触。这种构造具有减小的电接触电阻以及简化制造工艺的优点。在常规制造工艺中，多晶硅蚀刻掩模和蚀刻步骤用来定义在屏蔽浇道金属和屏蔽电极124、224之间的多晶硅总线结构。然而，能够通过调整工艺中使用的早期掩模，例如用来定义图5中示出的从源极金属到增强的掺杂区135和源极区136的掩模而定义以上简化的接触结构。因此，可以消除传统用来定义上述多晶硅总线结构的掩模和蚀刻步骤。
当制作高电流容量器件时，可以使用器件区120的若干实例而不是一个大的器件区120。器件区120的这些实例并联电耦接，并且与其中使用器件区120的一个大实例的情况相比，这种构造向屏蔽电极124的中心和栅电极126的中心提供低电阻路径。图15示出了布置在半导体芯片上的半导体器件200的顶部示意平面图。器件200包括布置在底部器件区120B上方的顶部器件区120A、布置在顶部器件区120A上方的顶部连接区150(如先前描述的)、布置在器件区120B下面的底部连接区150、布置在器件区120A和120B之间的中间连接区250。器件区120A和120B是先前描述的器件区120的实例。存在在每个连接区150中的栅极浇道和屏蔽浇道，以及在中间连接区250中的两个栅极浇道和一个屏蔽浇道。栅极浇道通过栅极馈送(gate feed)而电耦接至栅极焊盘212。源极金属层110布置在器件区120A和120B上方，电耦接至屏蔽浇道和两个源极焊盘111。多个交错沟槽122’和平台130’布置在半导体外延层中，并且在器件区120A、120B和连接区150、250内，如通过在图右侧处的短划线示出的。为在在图中视觉上清晰，仅示出了前几个沟槽和平台，但在阵列左边的箭头符号示意地表示交错沟槽和平台的阵列延伸到器件区120A、120B和连接区150、250的左侧。沟槽122’与沟槽122基本相同，除了它们连续伸展通过器件区120A、120B和连接区150、250之外。平台130’与平台130基本相同，除了它们连续伸展通过器件区120A、120B和连接区150、250之外。沟道截断环结构在芯片周边处围绕区域120A、120B、150和250，并通过间隙与区域120A、120B、150和250分隔开。这种间隙与在图11中示出的间隙相同。
图16示出了沿图15中示出的切割线16-16，连接区250的剖面图。该剖面沿沟槽122’截取。组件与参考图10在上面描述的组件相同，只是在该图左侧出现的栅电极126、栅极立管126R和栅极浇道的镜像组(mirrorset)，不存在介电贴片123C和介电侧123S，并且沟槽122’、介电层123’、屏蔽电极124’和屏蔽立管124R’镜像到左侧并沿剖面从左到右伸展。栅极浇道与栅电极126的栅极立管126R形成电接触，但与屏蔽金属浇道以及屏蔽立管124R’和屏蔽电极124’电绝缘。屏蔽浇道金属与屏蔽立管124R’和屏蔽电极124’形成电接触，但与栅极浇道、栅极立管124R和栅电极124电绝缘。以上沟槽构造消除了在紧接连接区150中的沟槽中断的器件100的平台区中发生的电场和电位不平衡，并因此消除相应的局部化电荷不平衡。这种构造背离了在连接区205的中部包括复杂场终止结构的现有技术构造。
图17示出了沿图15中示出的切割线17-17，连接区250的剖面图。该剖面沿平台130’截取。组件与参考图10在上面描述的组件相同，除了在图左侧出现的p掺杂阱134、栅电极126、栅极立管126R和栅极浇道的镜像组之外。屏蔽电极124’和栅电极125的位置的轮廓用短划线示出。类似于器件100，每个p-掺杂阱134典型地电耦接至源极和屏蔽的电位，但对于其中该区域用于场终止区中的一些情形可以处于浮置状态。每个p-掺杂阱134都具有优选在导电立管126R(是导电引线)处或下方终止的末端。存在由于曲率半径效应引起的在每个p-掺杂阱134末端处发生击穿的可能性。然而，布置在p-掺杂阱134任一侧上的栅电极126和屏蔽电极124通常消耗与阱134末端相邻的每个n-掺杂平台130的部分，由此显著减小阱134末端周围的电位和电场。然而，减小量的电场仍在阱134的末端周围存在，并且能够以径向方式(即，曲率半径效应)在阱134的末端处集中。然而，利用图17中示出的构造，阱134的末端基本上由栅极立管126R屏蔽，并且该构造基本减小在区域末端处的曲率半径效应(如先前参考图11的器件100描述的)。如果阱134的末端延伸超过布置在它上面的导电立管126R下部的远侧，那么将会丧失这种屏蔽。如果阱134的末端不延伸超过导电立管126R下部的远侧，并进一步与导电立管126R下部最远侧间隔开等于或大于阱134深度的距离L2，那么获得最佳的这种屏蔽效应。在优选的实施中，L2等于或大于阱134的深度加上在阱134和导电立管126R之间的分隔距离，其中该分隔距离等于用于该图中示出的构造的氧化物层106的薄部分。
图18示出了连接区250的一种变形250’的剖面图，其包括布置在外延层(epi layer)104中并在屏蔽浇道金属下面的电浮置p-掺杂阱134C。(该p-掺杂区通过在它和适合从外部电路接收电位的导电层之间不形成直接电连接而使其浮置。)浮置p-掺杂阱134C充当在外延层104和在它上面的氧化层106的部分之间的缓冲屏蔽。由于屏蔽浇道金属通常处于接地电位并且外延层104的下面部分通常处于漏极电位，所以在屏蔽浇道金属和外延层104之间的氧化层106的部分能够经受高电场。为了减小在p-掺杂阱134C的末端处的曲率半径效应，这些末端可以布置在栅极立管126R附近或下面。
图19示出了连接区250的另一种变形250”的剖面图，其包括连续p-掺杂阱134’代替图17中示出的两个阱134。连续p-掺杂阱134’从器件区120A延伸到器件区120B，并穿过连接区250”，并且电耦接至源极金属层110(又耦接至屏蔽浇道金属)。因为阱134’没有侧边缘或角落，所以没有与连续p-掺杂阱134’相关的曲率半径效应。连续p-掺杂阱134’也充当在外延层104和它上面的氧化层106之间的缓冲屏蔽。如上面指出的，由于屏蔽浇道金属通常处于接地电位并且外延层104的下面部分通常处于漏极电位，所以在屏蔽浇道金属和外延层104之间的氧化层106的部分能够经受高电场。
在举例说明连接区150、250、250’和250”的所有实施方式中，可以理解，每个连接区都具有产生无源器件的带有平台130、130’的相邻部分的一个以上的材料体(material body)的构造，其平台。材料体可以包括掺杂区、介电层、导电层等。相反，每个器件区120、120A、120B具有产生有源器件的带有平台130、130’的部分的一个以上材料体的构造平台。
现在参考图20中示出的半导体器件300描述并举例说明另一个实施方式。半导体器件300具有与图1-3中示出的半导体器件100基本相同的平面图(俯视图)。图20是沿半导体器件300的芯片的左侧部分的放大图，类似于图3中示出的器件100的左侧部分的放大图。半导体器件300包括以基本相同方式布置的与器件100基本相同的元件，并进一步包括环绕在先前描述的沟槽122、222和平台130、230的全部阵列，或者环绕该阵列周围的至少75％周边的周边沟槽(perimeter trench)320。(可以理解，周边沟槽320可以通过可不显著影响它的效果的相对较小破裂的一个或多个破裂而是不连续的。)图21和图22示出了沿阵列的底部，并沿图20中示出的切割线21-21和22-22，周边沟槽320与沟槽122、222和平台130、230的阵列的剖面。周边沟槽320包括内衬它的相对侧壁的介电层321，以及布置在沟槽中的导电电极324。导电电极324可以电耦接至导电层，例如屏蔽浇道，从而接收接地电位，或可以与带有电位的任何导电层去耦接，由此处于浮置电位。周边屏蔽320与沟槽222隔开在相邻沟槽122之间的间隔数量级的距离。间隙区(gap region)330布置在周边屏蔽320和沟槽222之间。没有电位通过任何导电层耦接至间隙区330的顶部，并且间隙区330中的电位是浮置的。当周边沟槽电极324处于浮置电位时，在它和浮置间隙区330上的电位能够浮动从而设定关于漏极电位的平衡电位(补偿电位，equalizing potential)，并能够由此减小对间隙区330中的电荷不平衡的敏感度。因此，变得比如果这些间隙区330通过常规接地p-阱固定在源极电位处更容易在间隙区330中实现电荷平衡条件。当周边沟槽电极324耦接至接地电位时实现基本相同的益处。间隙区330的宽度可以等于或小于平台130宽度的1.25倍，并且沿周边沟槽320各个侧面的间隙区330的宽度可以不同。例如，沿周边沟槽320(以及沟槽122和平台130的主阵列)左右垂直侧的间隙区330的宽度可以小于沿周边沟槽320(以及该主阵列)顶部和底部水平侧的间隙区330的宽度。
图23和图24是示出了沿主沟槽122和平台130的末端，并沿图20中示出的切割线23-23和24-24，周边沟槽320的剖面图。图23和图24的剖面基本上与对于器件100的图10和图11的剖面相同，加上添加的周边沟槽320和间隙区330。元件102-107、120、122、123、123C、123S、124、124R、125、125C、125S、126、126R、134、150、屏蔽浇道、栅极浇道和沟道截断环具有关于彼此的相同的相对关系。如上面指出的，由于曲率半径效应引起的击穿的一个可能区域，特别是对于高电压器件，存在于在屏蔽立管部分124R的末端处的介电侧面层123S中，如图23中通过点“A”指示的(与图10相同)。如先前描述的，通过在介电侧面层123S上方并以距离L1超过沟槽122的末端延伸顶侧屏蔽浇道金属(其为导电引线)，能够显著减少这种可能的击穿区域。距离L1可以等于或大于沟槽122的深度。周边沟槽320还通过移动电场远离点A而减轻可能的击穿区域。如上面指示的，当周边沟槽电极324处于浮置电位时，在它和浮置间隙区330上的电位能够浮动从而设定关于漏极电位的平衡电位，并能够由此减小对间隙区330中电荷不平衡的敏感度。因此，变得比如果这些间隙区330通过常规接地p-阱固定在源极电位下更容易在间隙区330中实现电荷平衡条件。当周边沟槽电极324耦接至接地电位(这可以通过布置在屏蔽电极324和屏蔽浇道金属之间的导电材料的接触通孔(contact via)325来完成)时实现基本相同的益处，其中接触通孔325电耦接至屏蔽浇道和屏蔽电极324二者。
相同的以上益处能够通过在浮置间隙区330中使用浮置p-掺杂阱334基本实现。这种实施方式通过图25-28举例说明，除了添加了浮置p-掺杂阱334之外，其与图21-24中的剖面相同。没有接地电位电压耦接至阱334。图29示出了布置在沟槽222和周边沟槽320之间的在间隙区330的部分中的浮置p-掺杂阱334。阱334左延伸至与周边沟槽320相邻。尽管阱334已经作为与周边沟槽320相邻布置的连续条示出，但可以理解，阱334可以是分段的(在连续条带中具有间隙)。阱334的任何分段区的末端可以布置在屏蔽浇道和其他导电引线下面，以最小化曲率半径效应。
如上面指出的，周边沟槽320可以是连续的并环绕沟槽122、222和平台130、230的整个阵列，或这可以是不连续的并环绕该阵列周围的至少75％周边。再次参考图20，当使用不连续周边沟槽320时，通常在阵列的角落处引入沟槽320中的破裂，其中每个破裂典型地小于间隙区330宽度的两倍，并且典型地等于间隙区330的宽度。在使用不连续周边沟槽320的一个实施方式中，在图20中的点“D”处，周边沟槽在它的水平支柱的末端处破裂，使得周边沟槽320的水平支柱具有与内沟槽122、222相同的长度。周边沟槽320的垂直支柱可以与水平支柱的末端齐平结束，或者可以延伸超过水平支柱的末端，如通过到图20中的点“E”的垂直支柱之一的点线延伸示出的。后一种延伸目前优选在与水平支柱末端齐平的垂直支柱结束的上方。在使用不连续周边沟槽320的另一实施方式中，在图20中点“F”处，周边沟槽在它的垂直支柱末端处破裂，使得周边沟槽320的水平支柱延伸超过内沟槽122、222的末端。周边沟槽320的水平支柱可以与垂直支柱的末端齐平结束，或者可以以与在先前实施方式中描述的相同方式延伸超过垂直支柱的末端。在之前的两个实施方式的每一个中，周边沟槽320的水平支柱和垂直支柱可以是电浮置的或接地的。可以使垂直支柱接地而使水平支柱电浮，反之亦然。同样，不连续周边沟槽320的不同段可易于具有不同电状态(例如，浮置状态、接地状态)。
当使用具有接地或浮置电极324的周边沟槽320时，在周边沟槽320的角转向(corner turn)处可存在电荷不平衡。这是因为间隙区330经历周边沟槽320的两个侧面而不是一个，如在图30的放大俯视图中示出的。周边沟槽的电极324试图消耗尽比间隙区330的角落区中存在的电荷更多的电荷。这种电荷不平衡能够通过缩短与周边沟槽320的水平支柱相邻的沟槽222的长度而得到解决。这作为器件400提供，其除了缩短沟槽之外，与器件300相同。沟槽222的缩短减小了沟槽222在间隙区300角落上的电荷成像效应，并由此补偿周边沟槽的电极324的过度成像。图31示出了缩短的沟槽222的剖面，连同未缩短长度的轮廓以进行比较。沟槽222的末端比沟槽122的末端与周边沟槽320隔得更远。器件300的p型阱334可以添加到具有器件400，其中器件400具有以上描述的构造的任一种。器件400的p-型阱334可以处于浮动电位(浮置电位)或处于固定电位(例如，接地电位)。
如在器件100的讨论和图1-14中简要指出的，器件100的一些发明性方面可以应用于沟槽屏蔽肖特基势垒二极管器件。肖特基二极管器件可以具有与器件100相似的构造，如在图1-14中举例说明的，并且可以包括与器件100相同的组件，但不需要栅电极126和226、栅极浇道、栅极焊盘、源极区136、布置在平台上的介电层106和107的部分，以及阱区134。图32-34示出了根据本发明方面的示例性肖特基二极管器件100”的剖面。图32示出了通过器件100”的器件区120的剖面，类似于器件100的图6中示出的剖面。器件100”包括分别类似于沟槽122和222的沟槽122”和222”，除了沟槽122”和222”分别不需要包括栅电极126和226，并且可以包括延伸到外延层104顶部或其附近的屏蔽电极124”，并且其可以高于屏蔽电极124之外。(在其他肖特基实施方式中，可以使用栅电极126和226连同栅极浇道，这种情况下它们通常耦接至源极金属层110的电位。)器件100”还包括沟槽220、平台130、230和230’、场终止区中的介电层106和107、以及器件100的源极金属层110。作为与器件100的不同，源极金属层和屏蔽浇道可以融合在一起，因为它们之间不存在栅极浇道。源极金属层110接触平台130的顶部从而提供肖特基势垒接触。表面补偿注入可以布置在平台130顶部处，以调整肖特基接触的电特性(例如，势垒高度)，如本领域中已知的。p-型阱134”可以布置在平台230顶部处，以提供具有比平台130中的肖特基势垒器件更高的反向偏置击穿电压的p-n结二极管。阱134”可以具有比阱134’更高的掺杂，使得可以省去增强的掺杂区135，或者可以包括增强的掺杂区135或在平台230顶部处的增强掺杂的层，以提供与源极金属层110的良好导电连接。在器件100的另一实施中，可以省去阱134”，并且介电层107和/106可以在平台230的顶部上方延伸，从而使它与源极金属层110电绝缘，因此使它与平台230’相似。在平台230的每一种实施中，平台230与沟槽222”和122”用来使对于器件100如上面描述的电位和场图案成形，从而改善器件100”的总体击穿电压特性。
图33示出了沿图3中定义的切割线10-10，在连接区150中的沟槽122”的剖面。图33的剖面类似于对于器件100的在图10中示出的剖面。屏蔽电极124”布置在沟槽中，其中屏蔽电极124与屏蔽浇道和源极金属层形成电接触。屏蔽电极124”具有邻近介电材料的贴片123C布置的外侧角，以及邻近介电材料的侧面层123S布置的垂直侧。如先前描述的，曲率半径效应显著增大紧接屏蔽电极外侧角的区域中的电场。由于曲率半径效应引起的可能击穿区，特别是对于高电压器件，存在于在屏蔽立管电极124”末端处的介电侧面层123S中，如在图33中通过点“A”指示的。这种电位击穿能够通过在介电侧面层123S上方并以距离L1超过沟槽122”的末端延伸顶侧屏蔽浇道金属(其为导电引线)而显著减轻。距离L1可以等于或大于沟槽122”的深度。对于较低电压器件应用，在点“A”处的击穿的可能性非常小，并且顶侧屏蔽浇道金属不需要在介电侧面层123S上方或超过沟槽122”的末端延伸，如在图中通过边缘“B”指示的。这种构造导致得到更薄的屏蔽浇道和更小的芯片。
图34示出了沿图3中定义的切割线11-11，在连接区150中的平台130的剖面。这个剖面类似于对于器件100的在图11-13中示出的剖面。如在图34中示出的，源极金属110覆盖平台130顶部的一部分(在图中的右边示出)从而提供肖特基势垒接触。在平台130任一侧上的屏蔽电极124”的位置以点线轮廓示出。介电层106和107使屏蔽浇道和场板与平台分隔开。存在在接触平台130的源极金属层110的末端边缘处发生击穿的可能性，其中它接触平台130，由于曲率半径效应。这个末端边缘是肖特基势垒金属的末端(即，与半导体一起形成肖特基势垒的金属部分)，并在图中以点“C”指示。布置在平台130任一侧上的屏蔽电极124”通常消耗与源极金属层110末端边缘相邻的平台的部分，由此显著减小该末端边缘周围的电位和电场。为实现这个益处，末端边缘应与屏蔽电极124”的末端或沟槽122”的末端隔开至少距离L3，如图34中示出的。距离L3可以等于沟槽122”的深度。利用这种构造，不需要如在现有技术构造中可以完成的那样，在点C处的肖特基势垒金属末端边缘的平台130中布置p-掺杂区。然而，p-掺杂区130可以布置在肖特基势垒金属末端边缘附近的平台130中，如通过p掺杂区334’的点线轮廓指示的。如果使用p掺杂区334’，则它应当与屏蔽电极124”的末端、或沟槽122”的末端隔开至少以上的距离L3。
如能够在图33和34的每个中看出的，没有在层104顶部表面处、垂直于沟槽122”和屏蔽电极124”的末端布置的垂直终止沟槽。这是与对于器件100在上面示出的相同的终止构造，并且减小了芯片尺寸。然而，如果期望，垂直终止沟槽或周边沟槽可以添加到器件100”中。
尽管已经用n-型外延层和p-型掺杂阱区举例说明了以上实施方式，但是可以理解，本发明和实施方式可以用p-型外延层和n-型掺杂阱区来实现。换句话说，本发明和实施方式可以用颠倒的层和区域的掺杂极性来实现。
尽管本发明的各种实施方式主要以N沟道屏蔽栅极MOSFET的内容进行描述，但是这些实施方式可以在各种各样的其他类型的器件中实施，例如P-沟道MOSFET(即，除了所有硅区域的导电类型颠倒之外，结构类似于上述MOSFET的晶体管)；N-沟道屏蔽栅极IGBT(即，除了使用P-型衬底代替N型衬底之外，结构类似于上述MOSFET的晶体管)；P-沟道屏蔽栅极IGBT(即，除了衬底保持N-型之外，结构类似于上述MOSFET，但具有相反导电性的硅区的晶体管)；屏蔽栅极同步整流管(即，集成屏蔽栅极MOSFET和肖特基)；TMBS整流管，以及以上器件的超结(superjunction)变形(即，具有交替导电型硅的列的器件)。
“一”、“一个”和“该”的任何叙述用于指一个或多个，除非有具体的相反说明。
本文中已经采用的术语和表达用作描述的术语并且不用于限制，并且在使用这样的术语和表达中没有排除所示出和所描述的特征的等同替换的意图，应该理解，在要求保护的本发明范畴内可以进行各种修改。
此外，在不背离本发明范围的情况下，本发明一个或多个实施方式的一个或多个特征可以与本发明其他实施方式的一个或多个特征进行组合。
尽管本发明关于举例说明的实施方式进行了具体描述，但是应该理解，基于本申请公开内容可以形成各种变形、修改、改编和等效布置，并且落入本发明和权利要求的范畴之内。

Claims (35)

1.一种半导体器件，包括：
延伸到半导体区中并且具有第一末端和第二末端的第一沟槽；
内衬所述第一沟槽的相对侧壁的第一介电层；
布置在所述第一沟槽中的第一屏蔽电极；
延伸到所述半导体区中并且具有第一末端和第二末端的第二沟槽；
内衬所述第二沟槽的相对侧壁的第二介电层；
布置在所述第二沟槽中的第二屏蔽电极；以及
布置在所述半导体区中且在所述第一和第二沟槽之间的第一导电型的第一阱区，所述第一阱区与所述第一沟槽的所述第一末端至少间隔第一距离；并且
其中，在所述第一阱区和所述第一沟槽的所述第一末端之间没有布置所述第一导电型的其他阱区。
2.根据权利要求1所述的半导体器件，其中，所述第一阱区电耦接至导电层以接收电位。
3.根据权利要求1所述的半导体器件，其中，所述第一沟槽在所述半导体区内延伸至第一深度，并且其中所述第一距离等于所述第一深度。
4.根据权利要求1所述的半导体器件，其中，所述第一沟槽在所述半导体区内延伸至第一深度，其中所述第一阱区在所述半导体区中延伸至第二深度，所述第二深度小于所述第一深度，并且其中所述第一距离等于所述第一深度和所述第二深度之间的差。
5.根据权利要求1所述的半导体器件，其中，所述半导体区布置在半导体芯片中；
其中所述第一和第二沟槽的所述第一末端面对所述半导体芯片的第一边缘；
其中所述半导体区的第一部分布置在所述第一和第二沟槽的所述第一末端与所述半导体芯片的所述第一边缘之间；以及
其中所述第一部分不具有布置在所述半导体区中的垂直终止沟槽。
6.根据权利要求1所述的半导体器件，其中，所述第一阱区具有与所述第一沟槽的所述第一末端至少间隔所述第一距离的第一末端，并且其中所述器件进一步包括布置在所述第一阱区的所述第一末端上方的场板，所述场板电耦接至所述屏蔽电极。
7.根据权利要求1所述的半导体器件，其中，所述第一阱区具有与所述第一沟槽的所述第一末端至少间隔所述第一距离的第一末端，并且其中没有布置在电耦接至所述屏蔽电极的所述第一阱区的所述第一末端上方的导电层。
8.一种半导体器件，包括：
延伸到半导体区内并且具有第一末端和第二末端的第一沟槽；
内衬所述第一沟槽的相对侧壁的第一介电层；
布置在所述第一沟槽中的第一屏蔽电极；
延伸到所述半导体区中并且具有第一末端和第二末端的第二沟槽；
内衬所述第二沟槽的相对侧壁的第二介电层；
布置在所述第二沟槽中的第二屏蔽电极；
布置在所述半导体区中且在所述第一和第二沟槽之间的第一导电型的第一阱区，所述第一阱区与所述第一沟槽的所述第一末端至少间隔第一距离；以及
布置在所述第一阱区与所述第一沟槽的所述第一末端之间的第一导电型的第二阱区，所述第二阱区比所述第一阱区更轻度地掺杂。
9.根据权利要求8所述的半导体器件，其中，所述第一阱区电耦接至导电层以接收电位。
10.根据权利要求8所述的半导体器件，其中，所述第一沟槽在所述半导体区内延伸至第一深度，并且其中所述第一距离等于所述第一深度。
11.根据权利要求8所述的半导体器件，其中，所述第一沟槽在所述半导体区内延伸至第一深度，其中所述第一阱区在所述半导体区内延伸至第二深度，所述第二深度小于所述第一深度，并且其中所述第一距离等于所述第一深度和所述第二深度之间的差。
12.根据权利要求8所述的半导体器件，其中，所述半导体层布置在半导体芯片上；
其中所述第一和第二沟槽的所述第一末端面对所述半导体芯片的第一边缘；
所述半导体层的第一部分布置在所述第一和第二沟槽的所述第一末端与所述半导体芯片的所述第一边缘之间；以及
其中所述第一部分不具有布置在所述半导体层的所述第一表面处的垂直终止沟槽。
13.根据权利要求8所述的半导体器件，其中，所述第一阱区具有与所述第一沟槽的所述第一末端至少间隔所述第一距离的第一末端，并且其中所述器件进一步包括布置在所述第一阱区的所述第一末端上方的场板，所述场板电耦接至所述屏蔽电极。
14.根据权利要求8所述的半导体器件，其中，所述第一阱区具有与所述第一沟槽的所述第一末端至少间隔所述第一距离的第一末端，并且其中没有布置在电耦接至所述屏蔽电极的所述第一阱区的所述第一末端上方的导电层。
15.一种沟道屏蔽肖特基势垒整流器件，包括：
延伸到半导体区内并且具有第一末端和第二末端的第一沟槽；
内衬所述第一沟槽的相对侧壁的第一介电层；
布置在所述第一沟槽中的第一屏蔽电极；
延伸到所述半导体区内并且具有第一末端和第二末端的第二沟槽；
内衬所述第二沟槽的相对侧壁的第二介电层；
布置在所述第二沟槽中的第二屏蔽电极；以及
由所述第一和第二沟槽限定的平台区，所述平台区具有宽度、高度和顶面；以及
布置在所述平台的所述顶面处的肖特基接触，所述肖特基接触具有与所述第一沟槽的所述第一末端至少间隔第一距离的第一末端。
16.根据权利要求15所述的半导体器件，其中，所述第一距离等于所述沟槽的深度。
17.根据权利要求15所述的半导体器件，其中，p-掺杂区布置在所述肖特基势垒金属的末端边缘处的所述沟槽的所述末端之间，所述p-掺杂区与所述沟槽的所述末端间隔开。
18.一种半导体器件，包括：
延伸到半导体区内并且具有第一末端和第二末端的第一沟槽；
内衬所述第一沟槽的相对侧壁的第一介电层；
布置在所述第一沟槽中的第一电极；
延伸到所述半导体区内并且具有第一末端和第二末端的第二沟槽；
内衬所述第二沟槽的相对侧壁的第二介电层；
布置在所述第二沟槽中的第二电极；
布置在所述半导体区中且在所述第一和第二沟槽之间的第一导电型的阱区，所述阱区具有第一末端；以及
布置在所述第一和第二沟槽上方的导电引线，所述导电引线具有垂直于所述沟槽伸展的长度和小于所述长度的宽度，所述导电引线具有与布置在所述沟槽之间的所述半导体区的部分间隔第一距离的部分，所述引线的所述部分具有平行于所述引线的长度的第一侧面和第二侧面，所述第一侧面比所述第二侧面更靠近所述阱区的所述第一末端；并且
其中，所述阱区的所述第一末端与所述导电引线的所述第二侧面至少间隔第二距离。
19.根据权利要求18所述的半导体器件，其中，所述阱区电耦接至导电层以接收电位。
20.根据权利要求18所述的半导体器件，其中，所述阱区在所述半导体区内延伸第一深度，并且其中所述第二距离等于所述第一深度。
21.根据权利要求18所述的半导体器件，其中，所述阱区在所述半导体区内延伸第一深度，并且其中所述第二距离等于所述第一距离加上所述第一深度。
22.一种半导体器件，包括：
布置在半导体区的表面处的至少第一器件区和第二器件区，所述第二器件区与所述第一器件区相邻并且与所述第一器件区间隔开；
布置在所述第一器件区和所述第二器件区之间的连接区；
第一沟槽，其延伸到所述半导体区内，而且至少从所述第一器件区延伸，通过所述连接区，并到达所述第二器件区；
内衬所述第一沟槽的相对侧壁的第一介电层；
布置在所述第一沟槽中的第一电极；以及
布置在所述连接区中的所述第一沟槽上方并且电耦接至所述连接区中的所述第一电极的第一导电引线。
23.根据权利要求22所述的半导体器件，其中，所述第一电极包括栅电极，并且具有在所述器件区的每一个中的布置在它上方的电介质。
24.根据权利要求22所述的半导体器件，其中，所述第一电极包括屏蔽电极，并且其中所述半导体器件进一步包括布置在所述第一沟槽中但与所述屏蔽电极电绝缘的栅电极。
25.根据权利要求24所述的半导体器件，进一步包括第二导电引线，其布置在所述连接区中的所述第一沟槽上方并且电耦接至所述连接区中的所述栅电极，并且与所述屏蔽电极电绝缘。
26.根据权利要求22所述的半导体器件，进一步包括与所述第一沟槽相邻布置的第一平台、在所述连接区内具有所述第一平台区的部分的一个或多个材料体的第一构造、在所述第一器件区内具有所述第一平台区的所述部分的一个或多个材料体的第二构造、在第二第一器件区内具有所述第一平台区的所述部分的一个或多个材料体的第三构造，其中所述第一构造不同于所述第二构造和所述第三构造中的每一个。
27.根据权利要求22所述的半导体器件，进一步包括：
第二沟槽，其延伸到所述半导体区内而且至少从所述第一器件区延伸，通过所述连接区，并到达所述第二器件区；
内衬所述第二沟槽的相对侧壁的第二介电层；
布置在所述第二沟槽中的第二电极；以及
布置在所述半导体区中且在所述第一和第二沟槽之间的第一导电型的阱区，所述阱区具有第一末端；以及
布置在所述第一和第二沟槽上方的第二导电引线，所述导电引线具有垂直于所述沟槽伸展的长度和小于所述长度的宽度，所述第二导电引线具有与布置在所述沟槽之间的所述半导体区的部分间隔第一距离的部分，所述第二引线的所述部分具有平行于所述引线的长度的第一侧面和第二侧面，所述第一侧面比所述第二侧面更靠近所述阱区的所述第一末端；并且
其中所述阱区的所述第一末端与所述第二导电引线的所述第二侧面至少间隔第二距离。
28.根据权利要求27所述的半导体器件，其中，所述阱区电耦接至导电层以接收电位。
29.根据权利要求27所述的半导体器件，其中，所述阱区在所述半导体区内延伸第一深度，并且其中所述第二距离等于所述第一深度。
30.根据权利要求27所述的半导体器件，其中所述阱区在所述半导体区内延伸第一深度，并且其中所述第二距离等于所述第一距离加上所述第一深度。
31.根据权利要求27所述的半导体器件，进一步包括布置在所述半导体区中、在所述第一和第二沟槽之间并且在所述第一导电引线下面的第一导电型的第二阱区。
32.根据权利要求31所述的半导体器件，其中，所述第二阱区是电浮置的。
33.根据权利要求22所述的半导体器件，进一步包括布置在所述半导体区中且在所述第一导电引线下面的第一导电型的阱区。
34.根据权利要求33所述的半导体器件，其中，所述第二阱区是电浮置的。
35.根据权利要求22所述的半导体器件，进一步包括：
第二沟槽，其延伸到所述半导体区内而且至少从所述第一器件区延伸，通过所述连接区，并到达所述第二器件区；
内衬所述第二沟槽的相对侧壁的第二介电层；
布置在所述第二沟槽中的第二电极；以及
布置在所述半导体区中且在所述第一和第二沟槽之间的第一导电型的阱区，所述阱区从所述第一器件区延伸，通过所述连接区，并到达所述第二器件区。
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CN103367437A (zh) * 2012-04-03 2013-10-23 朱江 一种沟槽mos半导体装置及其制造方法
CN103367437B (zh) * 2012-04-03 2017-04-26 朱江 一种沟槽mos半导体装置及其制造方法
CN104241337A (zh) * 2013-06-21 2014-12-24 英飞凌科技奥地利有限公司 具有复合中心的半导体器件和制造方法
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CN117059669A (zh) * 2023-10-09 2023-11-14 华羿微电子股份有限公司 一种屏蔽栅型mosfet终端结构及制作方法
CN117059669B (zh) * 2023-10-09 2024-02-06 华羿微电子股份有限公司 一种屏蔽栅型mosfet终端结构及制作方法

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