CN102315093A

CN102315093A - Process method for flattening filled trench

Info

Publication number: CN102315093A
Application number: CN2010102215974A
Authority: CN
Inventors: 刘继全
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-07-08
Filing date: 2010-07-08
Publication date: 2012-01-11
Anticipated expiration: 2030-07-08
Also published as: CN102315093B

Abstract

The invention discloses a process method for flattening a filled trench. The process method comprises the following steps of: growing a layer of epitaxial layer on a substrate silicon sheet; growing a hard mask on the epitaxial layer; forming the trench in the epitaxial layer; epitaxially growing silicon in the trench so as to fill the trench; preliminarily flattening the surface of the trench by grinding by using chemical machinery; performing high-temperature thermal oxidation on the silicon on the surface of the trench; and removing an oxidized layer and the hard mask from the surface of the trench by using wet etching or dry etching. By the process method, flattening of the surface of the trench can be realized, and the surface of the trench can be flattened well; and the process method is applicable to super junction metal-oxide-semiconductor field effect transistor (MOSFET) devices.

Description

The process of planarization after the trench fill

Technical field

The present invention relates to the semiconductor integrated circuit field, particularly relate to the process of planarization after a kind of trench fill.

Background technology

The structure of super junction MOSFET device is as shown in Figure 1, and the groove-shaped epitaxial loayer 3 that films of opposite conductivity is filled that has is arranged in the N epitaxial loayer 2 on silicon substrate (N+ substrate) 1, and this top, zone is surrounded by P well region 5, N+ well region 6, P+ implanted layer 7 from outside to inside successively.Between two groove-shaped epitaxial loayers 3, be provided with polysilicon 4 on the N epitaxial loayer 2, polysilicon 4 is provided with inter-level dielectric 8, and source metal electrode 9 covers whole inter-level dielectric 8 and epitaxial loayer 3 then.There is back metal electrode (drain electrode) 10 at N+ substrate 1 back side.

The main difficult point of this device is the P type of alternately arrangement and the formation of N type semiconductor laminate structure.This structure forms process has two kinds, and first kind of (see figure 2) is: growth one deck epitaxial loayer 22 on silicon substrate 21, and suitable position is injected to mix and is formed ion implanted region 23 in epitaxial loayer 22; Regrowth one deck epitaxial loayer 22 on original epitaxial loayer 22; At last time identical injection doping position, the epitaxial loayer 22 that is positioned at the back growth injects to mix again and forms ion implanted region 23.Mix with injecting through the multiple cycles epitaxial growth like this, reach needed channel depth until epitaxial thickness.Inject the doped region diffusion at boiler tube and make a plurality of ion implanted regions form the doped region 25 of a completion, complete like this P (or N) type thin layer is just calculated completion.The problem that this method exists is: at first, cost is higher, and extension all is that semiconductor is made cost higher technology, particularly extension with injecting, in general semiconductor is made generally for once; Next is a difficult technique with control, and epitaxial growth several times requires identical resistivity, and identical film quality is had relatively high expectations to the stable aspect of technology; Each in addition injection all requires in identical position, all requires very high to aligning, the precision aspect of injecting.

A kind of in addition method of manufacturing technology is, at first the silicon epitaxy layer 32 of growth one bed thickness on silicon substrate 31 forms groove 35 then on this epitaxial loayer 32, and using with epitaxial loayer 32 has silicon epitaxy 33 filling grooves 35 (see figure 3)s of contra-doping mutually again.Extension fills the back because the surplus growth of extension generally will be carried out planarization to flute surfaces.The method of planarization generally has two kinds, and the one, cmp, the 2nd, dry etching.Two kinds of methods all need hard mask as the barrier layer, but the etching selection ratio of two kinds of materials of dry etching generally is lower than the grinding ratio of cmp, so select for use chemical and mechanical grinding method to carry out planarization usually.But chemical and mechanical grinding method also has limitation, and promptly milling time is long, has certain thickness silicon residual at hard mask easily, in case produce the residual then cmp of silicon then be difficult to get rid of.

Summary of the invention

The technical problem that the present invention will solve provides the process of planarization after a kind of trench fill, can obtain the good flute surfaces of planarization.

For solving the problems of the technologies described above, the process of planarization comprises the steps: after the trench fill of the present invention

Step 1, one deck epitaxial loayer of on silicon substrate, growing;

Step 2, on said epitaxial loayer, carry out the growth of hard mask;

Step 3, in said epitaxial loayer, form groove;

Step 4, in said groove, carry out growing epitaxial silicon and fill this groove;

Step 5, said flute surfaces is carried out preliminary planarization with cmp;

Step 6, the silicon of said flute surfaces is carried out high-temperature thermal oxidation;

Step 7, remove the oxide layer and the hard mask of flute surfaces with wet etching or dry etching.

Adopt method of the present invention, behind etching groove, keep hard mask, use the growing epitaxial silicon filling groove then, with cmp groove is carried out preliminary planarization again, at last with the silicon thin layer removal of high-temperature thermal oxidation method after cmp.Because the silicon layer to flute surfaces carries out high-temperature thermal oxidation, can make the silicon layer on the hard mask be converted into oxide layer fully; Can thoroughly remove oxide layer and hard mask with wet etching or dry etching again.Therefore, the present invention can effectively solve the planarization problem after the trench fill, obtains the good flute surfaces of planarization.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 is a super junction MOSFET device cell sketch map;

Fig. 2 is first kind of P type and N type semiconductor thin layer manufacturing approach sketch map of alternately arranging;

Fig. 3 is second kind of P type and N type semiconductor thin layer manufacturing approach sketch map of alternately arranging;

Fig. 4-the 10th, method one embodiment process flow diagram of the present invention;

Figure 11 is method one an embodiment control flow chart of the present invention.

Embodiment

In conjunction with shown in Figure 11, in one embodiment, the process of planarization comprises the steps: after the said trench fill

Step 1, epitaxial growth.Referring to shown in Figure 4, adopt to have highly doped N type silicon substrate 51, the low-doped N type thick epitaxial layer 52 of growth on this silicon substrate 51, the thickness of epitaxial loayer 52 and have first doping type between 10.0 μ m-100.0 μ m.

Step 2, hard mask growth.Referring to Fig. 5, adopt methods such as epitaxial growth, thermal oxidation or deposit to form one deck or a few layer dielectric on the surface of said epitaxial loayer 52, as the hard mask 56 of etching groove.Said hard mask is at least a in silica, silicon nitride and the silicon oxynitride, thickness be 500 -20000

Step 3, etching groove.Referring to shown in Figure 6, in said epitaxial loayer 52, etching the degree of depth is 10.0-100.0 μ m, and width is the groove 55 of 1.0-10.0 μ m.Groove 55 etchings can after the etching be removed photoresist with photoresist as etching barrier layer; Also available hard mask 56 is as etching barrier layer, hard mask 56 all or part of reservations after groove 55 etchings.

Step 4, extension are filled.Referring to Fig. 7, in said groove 55, carry out P type growing epitaxial silicon and form silicon epitaxy layer 53, groove 55 complete filling.Certainly, the epitaxial loayer 52 that is grown on the silicon substrate 51 also can be the P type, and what in groove 55, carry out the growing epitaxial silicon filling this moment then should be the N type.The silicon epitaxy layer 53 of growth has second doping type in the groove 55.

Step 5, groove is carried out preliminary planarization.Referring to Fig. 8, behind the growing epitaxial silicon complete filling groove 55, because superfluous growth, the silicon epitaxy layer 53 at groove 55 tops can be higher than hard mask 56, and also has certain thickness silicon layer formation on the hard mask 56 of groove 55 both sides.With chemical and mechanical grinding method preliminary planarization is carried out on groove 55 surfaces.Initial flattened hard mask 56 on the silicon layer has a thickness 0 <img file = "BSA00000179313000043.GIF" he = "51" img-content = "drawing" img-format = "tif" inline = "yes" orientation = "portrait" wi = "31" /> <-5000 <img file = "BSA00000179313000044.GIF" he = "52" img-content = "drawing" img-format = " tif " inline =" yes " orientation =" portrait " wi =" 31 " /> between.

Step 6, high-temperature thermal oxidation.Referring to Fig. 9, groove 55 surperficial silicon layers are carried out high-temperature thermal oxidation, make the silicon layer on the hard mask 56 be converted into oxide layer 57 fully through behind the high-temperature oxydation.

Step 7, referring to shown in Figure 10, adopt wet etching or dry etching to remove the oxide layer 57 and hard mask 56 on epitaxial loayer 52 and groove 55 surfaces.

More than through embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.

Claims

1. the process of planarization after the trench fill is characterized in that, may further comprise the steps:

Step 1, one deck epitaxial loayer of on silicon substrate, growing;

Step 2, on said epitaxial loayer, carry out the growth of hard mask;

Step 3, in said epitaxial loayer, form groove;

Step 5, said flute surfaces is carried out preliminary planarization with cmp;

2. process as claimed in claim 1 is characterized in that: the thickness of epitaxial loayer described in the step 1 is 10.0-100.0 μ m, and has first doping type.

3. process as claimed in claim 1; It is characterized in that: hard mask described in the step 2 is at least a in silica, silicon nitride and the silicon oxynitride, thickness be 500

-20000

4. process as claimed in claim 1 is characterized in that: the width of groove described in the step 3 is 1.0-10.0 μ m, and the degree of depth is 10.0-100.0 μ m; Hard mask part reservation at least behind the etching groove.

5. process as claimed in claim 1 is characterized in that: behind the complete filling of growing epitaxial silicon described in the step 4 groove, the height of silicon is higher than hard mask in its groove, and on the hard mask in groove both sides certain thickness silicon layer growth is arranged; Silicon epitaxy layer in the groove has second doping type.

6. process as claimed in claim 1 is characterized in that: described in the step 5 behind the cmp on the hard mask remaining silicon layer thickness be 0

＜-5000

7. process as claimed in claim 1 is characterized in that: the silicon layer behind the high-temperature thermal oxidation described in the step 6 on the hard mask is converted into oxide layer fully.