CN102322968B - 沟槽式多晶硅二极管 - Google Patents

沟槽式多晶硅二极管 Download PDF

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CN102322968B
CN102322968B CN201110147177.0A CN201110147177A CN102322968B CN 102322968 B CN102322968 B CN 102322968B CN 201110147177 A CN201110147177 A CN 201110147177A CN 102322968 B CN102322968 B CN 102322968B
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diode
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CN102322968A (zh
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陈曲飞
罗伯特.徐
凯尔.特里尔
戴娃.帕塔纳亚克
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Vishay Siliconix Inc
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Abstract

本发明包括温度传感器，其包括被电连接到第一管脚和第二管脚的第一沟槽式多晶硅二极管，其中第一沟槽多晶硅二极管的一部分位于N-(P-)型外延区域的表面之下；和被连接到所述第一管脚和所述第二管脚的第二沟槽式多晶硅二极管，其中第二沟槽式多晶硅二极管的一部分位于N-(P-)型外延区域的所述表面之下，并且其中第一沟槽式多晶硅二极管和第二沟槽式多晶硅二极管被反并联地连接，能够通过在第一管脚和第二管脚之间测量的电压来确定温度。

Description

沟槽式多晶硅二极管
本申请是申请日为2006年12月22日、申请号为200680050082.4、发明名称为“沟槽式多晶硅二极管”的专利申请的分案申请。
技术领域
金属氧化物半导体(MOS)集成电路(IC)和分立式功率MOS晶体管通过MOS晶体管的栅极接收输入信号。如果高电压输入信号被施加到栅极，栅极氧化层可能不能承受该高电压而击穿。当人或机器运输半导体器件时，可能会产生高于正常输入电压的电压，导致对该半导体器件的损坏。
然而，电压异常高的原因有很多种。例如，当从塑料包装中取出IC或分立式MOS晶体管时，由于表面之间的摩擦会产生电荷。静电的范围可从几百伏到几千伏。如果这种高压被施加到IC或分立封装的管脚，封装内的晶体管的栅极氧化层可能会发生电压击穿，这会导致晶体管失效。结果，可能会使整个IC或分立式MOS晶体管失效。
为了防止这种对MOS晶体管的损坏，向IC或分立式MOS晶体管封装的管脚连接保护电路。这种保护电路典型地连接在每个输入/输出(I/O)基垫元件(input/output pad)与集成电路之间。保护电路被设计成在I/O基垫元件被施以高电压的时候导通。这样，这些保护电路提供例如接地的电气路径，以安全地将由高峰值电压引起的高峰值电流释放出去，并保护MOS晶体管免遭栅极氧化层损坏。
对于表面成形(surface-formed)的多晶硅齐纳二极管来说，优选的是沟槽式功率MOS晶体管中的ESD(静电放电)保护。然而，随着半导体IC和器件的特征尺寸(feature size)变小，具有平面形状以便于光刻模块印刷小的特征(feature)从而实现较高的单元密度是非常重要的。传统表面形成的多晶硅齐纳二极管会增加表面拓扑，这限制了在光刻期间印刷小的特征的能力。
发明内容
本发明的实施例包括一种制造沟槽式多晶硅二极管的方法。该方法包括形成N-(P-)型外延层，在该N-(P-)型外延区域中形成沟槽并沿着该沟槽生长出厚的氧化绝缘层，该N-(P-)型外延层取决于N+(P+)型基板上的N沟道(P沟道)沟槽式MOSFET的漏极-源极击穿电压要求。该方法还包括用多晶硅填充沟槽，并对多晶硅进行回蚀，形成沟槽的顶面，并在沟槽式多晶硅区域中形成二极管，其中，二极管的一部分低于沟槽的顶面。
本发明的实施例还包括一种包括静电放电保护的沟槽式MOSFET。该沟槽式MOSFET包括N-(P-)型外延区域，该N-(P-)型外延区域取决于N+(P+)型基板上的N沟道(P沟道)沟槽式MOSFET的漏极-源极击穿电压要求。在N-(P-)型外延区域中形成沟槽，其中，该沟槽包括顶面。栅极氧化层生长在沟槽上，并且栅极多晶硅沉积并被回蚀以形成沟槽式MOSFET的栅极。沟槽式MOSFET还包括P(N)型主体，该P(N)型主体形成于N-(P-)型外延区域中，并且在该P(N)型主体中形成N+(P+)型源极。
本发明的沟槽式多晶硅二极管通过将多晶硅齐纳二极管结构置于硅中，极大地减小了硅表面的拓扑。传统的多晶硅齐纳二极管结构位于硅的表面上并且增加了硅的拓扑，限制了光刻的特征尺寸并减小了单元密度。在本发明的一个实施例中，修改条形源极块(strip sourceblock)可以确定多晶硅齐纳二极管结构的不同的击穿电压。在本发明的一个实施例中，并行排列更多个沟槽式多晶硅齐纳二极管单元可以确定不同的ESD等级。在本发明的一个实施例中，沟槽式多晶硅二极管也可以用于保护、箝位和温度感测功能。
本发明的实施例包括一种制造沟槽式多晶硅二极管的方法。该方法包括在N+(P+)型基板上形成N-(P-)型外延区域，和在N-(P-)型外延区域中形成沟槽。该方法还包括在沟槽中形成绝缘层，用多晶硅填充沟槽，形成沟槽的顶面。该方法还包括在沟槽中形成P+(N+)型掺杂的多晶硅区域和N+(P+)型掺杂的多晶硅区域，和在沟槽中形成二极管，其中，二极管的一部分低于沟槽的顶面。
附图说明
附图结合在说明书中并构成说明书的一部分，附图示出了本发明的各实施例，与说明书一起用来解释本发明的原理。
图1A、1B、1C、1D、1E、1F、1G、1H、1I、1J、1K和1L示出了根据本发明的实施例的制造包括沟槽式多晶硅二极管的沟槽式MOSFET的示例性方法中执行的各个步骤；
图2A示出了根据本发明的实施例的示例性的单条形沟槽式多晶硅齐纳二极管单元的布局；
图2B示出了根据本发明的实施例的单条形沟槽式多晶硅齐纳二极管的第一横截面视图；
图2C示出了根据本发明的实施例的单条形沟槽式多晶硅齐纳二极管的第二横截面视图；
图3A示出了根据本发明的实施例的双条形沟槽式多晶硅齐纳二极管单元布局，该双沟槽式多晶硅齐纳二极管的击穿电压为单条形沟槽式多晶硅齐纳二极管的二倍。沟槽式多晶硅齐纳二极管的击穿电压越高，条形沟槽式多晶硅齐纳二极管单元布局就可以设计得越多；
图3B示出了根据本发明的实施例的双条形沟槽式多晶硅齐纳二极管的横截面视图；
图3C是根据本发明的实施例的用于ESD保护的示例性单级沟槽式多晶硅齐纳二极管的示意图；
图3D是根据本发明的实施例的用于ESD保护的示例性双级多晶硅齐纳二极管的示意图；
图4是根据本发明的实施例的用于制造沟槽式多晶硅二极管的示例性方法的处理流程图；
图5A是根据本发明的实施例的包括垂直沟槽二极管的示例性的感测温度的示意性布局的顶视图；
图5B示出了根据本发明的实施例的包括垂直沟槽式多晶硅二极管的温度感测电路。
具体实施方式
现具体参照本发明的各实施例，附图中示出了这些实施例的例子。尽管以下将结合这些实施例来描述本发明，但应该理解，这些实施例不意欲将本发明限制于这些实施例。相反，本发明将要覆盖所有可替代实施方式、修改和等效体，可替代实施方式、修改和等效体可以包括在本发明的精神和范围内，正如所附的权利要求所定义的那样。而且，在以下的本发明的详细说明中，为了使读者能透彻理解本发明，描述了大量的具体细节。然而，应当理解，本发明的实施可以不使用这些具体细节来实现。在其它例子中，对于公知的方法、步骤、组件和电路并没有进行详细描述，以免对本发明造成不必要的混淆。
本发明的实施例包括沟槽式多晶硅二极管的方法和结构。本发明的沟槽式多晶硅二极管通过将沟槽式多晶硅二极管结构置于硅中，极大地减少了硅表面的拓扑。传统的多晶硅二极管结构被置于硅的表面上，增加了硅的拓扑，减小了单元密度。在本发明的一个实施例中，修改二极管注入法可确定沟槽式多晶硅齐纳二极管结构的不同的击穿电压。在本发明的一个实施例中，修改串联的背对背二极管的数量也可以确定沟槽式多晶硅齐纳二极管结构的不同的击穿电压。在本发明的一个实施例中，形成沟槽式多晶硅齐纳二极管用于ESD保护。在本发明的一个实施例中，可以并联更多个沟槽式多晶硅齐纳二极管单元，以确定ESD等级。在本发明的一个实施例中，沟槽式多晶硅二极管可用于温度感测功能。在本发明的一个实施例中，沟槽式多晶硅齐纳二极管可用于源极-漏极过电压保护和箝位功能。
图1A、1B、1C、ID、1E、1F、1G、1H、1I、1J、1K和1L示出了根据本发明的实施例的在用于制造垂直沟槽式多晶硅二极管的示例性方法中执行的各步骤。
在图1A中，在传统的N+(P+)型掺杂的基板101上形成N-(P-)型掺杂的外延区域102。在N-(P-)型掺杂的外延区域102上形成氧化垫103。在本发明的一个实施例中，氧化垫的厚度约为300埃。在本发明的一个实施例中，氧化垫(oxide pad)包括二氧化硅(SiO2)。在氧化垫103上形成氮化硅层104。在本发明的一个实施例中，氮化硅层104的厚度约为两千埃。
光刻胶层105用于遮蔽沟槽120的位置。图1A示出了沟槽形成之后的半导体器件。在本发明的一个实施例中，沟槽120是静电放电(ESD)沟槽。在本发明的另一个实施例中，沟槽120是沟槽二极管的用于箝位功能或者用于温度感测功能的部分。
在图1B中，光刻胶层105(见图1A)被去除，并且在沟槽120内部形成绝缘层122。在本发明的一个实施例中，绝缘层包括LOCOS(硅的局部氧化)氧化物。在本发明的一个实施例中，绝缘层的厚度为三千埃。在本发明的一个实施例中，绝缘层122的厚度取决于受保护的器件所需的漏极-源极击穿等级，以将齐纳二极管与受保护的器件很好地隔离开。例如，较厚的绝缘层122相比较薄的绝缘层122提供的隔离等级更高。在本发明的一个实施例中，三千埃的绝缘层122包括的击穿电压(BV)大于40伏。在本发明的一个实施例中，绝缘层122不是形成在氮化硅层104的顶面上。
在图1C中，多晶硅层140沉积以填充沟槽120。在本发明的一个实施例中，多晶硅层140的厚度为1.5微米，并且其厚度可以根据沟槽宽度改变。多晶硅层140沉积在绝缘层122上。在本发明的一个实施例中，多晶硅层沉积在氮化硅层104的表面上。在本发明的该实施例中，氮化硅层104用作蚀刻终止器(etch stop)。图1C示出了回蚀之后的多晶硅层140。剩余的多晶硅140填充沟槽120。在本发明的一个实施例中，沟槽被填充，使得沟槽的顶部与N-(P-)型外延区域的顶层齐平。
在图1D中，氮化硅层104和氧化垫层103被去除。在本发明的一个实施例中，缓冲氧化物蚀刻或者HF蚀刻被用于去除氧化垫层103。
在图1E中，一个或多个MOSFET晶体管沟槽155被形成于邻近二极管(ESD)沟槽120处。沟槽掩模(trench mask)(光刻胶)150遮蔽MOSFET晶体管沟槽155的位置。在本发明的一个实施例中，传统的制造工艺被用于形成MOSFET沟槽155。
在图1F中，光刻胶155被去除，并且形成栅极氧化层160，其沿着MOSFET沟槽155。栅极氧化层160也形成于填充二极管(ESD)沟槽120的多晶硅140的顶部。栅极多晶硅层161沉积在栅极氧化层160上。在本发明的一个实施例中，栅极多晶硅161的厚度约为一微米。在本发明的一个实施例中，可在该步骤执行栅极掺杂。
在图1G中，栅极多晶硅161被回蚀，并且栅极多晶硅161的剩余部分填充MOSFET沟槽155。
在图1H中，掩模170用于保护MOSFET沟槽155免于受到ESD注入171，以形成P+(N+)型的沟槽式多晶硅二极管。可以修改ESD注入，以调整本发明的沟槽式多晶硅二极管的特性。例如，不同的注入量可被用于二极管的不同的击穿电压。
在图1I中，执行主体注入以形成P(N)型主体区域175。在本发明的一个实施例中，主体阻挡掩模被用于形成主体注入区。在本发明的一个实施例中，主体注入是在注入之后执行的。
在图1J中，源极阻挡掩模被用于形成源极注入区，并且形成N+(P+)型硅区域180。同时，源极注入还用于形成沟槽式多晶硅二极管的N+(P+)型多晶硅区域，图1G中的未被阻挡的多晶硅区域140现成为N+(P+)型掺杂区域。
在图1K和1L中，沟槽晶体管155是以传统方式完成的。在图1K中，形成LTO(低温氧化物)加BPSG(硼磷硅玻璃)层181，并且形成源极和栅极电极的图案。在本发明的一个实施例中，在触点注入(contact implant)期间使用触点掩模以形成触点。在触点形成之后，在本发明的一个实施例中，当需要箝位功能时，可以执行箝位注入。
在图1L中，执行镀金属199以完成MOSFET晶体管的源极/漏极侧189和ESD侧190。
图2A示出了根据本发明的实施例的单条形垂直沟槽式多晶硅齐纳二极管单元布局。一个齐纳二极管电极包括金属区域200、N+(P+)型多晶硅区域203和栅极触点204。接地侧206还包括N+(P+)型多晶硅区域203和接地触点214。P+(N+)型多晶硅区域201位于N+(P+)型多晶硅区域203之间。
NPN(PNP)(例如，N+(P+)203、P+(N+)201、N+(P+)203)区域形成本发明的沟槽式多晶硅齐纳二极管。在一个实施例中，本发明的沟槽式多晶硅齐纳二极管被用于ESD保护。在本发明的一个实施例中，多个多晶硅沟槽的齐纳二极管可以被连接(例如，并联)以实现不同的ESD保护等级。
在本发明的另一个实施例中，本发明的沟槽式多晶硅齐纳二极管被用于箝位功能。在本发明的另一个实施例中，本发明的沟槽式多晶硅二极管可用于温度感测。沿着从A 210到A′216的轴切开齐纳二极管，可看到图2A中的沟槽式多晶硅齐纳二极管的横截面视图(如图2B中所示)。
图2B是图2A的垂直沟槽多晶硅二极管的从(图2A的)A 210到A′216的第一横截面。NPN(PNP)形成对应于图2B的沟槽式多晶硅齐纳二极管280。
图2C是图2A的垂直沟槽式多晶硅二极管的从(图2A的)B 211到B′217的第二横截面。
图3A示出了根据本发明的实施例的双条形垂直沟槽式多晶硅齐纳二极管单元布局。栅极侧300包括N+(P+)型多晶硅区域303和栅极触点304。接地侧306包括N+(P+)型多晶硅区域303和接地触点314。两个P+(N+)型多晶硅区域301位于N+(P+)型多晶硅区域203之间。位于两个P+(N+)型多晶硅区域301之间的是另一N+(P+)型多晶硅区域303。NPNPN(PNPNP)区域形成本发明的多个沟槽式多晶硅二极管。在一个实施例中，本发明的多个沟槽式多晶硅二极管被连接并被用于ESD保护。将齐纳二极管沿着从C 310到C′316切开，可观察到图3A的沟槽式多晶硅齐纳二极管的横截面(如图3B所示)。
图3B是图3A的垂直沟槽式多晶硅齐纳二极管的从(图3A的)C 310到C′316的横截面图。NPNPN(PNPNP)形成对应于连接在一起的多个图3B的沟槽式多晶硅齐纳二极管380。
图3C是根据本发明的实施例的包括垂直沟槽式多晶硅齐纳二极管381的单级ESD保护电路380的示意图。
图3D是根据本发明的实施例的包括第一垂直沟槽式多晶硅齐纳二极管391、沟槽多晶硅阻抗和第二垂直沟槽式多晶硅齐纳二极管392的双级ESD保护电路390的示意图。
图4是根据本发明的实施例的用于制造垂直沟槽式多晶硅二极管的示例性方法的流程图。在本发明的一个实施例中，处理400得到的沟槽式多晶硅齐纳二极管被用于ESD保护。在本发明的另一个实施例中，处理400得到的沟槽式多晶硅二极管被用于过电压保护和/或箝位功能。可以理解的是方法400还可用于制造用于温度感测的沟槽式多晶硅二极管。
在步骤402，处理400包括在N+(P+)型基板上形成N-(P-)型外延区域。
在步骤404，处理400包括在N-(P-)型外延区域中形成沟槽，并在其上生长LOCOS氧化物。在本发明的一个实施例中，在步骤404中形成的沟槽是ESD沟槽。在本发明的一个实施例中，可以修改LOCOS氧化物的厚度以支持完成的二极管所需的击穿电压。
在步骤406，处理400包括沉积多晶硅和回蚀多晶硅，其剩余的多晶硅填充在步骤404中所形成的沟槽的顶面。
在步骤408，处理400包括通过进行P+(N+)型ESD注入，在步骤406中所形成的沟槽多晶硅中形成P+(N+)型多晶硅区域。在本发明的一个实施例中，可以修改P+(N+)型ESD注入量，以实现完成的二极管所需的击穿电压和ESD等级。
在步骤410，处理400包括通过进行N+(P+)型源极注入，在步骤406中所形成的沟槽多晶硅中形成N+(P+)型多晶硅区域。
在步骤412，处理400包括在主体区域中形成二极管，其中二极管的一部分低于沟槽的顶面。在本发明的一个实施例中，执行一系列注入形成二极管。执行第一ESD注入以掺杂沉积在沟槽中的多晶硅(形成P+(N+)型多晶硅区域)，执行第二源极注入以掺杂沉积在沟槽(形成N+(P+)型多晶硅区域)中的多晶硅。
图5A是根据本发明的实施例的用于感测温度的示意性布局的顶视图500a。温度传感器500a包括垂直沟槽式多晶硅二极管510和520。沟槽式多晶硅二极管510和520被反并联地电连接，并且被电连接到管脚一502和管脚二504。
沟槽二极管510包括N+型多晶硅区域512的区域和P+型多晶硅区域511的区域。二极管510通过触点513被电连接到管脚一502，并通过触点514被电连接到管脚二504。
沟槽二极管520包括N+型多晶硅区域521的区域和P+型多晶硅区域522的区域。二极管520通过触点523被电连接到管脚一502，并通过触点524被电连接到管脚二504。
可通过测量管脚一502和管脚二504之间的电压来确定温度。可以使用查询表来确定多个电压对应的温度。
图5B示出了图5A的示例性电路500b。沟槽式多晶硅二极管510和520被电连接到管脚一502和管脚二504。可以测量管脚一502和管脚二504之间的电压，并可通过例如查询表来确定对应的温度。可以理解的是，根据本发明的实施例，可以使用对给定电压提取对应的温度的任何数量的方法。
以上已经描述了本发明的实施例，垂直沟槽式多晶硅二极管。虽然在特定实施例中描述了本发明，但应该理解，本发明不应被认为限制于这些实施例，而是应当根据以下的权利要求来解释本发明。

Claims (3)

1.一种温度传感器，包括：
第一沟槽式多晶硅二极管，其被电连接到第一管脚和第二管脚，其中所述第一沟槽式多晶硅二极管的一部分位于N-或P-型外延区域的表面之下；和
第二沟槽式多晶硅二极管，其被连接到所述第一管脚和所述第二管脚，其中所述第二沟槽式多晶硅二极管的一部分位于所述N-或P-型外延区域的所述表面之下，
其中所述第一沟槽式多晶硅二极管和所述第二沟槽式多晶硅二极管被反并联地连接，其中能够通过在所述第一管脚和所述第二管脚之间测量的电压来确定温度。
2.如权利要求1所述的温度传感器，还包括查询表，所述查询表包括多个电压和对应的温度值。
3.如权利要求1-2中任一项所述的温度传感器，其中所述第一和第二沟槽式多晶硅二极管包括P+型多晶硅区域和N+型多晶硅区域。
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