CN102324428A - One time programmable storage unit and manufacturing method thereof as well as one time programmable storage array - Google Patents
One time programmable storage unit and manufacturing method thereof as well as one time programmable storage array Download PDFInfo
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- CN102324428A CN102324428A CN201110219592A CN201110219592A CN102324428A CN 102324428 A CN102324428 A CN 102324428A CN 201110219592 A CN201110219592 A CN 201110219592A CN 201110219592 A CN201110219592 A CN 201110219592A CN 102324428 A CN102324428 A CN 102324428A
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Abstract
The invention relates to a one time programmable storage unit and a manufacturing method thereof as well as a one time programmable storage array. By virtue of a structure composed of a substrate, dielectric layers and polycrystalline silicon or polycrystalline silicon-germanium layers arranged orderly from bottom to top, a cheap one time programmable storage unit and a manufacturing method thereof are provided. The storage unit comprises a capacitor and a MOS (Metal Oxide Semiconductor) transistor. The capacitor comprises a first electrode, the dielectric layer and a second electrode, wherein the first electrode is formed by a doped region on a semiconductor substrate or a conducting material layer on an insulating substrate, and the second electrode is formed by a first polycrystalline silicon or polycrystalline silicon-germanium layer. An active layer of the MOS transistor is located on a second dielectric layer which is simultaneously formed on the semiconductor substrate or the insulating substrate through the same technology as that for the first dielectric layer, and the active layer is formed by a second polycrystalline silicon or polycrystalline silicon-germanium layer which is formed by the same technology as that of the first polycrystalline silicon or polycrystalline silicon-germanium layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to One Time Programmable (One-Time-Programmable, OTP) memory cell, the method that comprises the storage device of this memory cell and make said one-time programmable memory cell.
Background technology
The disposable programmable storage device is a Nonvolatile memory devices, is characterized in the one-time programming stored information, even power cut-off information also can forever be preserved.Because technology is simple, cheap, the disposable programmable storage device is widely used in various semiconductor products.The example of the memory cell of disposable programmable storage device comprises; For example propose in the United States Patent(USP) No. 5943264 by a nmos pass transistor and the memory cell that the PN junction series connection constitutes; The memory cell that capacitor that for example proposes in the United States Patent(USP) No. 6215140 and diode constitute, and the memory cell by nmos pass transistor and mos capacitance series connection of United States Patent(USP) No. 6822888 propositions.
Summary of the invention
According to a first aspect of the invention, a kind of one-time programmable memory cell that can be used for storage array is provided, this memory cell comprises:
Comprise first electrode, be positioned at first dielectric layer on first electrode and be positioned at the capacitor of second electrode on said first dielectric layer; This first electrode is formed by the conductive material layer that is formed on the doped region in the Semiconductor substrate or be formed on the dielectric substrate, and said second electrode is formed by first polysilicon or polysilicon germanium layer;
MOS transistor; Comprise active layer and be positioned at gate dielectric layer and the grid conductor on this active layer; The channel region of this MOS transistor is arranged in said active layer and the source region of said gate dielectric layer below and the said active layer that the drain region lays respectively at said channel region both sides; Said active layer is positioned at said first dielectric layer and adopts identical technology to be formed on simultaneously on second dielectric layer on the said Semiconductor substrate or on the dielectric substrate, and said active layer is by forming with second polysilicon or polysilicon germanium layer that said first polysilicon or polysilicon germanium layer adopt identical technology to form simultaneously; And
Be formed on the interlayer insulating film on said capacitor and the said MOS transistor,
Second electrode of said capacitor is electrically connected with the conductive interconnection that is formed on the said interlayer insulating film through the conductive path that is formed in the said interlayer insulating film with the drain region of said MOS transistor.
Alternatively, said Semiconductor substrate is the substrate that high-purity metallurgical grade silicon wafer, technology silicon chip clout or low-cost polysilicon form, and said dielectric substrate is formed by glass or polyester material.
Alternatively, said first and second polysilicon layers are formed for the 50nm-100um polysilicon by the particle size that forms through the laser annealing amorphous silicon.
According to a second aspect of the invention, a kind of One Time Programmable storage array that comprises aforesaid one-time programmable memory cell also is provided.
According to a third aspect of the invention we, a kind of method of making one-time programmable memory cell is provided, this one-time programmable memory cell comprises capacitor and MOS transistor, and this method comprises:
The part of Semiconductor substrate is carried out ion inject, to form doped region as first electrode of said capacitor;
Dielectric layer deposition on said Semiconductor substrate;
On said dielectric layer, form polysilicon layer or polysilicon germanium layer;
Said polysilicon layer of patterning or polysilicon germanium layer, with the first and the second portion of the separation that forms said polysilicon layer or polysilicon germanium layer, said first is as second electrode of said capacitor;
On said second portion, form gate-dielectric and grid conductor;
With said grid conductor is mask, the second portion of said polysilicon layer or polysilicon germanium layer is carried out ion inject, with source region and the drain region that forms said MOS transistor; And
Form interlayer insulating film;
Formation run through said interlayer insulating film arrive said polysilicon layer or polysilicon germanium layer first first conductive path with run through second conductive path that said interlayer insulating film arrives the drain region of said MOS transistor;
On said interlayer insulating film, form the conductive interconnection that connects said first conductive path and second conductive path.
Alternatively, said Semiconductor substrate is the substrate that high-purity metallurgical grade silicon wafer, technology silicon chip clout or low-cost polysilicon form.
According to a forth aspect of the invention, the method for another kind of manufacturing one-time programmable memory cell is provided, this one-time programmable memory cell comprises capacitor and MOS transistor, and this method comprises:
On the part of dielectric substrate, form conductive material layer, with first electrode as said capacitor;
On said dielectric substrate and said conductive material layer, form dielectric layer;
On said dielectric layer, form polysilicon layer or polysilicon germanium layer;
Said polysilicon layer of patterning or polysilicon germanium layer, with the first and the second portion of the separation that forms said polysilicon layer or polysilicon germanium layer, said first is as second electrode of said capacitor;
On said second portion, form gate-dielectric and grid conductor;
With said grid conductor is mask, the second portion of said polysilicon layer or polysilicon germanium layer is carried out ion inject, and with source region and the drain region that forms said MOS transistor, and
Form interlayer insulating film;
Formation run through said interlayer insulating film arrive said polysilicon layer or polysilicon germanium layer first first conductive path with run through second conductive path that said interlayer insulating film arrives the drain region of said MOS transistor;
On said interlayer insulating film, form the conductive interconnection that connects said first conductive path and second conductive path.
In the method aspect third and fourth according to the present invention; Alternatively; Be mask with said grid conductor; The second portion of said polysilicon layer or polysilicon germanium layer is carried out ion inject, during with the drain region, the first to said polysilicon layer or polysilicon germanium layer carries out the ion injection simultaneously with the source region that forms said MOS transistor.
In the method aspect third and fourth according to the present invention, alternatively, comprise at the said polysilicon layer of formation on the said dielectric layer: on said dielectric layer, form amorphous silicon layer, this amorphous silicon layer of annealing is to form polysilicon layer.Further alternatively, this amorphous silicon layer of annealing comprises to form polysilicon layer: this amorphous silicon layer of laser annealing is the 50nm-100um polysilicon layer to form particle size.
In one-time programmable memory cell according to the present invention; Owing to can adopt relatively inexpensive material; For example high-purity metallurgical grade silicon wafer, technology silicon chip clout, low-cost polysilicon, glass, polyester material etc. as substrate, make manufacturing cost reduce greatly.
Through reading detailed description and the appended claims below in conjunction with accompanying drawing, feature and advantage of the present invention will be more obvious.
Description of drawings
Fig. 1 a shows the schematic circuit that can use according to the part of an exemplary memory array of one-time programmable memory cell of the present invention.
Fig. 1 b shows the schematic circuit that can use according to the part of another exemplary memory array of one-time programmable memory cell of the present invention.
Fig. 2 shows the schematic sectional view according to a kind of structure of memory cell of the present invention.
Fig. 3 a-3e shows the schematic cross section in each stage of illustrative methods of the structure of making memory cell shown in Figure 2.
Fig. 4 shows the schematic cross section that after the step shown in Fig. 3 a-3e, has formed the structure behind interlayer insulating film, conductive path and the conductive interconnection.
Fig. 5 a-5d shows the schematic cross section in another each stage of illustrative methods of the structure of making memory cell shown in Figure 2.
Fig. 6 shows the schematic cross section that after the step shown in Fig. 5 a-5d, has formed the structure behind interlayer insulating film, conductive path and the conductive interconnection.
Fig. 7 shows the schematic sectional view according to the another kind of structure of one-time programmable memory cell of the present invention.
Fig. 8 a-8d shows the schematic cross section in each stage of illustrative methods of the structure of making memory cell shown in Figure 7.
Fig. 9 shows the schematic cross section that after the step shown in Fig. 8 a-8d, has formed the structure behind interlayer insulating film, conductive path and the conductive interconnection.
Embodiment
In order to make technical scheme provided by the invention clear more and understand, below with reference to accompanying drawing and combine specific embodiment, the present invention is described in more detail.Accompanying drawing is schematically, might not draw in proportion, runs through the identical Reference numeral of accompanying drawing and representes same or analogous part.In order to make the present invention clearer, device architectures more well known to those skilled in the art (for example, be formed on gate dielectric layer and the grid conductor sidewall spacer) and processing step omit at this.
The illustrative circuitry of Fig. 1 a illustrates the part that can use according to an exemplary memory array 1000 of disposable programmable property memory cell 1111 of the present invention.Memory cell 1111 comprises MOS transistor 1101 and capacitor 1102.The grid of MOS transistor 1101 is connected to word line WL1, and source electrode is connected to earth potential Gnd, and drain electrode is connected with an electrode of capacitor 1102.Another electrode of capacitor 1102 is connected to bit line BL1.Writing and reading of storage array 1000 shown in Fig. 1 a is well known in the art, this no longer tired stating.
The illustrative circuitry of Fig. 1 b illustrates the part that can use according to another exemplary memory array 2000 of one-time programmable memory cell 1111 of the present invention.In this storage array 2000, the grid of the MOS transistor 1101 of memory cell 1111 is connected to word line WL1, and source electrode is connected to bit line BL1, and drain electrode is connected with an electrode of capacitor 1102.Another electrode of capacitor 1102 is connected to line program PRG1.Writing and reading of storage array 2000 shown in Fig. 1 b is well known in the art, this no longer tired stating.
Fig. 2 shows the schematic sectional view according to a kind of structure of memory cell 1111 of the present invention.This memory cell 1111 comprises the isolated M OS transistor 1101 and capacitor 1102 that is formed on the Semiconductor substrate 100.Said MOS transistor 1101 comprises: be positioned at polysilicon or polycrystalline germanium silicon layer 106 ' on the dielectric layer 104 ' on the said Semiconductor substrate 100; Be positioned at gate dielectric layer 108 and grid conductor 110 on said polysilicon or the polycrystalline germanium silicon layer 106 '; The channel region of said MOS transistor 1101 is arranged in the said polysilicon of said gate dielectric layer 108 belows or the part of polycrystalline germanium silicon layer 106 ', and source region and drain region lay respectively at the both sides of said channel region.Said capacitor 1102 comprises as the doped region 102 in the said Semiconductor substrate 100 of first electrode, the dielectric layer 104 on the said doped region 102 and is used as polysilicon or the polycrystalline germanium silicon layer 106 on the said dielectric layer 104 of second electrode.Said dielectric layer 104 and 104 ' uses identical manufacturing process to form simultaneously, and said polysilicon or polycrystalline germanium silicon layer 106,106 ' use identical manufacturing process to form simultaneously.
Being connected of second electrode of being connected of being connected of the grid of MOS transistor 1101 and word line WL1, source electrode and earth potential Gnd (or bit line), drain electrode and capacitor 1102; And being connected of first electrode of capacitor 1102 and bit line BL1 (or line program) can be through forming interlayer insulating film, running through the conductive path of interlayer insulating film and the conductive interconnection (not shown) on the interlayer insulating film is realized; These all are as known in the art, therefore this no longer tired stating.
Said Semiconductor substrate 100 can adopt cheap silicon substrate, the substrate that for example high-purity metallurgical grade (UMG) silicon wafer, technology silicon chip clout, low-cost polysilicon etc. form.Said doped region 102 can be P
+Doped region or N
+Doped region, doping content is preferably 1e20-1e22cm
-3Said dielectric layer 104 (104 ') can be by silica, silicon nitride, silicon oxynitride, silicon oxynitride, HfSiO
x, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, SrTiO
3, LaAlO
3Or it is combined to form, and thickness is preferably 1nm-300nm.Preferably, said polysilicon or polycrystalline germanium silicon layer 106 (106 ') are formed by the bigger polysilicon of particle size.Said particle size can be 50nm-100um.In a specific instance, said particle size is 0.3-10um.In another specific instance, said particle size is 1um.The thickness of said polysilicon or polycrystalline germanium silicon layer 106 (106 ') is 5nm-200nm.Said gate dielectric layer 108 can be by silica, silicon nitride, silicon oxynitride, silicon oxynitride, HfSiO
x, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, SrTiO
3, LaAlO
3Or it is combined to form.Said grid conductor 110 can be formed by DOPOS doped polycrystalline silicon or any suitable metal (for example, Ti, W, Al etc.).
An illustrative methods of the structure of making memory cell 1111 shown in Figure 2 is described below in conjunction with Fig. 3 a-3e.
At first, shown in Fig. 3 a, be infused in through ion and form doped region 102 in the part of Semiconductor substrate 100, first electrode of the capacitor that this doped region 102 is used for forming.
Next, shown in Fig. 3 b, on said Semiconductor substrate 100, form dielectric layer 104, polysilicon or polycrystalline germanium silicon layer 106 and sacrifice layer 101 successively.Said dielectric layer 104 common process such as MOCVD (metal-organic chemical vapor deposition equipment), PECVD (plasma activated chemical vapour deposition), ALCVD (atomic layer chemical vapor deposition), sputter, electron beam evaporation etc. capable of using, cvd silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, HfSiO
x, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, SrTiO
3, LaAlO
3Or its combination and forming.Form said polysilicon or polycrystalline germanium silicon layer 106 can comprise: deposition one amorphous silicon layer on said dielectric layer 104, this amorphous silicon layer of crystallization is to form polysilicon or polycrystalline germanium silicon layer 106.This crystallization for example thermal annealing capable of using, laser annealing or infrared radiation annealing realize.Preferably, the temperature of laser annealing is about 1,000 degree, and the time is about a few to tens of nanoseconds.Preferably, form the bigger polysilicon of particle size, for example particle size is the polysilicon of 50nm-100um.In a specific instance, said particle size is 0.3-10um.In another specific instance, said particle size is 1um.The thickness of this polysilicon or polycrystalline germanium silicon layer 106 is preferably 5nm-200nm.Said sacrifice layer 101 for example can be formed by silicon nitride.
Then; Shown in Fig. 3 c; Adopt the graphical said sacrifice layer of conventional photoetching and etch process 101, polysilicon or polycrystalline germanium silicon layer 106 and dielectric layer 104; To form by said sacrifice layer 101, polysilicon or polycrystalline germanium silicon layer 106 and the platform A and the B that separate that dielectric layer 104 constitutes, be respectively applied for and in subsequent step, form said capacitor and MOS transistor, the projection of said platform A on substrate falls in the scope of said doped region 102.
Next, dielectric layer deposition 103 is utilized the resulting structure of CMP technology planarization, up to the said sacrifice layer 101 of removal, thereby forms the structure shown in Fig. 3 d.Expose portion at substrate 100 described in Fig. 3 d is coated with dielectric layer 103, and this dielectric layer 103 flushes with said polysilicon or polycrystalline germanium silicon layer 106.Preferably, said dielectric layer 103 is finer and close than said dielectric layer 104.
Then; Adopt deposition well known in the art and photoetching and etch process; On said platform B, forming gate dielectric layer 108 and grid conductor 110, shown in Fig. 3 e, and is the doping that mask carries out the source region and the drain region of MOS transistor with grid conductor 110; Optional, can be simultaneously the said polysilicon or the polycrystalline germanium silicon layer of second electrode that constitutes capacitor be carried out identical doping.
After accomplishing the step shown in Fig. 3 a-3e; Can be according to method well known in the art; On resulting structure, form interlayer insulating film; In said interlayer insulating film, form conductive path, and on said interlayer dielectric, form the conductive interconnection that connects conductive path according to the connection needs of side circuit.Fig. 4 schematically shows the cross-sectional view that has formed interlayer insulating film 112, conductive path 114,116,118,120 and conductive interconnection 122 back resulting structures.
Another illustrative methods of the structure of making memory cell 1111 shown in Figure 2 is described below in conjunction with Fig. 5 a-5d.
At first, shown in Fig. 5 a, be infused in through ion and form doped region 102 in the part of Semiconductor substrate 100.
Next, shown in Fig. 5 b, on said Semiconductor substrate 100, form dielectric layer 104 and polysilicon or polycrystalline germanium silicon layer 106 successively.The formation technology of said dielectric layer 104 and polysilicon or polycrystalline germanium silicon layer 106, material are identical with reference to the described step of Fig. 3 b with the front, no longer repeat at this.
Then, shown in Fig. 5 c, said polysilicon of patterning or polysilicon germanium layer 106 with platform A ' and the B ' that form to separate, are respectively applied for second electrode of the capacitor that formation will form and the active area of MOS transistor.For example, can utilize photoetching well known in the art and etching technique with respect to said dielectric layer 104 optionally said polysilicon of etching or polycrystalline germanium silicon layer 106.
Next; Dielectric layer deposition 108 conformally on the structure shown in Fig. 5 c; This dielectric layer 108 is as the gate-dielectric of the MOS transistor 1101 that will form; Said dielectric layer 108 tops on said platform B ' form grid conductor 110 afterwards, shown in Fig. 5 d, and are the doping that mask carries out the source region and the drain region of MOS transistor with grid conductor 110; Optional, can be simultaneously the said polysilicon or the polycrystalline germanium silicon layer of second electrode that constitutes said capacitor 1102 be carried out identical doping.
After accomplishing the step shown in Fig. 5 a-5d; Can be according to method well known in the art; On resulting structure, form interlayer insulating film; In said interlayer insulating film, form conductive path, and on said interlayer dielectric, form the conductive interconnection that connects conductive path according to the connection needs of side circuit.Fig. 6 schematically shows the cross-sectional view that has formed interlayer insulating film 112, conductive path 114,116,118,120 and conductive interconnection 122 back resulting structures.
Fig. 7 shows the schematic sectional view according to the another kind of structure of memory cell 1111 of the present invention.Memory cell 1111 shown in Fig. 7 comprises the isolated M OS transistor 1101 and capacitor 1102 that is formed on the dielectric substrate 200.Said MOS transistor 1101 comprises: be positioned at polysilicon or polycrystalline germanium silicon layer 206 ' on the dielectric layer 204 ' on the said Semiconductor substrate 200; Be positioned at gate dielectric layer 208 and grid conductor 210 on said polysilicon or the polycrystalline germanium silicon layer 206 '; The channel region of said MOS transistor 1101 is arranged in the said polysilicon of said gate dielectric layer 208 belows or the part of polycrystalline germanium silicon layer 206 ', and source region and drain region lay respectively at the both sides of said channel region.Said capacitor 1102 comprise as first electrode 202 on the said Semiconductor substrate 200 of first electrode, on the said metal electrode 202 dielectric layer 204 and as polysilicon or polycrystalline germanium silicon layer 206 on the said dielectric layer 204 of second electrode.Said first electrode 202 can be formed by metal or DOPOS doped polycrystalline silicon.Said dielectric layer 204 and 204 ' uses identical manufacturing process to form simultaneously, and said polysilicon or polycrystalline germanium silicon layer 206,206 ' use identical manufacturing process to form simultaneously.
The difference of the structure of the memory cell 1111 shown in Fig. 7 and structure shown in Figure 2 only is: be employed in metal or doped polysilicon layer on the dielectric substrate 200 as first electrode 202 of capacitor 1102.Said dielectric substrate 200 is for example formed by glass or polyester material, and said metal for example is copper, aluminium or nickel.More than describe and also be applicable to the dielectric layer 204 shown in Fig. 7, polysilicon or polycrystalline germanium silicon layer 206, gate dielectric layer 208 and grid conductor 210 respectively to dielectric layer 104, polysilicon or polycrystalline germanium silicon layer 106 among Fig. 2, gate dielectric layer 108 and grid conductor 110.
Being connected of second electrode of being connected of being connected of the grid of the MOS transistor 1101 shown in Fig. 7 and word line WL1, source electrode and earth potential Gnd (or bit line), drain electrode and capacitor 1102; And being connected of first electrode of capacitor 1102 and bit line BL1 (or line program) can be through forming interlayer insulating film, running through the conductive path of interlayer insulating film and the conductive interconnection (not shown) on the interlayer insulating film is realized; These all are as known in the art, therefore this no longer tired stating.
An illustrative methods of the structure of making memory cell 1111 shown in Figure 7 is described below in conjunction with Fig. 8 a-8d.
At first, shown in Fig. 8 a, on the zone that will form capacitor 1102 on the dielectric substrate 200, form metal electrode layer 202, on this metal electrode layer 202, form dielectric layer 204 and utilize this dielectric layer 204 of technology planarization such as CMP.This metal electrode layer 202 can be through sputter or evaporated metal layer on dielectric substrate 200, graphical afterwards this metal level and forming.
Then, shown in Fig. 8 b, on said dielectric layer 204, form polysilicon or polysilicon germanium layer 206.The polysilicon layer that front combination Fig. 3 b describes or the formation of polycrystalline germanium silicon layer 106 also are applicable to the formation of this polysilicon or polysilicon germanium layer 206.
Next, shown in Fig. 8 c, said polysilicon of patterning or polysilicon germanium layer 206 with platform A ' ' and the B ' ' that form to separate, are respectively applied for second electrode of the capacitor that formation will form and the active area of MOS transistor.
Again next; Dielectric layer deposition 208 conformally on the structure shown in Fig. 8 c; This dielectric layer 208 is as the gate-dielectric of the MOS transistor 1101 that will form; Said dielectric layer 108 tops on said platform B ' ' form grid conductor 210 afterwards, shown in Fig. 8 d, and are the doping that mask carries out the source region and the drain region of MOS transistor with grid conductor 210; Optional, can be simultaneously the said polysilicon or the polycrystalline germanium silicon layer of second electrode that constitutes said capacitor 1102 be carried out identical doping.
After accomplishing the step shown in Fig. 8 a-8d; Can be according to method well known in the art; On resulting structure, form interlayer insulating film; In said interlayer insulating film, form conductive path, and on said interlayer dielectric, form the conductive interconnection that connects conductive path according to the connection needs of side circuit.Fig. 9 schematically shows the cross-sectional view that has formed interlayer insulating film 212, conductive path 214,216,218,220 and conductive interconnection 222 back resulting structures.
Should be appreciated that the MOS transistor described in the preceding text both can also can be the PMOS transistor for nmos pass transistor.Said interlayer insulating film, said conductive path and said conductive interconnection can select various material as known in the art to form, and give an example no longer one by one at this.
More than through exemplary embodiment the method according to manufacturing one-time programmable memory cell of the present invention has been described, yet this is not intended to limit protection scope of the present invention.Any modification of the foregoing description that it may occur to persons skilled in the art that or modification all fall in the scope of the present invention that is defined by the following claims.
Claims (13)
1. one-time programmable memory cell comprises:
Comprise first electrode, be positioned at first dielectric layer on first electrode and be positioned at the capacitor of second electrode on said first dielectric layer; This first electrode is formed by the conductive material layer that is formed on the doped region in the Semiconductor substrate or be formed on the dielectric substrate, and said second electrode is formed by first polysilicon or polysilicon germanium layer;
MOS transistor; Comprise active layer and be positioned at gate dielectric layer and the grid conductor on this active layer; The channel region of this MOS transistor is arranged in said active layer and the source region of said gate dielectric layer below and the said active layer that the drain region lays respectively at said channel region both sides; Said active layer is positioned at said first dielectric layer and adopts identical technology to be formed on simultaneously on second dielectric layer on the said Semiconductor substrate or on the dielectric substrate, and said active layer is by forming with second polysilicon or polysilicon germanium layer that said first polysilicon or polysilicon germanium layer adopt identical technology to form simultaneously; And
Be formed on the interlayer insulating film on said capacitor and the said MOS transistor,
Second electrode of said capacitor is electrically connected with the conductive interconnection that is formed on the said interlayer insulating film through the conductive path that is formed in the said interlayer insulating film with the drain region of said MOS transistor.
2. memory cell according to claim 1, said Semiconductor substrate are the substrates that high-purity metallurgical grade silicon wafer, technology silicon chip clout or low-cost polysilicon form, and said dielectric substrate is formed by glass or polyester material.
3. memory cell according to claim 1 and 2, wherein said first and second polysilicon layers are formed for the 50nm-100um polysilicon by the particle size that forms through the laser annealing amorphous silicon.
4. an One Time Programmable storage array comprises like each described one-time programmable memory cell among the claim 1-3.
5. method of making one-time programmable memory cell, this one-time programmable memory cell comprises capacitor and MOS transistor, this method comprises:
The part of Semiconductor substrate is carried out ion inject, to form doped region as first electrode of said capacitor;
Dielectric layer deposition on said Semiconductor substrate;
On said dielectric layer, form polysilicon layer or polysilicon germanium layer;
Said polysilicon layer of patterning or polysilicon germanium layer, with the first and the second portion of the separation that forms said polysilicon layer or polysilicon germanium layer, said first is as second electrode of said capacitor;
On said second portion, form gate-dielectric and grid conductor;
With said grid conductor is mask, the second portion of said polysilicon layer or polysilicon germanium layer is carried out ion inject, with source region and the drain region that forms said MOS transistor; And
Form interlayer insulating film;
Formation run through said interlayer insulating film arrive said polysilicon layer or polysilicon germanium layer first first conductive path with run through second conductive path that said interlayer insulating film arrives the drain region of said MOS transistor;
On said interlayer insulating film, form the conductive interconnection that connects said first conductive path and second conductive path.
6. method according to claim 5; Be mask wherein with said grid conductor; Second portion to said polysilicon layer or polysilicon germanium layer carries out the ion injection; During with the source region that forms said MOS transistor and drain region, simultaneously the first of said polysilicon layer or polysilicon germanium layer is carried out ion and inject.
7. method according to claim 5, said Semiconductor substrate are the substrates that high-purity metallurgical grade silicon wafer, technology silicon chip clout or low-cost polysilicon form.
8. according to each described method among the claim 5-7, wherein comprise at the said polysilicon layer of formation on the said dielectric layer: on said dielectric layer, form amorphous silicon layer, this amorphous silicon layer of annealing is to form polysilicon layer.
9. method according to claim 8, this amorphous silicon layer of wherein annealing comprises to form polysilicon layer: this amorphous silicon layer of laser annealing is the 50nm-100um polysilicon layer to form particle size.
10. method of making one-time programmable memory cell, this one-time programmable memory cell comprises capacitor and MOS transistor, this method comprises:
On the part of dielectric substrate, form conductive material layer, with first electrode as said capacitor;
On said dielectric substrate and said conductive material layer, form dielectric layer;
On said dielectric layer, form polysilicon layer or polysilicon germanium layer;
Said polysilicon layer of patterning or polysilicon germanium layer, with the first and the second portion of the separation that forms said polysilicon layer or polysilicon germanium layer, said first is as second electrode of said capacitor;
On said second portion, form gate-dielectric and grid conductor;
With said grid conductor is mask, the second portion of said polysilicon layer or polysilicon germanium layer is carried out ion inject, and with source region and the drain region that forms said MOS transistor, and
Form interlayer insulating film;
Formation run through said interlayer insulating film arrive said polysilicon layer or polysilicon germanium layer first first conductive path with run through second conductive path that said interlayer insulating film arrives the drain region of said MOS transistor;
On said interlayer insulating film, form the conductive interconnection that connects said first conductive path and second conductive path.
11. the method for stating according to claim 10; Be mask wherein with said grid conductor; Second portion to said polysilicon layer or polysilicon germanium layer carries out the ion injection; During with the source region that forms said MOS transistor and drain region, simultaneously the first of said polysilicon layer or polysilicon germanium layer is carried out ion and inject.
12. claim 10 or 11 described methods wherein comprise at the said polysilicon layer of formation on the said dielectric layer: on said dielectric layer, form amorphous silicon layer, this amorphous silicon layer of annealing is to form polysilicon layer.
13. method according to claim 12, this amorphous silicon layer of wherein annealing comprises to form polysilicon layer: this amorphous silicon layer of laser annealing is the 50nm-100um polysilicon layer to form particle size.
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| CN105405467A (en) * | 2012-08-21 | 2016-03-16 | 力旺电子股份有限公司 | One-bit Memory Cell For Nonvolatile Memory And Associated Control Method |
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| CN1304547A (en) * | 1999-03-05 | 2001-07-18 | 精工爱普生株式会社 | Method for producing thin film semiconductor device |
| US6822888B2 (en) * | 2001-09-18 | 2004-11-23 | Kilopass Technologies, Inc. | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| CN101752380A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | OTP device |
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2011
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1304547A (en) * | 1999-03-05 | 2001-07-18 | 精工爱普生株式会社 | Method for producing thin film semiconductor device |
| US6822888B2 (en) * | 2001-09-18 | 2004-11-23 | Kilopass Technologies, Inc. | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| CN101752380A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | OTP device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405467A (en) * | 2012-08-21 | 2016-03-16 | 力旺电子股份有限公司 | One-bit Memory Cell For Nonvolatile Memory And Associated Control Method |
| CN105405467B (en) * | 2012-08-21 | 2019-04-19 | 力旺电子股份有限公司 | The control method of a storage unit applied to nonvolatile memory |
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| CN102324428B (en) | 2013-11-27 |
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