CN102324428B - One time programmable storage unit and manufacturing method thereof as well as one time programmable storage array - Google Patents
One time programmable storage unit and manufacturing method thereof as well as one time programmable storage array Download PDFInfo
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- CN102324428B CN102324428B CN2011102195922A CN201110219592A CN102324428B CN 102324428 B CN102324428 B CN 102324428B CN 2011102195922 A CN2011102195922 A CN 2011102195922A CN 201110219592 A CN201110219592 A CN 201110219592A CN 102324428 B CN102324428 B CN 102324428B
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Abstract
The invention relates to a one time programmable storage unit and a manufacturing method thereof as well as a one time programmable storage array. By virtue of a structure composed of a substrate, dielectric layers and polycrystalline silicon or polycrystalline silicon-germanium layers arranged orderly from bottom to top, a cheap one time programmable storage unit and a manufacturing method thereof are provided. The storage unit comprises a capacitor and a MOS (Metal Oxide Semiconductor) transistor. The capacitor comprises a first electrode, the dielectric layer and a second electrode, wherein the first electrode is formed by a doped region on a semiconductor substrate or a conducting material layer on an insulating substrate, and the second electrode is formed by a first polycrystalline silicon or polycrystalline silicon-germanium layer. An active layer of the MOS transistor is located on a second dielectric layer which is simultaneously formed on the semiconductor substrate or the insulating substrate through the same technology as that for the first dielectric layer, and the active layer is formed by a second polycrystalline silicon or polycrystalline silicon-germanium layer which is formed by the same technology as that of the first polycrystalline silicon or polycrystalline silicon-germanium layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to One Time Programmable (One-Time-Programmable, OTP) memory cell, the method that comprises the storage device of this memory cell and manufacture described one-time programmable memory cell.
Background technology
The disposable programmable storage device is Nonvolatile memory devices, is characterized in one-time programming storage information, even power cut-off information also can persistence.Because technique is simple, cheap, the disposable programmable storage device is widely used in various semiconductor products.The example of the memory cell of disposable programmable storage device comprises, for example in U.S. Patent No. 5943264, propose by a nmos pass transistor and the memory cell that PN junction is in series, the memory cell that the capacitor for example proposed in U.S. Patent No. 6215140 and diode form, and the memory cell by nmos pass transistor and mos capacitance series connection of U.S. Patent No. 6822888 propositions.
Summary of the invention
According to a first aspect of the invention, provide a kind of one-time programmable memory cell that can be used for storage array, this memory cell comprises:
Comprise the first electrode, be positioned at the first dielectric layer on the first electrode and be positioned at the capacitor of the second electrode on described the first dielectric layer, this first electrode in being formed on Semiconductor substrate doped region or the conductive material layer be formed on dielectric substrate form, described the second electrode is formed by the first polysilicon or polysilicon germanium layer;
MOS transistor, comprise active layer and be positioned at gate dielectric layer and the grid conductor on this active layer, the channel region of this MOS transistor is arranged in the described active layer that the described active layer of described gate dielectric layer below and source region and drain region lay respectively at described channel region both sides, described active layer is positioned at described the first dielectric layer and adopts identical technique to be formed on simultaneously on the second dielectric layer on described Semiconductor substrate or on dielectric substrate, and described active layer is formed by the second polysilicon or the polysilicon germanium layer with described the first polysilicon or polysilicon germanium layer adopt identical technique to form simultaneously, and
Be formed on the interlayer insulating film on described capacitor and described MOS transistor,
The second electrode of described capacitor is electrically connected to by the conductive interconnection that is formed on the conductive path in described interlayer insulating film and be formed on described interlayer insulating film with the drain region of described MOS transistor.
Alternatively, described Semiconductor substrate is the substrate that high-purity metallurgical grade silicon wafer, technique silicon chip clout or low-cost polysilicon form, and described dielectric substrate is formed by glass or polyester material.
Alternatively, described the first and second polysilicon layers are that the 50nm-100um polysilicon forms by the particle size formed by the laser annealing amorphous silicon.
According to a second aspect of the invention, also provide a kind of One Time Programmable storage array that comprises one-time programmable memory cell as above.
According to a third aspect of the invention we, provide a kind of method of manufacturing one-time programmable memory cell, this one-time programmable memory cell comprises capacitor and MOS transistor, and the method comprises:
A part to Semiconductor substrate is carried out Implantation, to form the doped region as the first electrode of described capacitor;
Dielectric layer deposition on described Semiconductor substrate;
On described dielectric layer, form polysilicon layer or polysilicon germanium layer;
The described polysilicon layer of patterning or polysilicon germanium layer, with first and the second portion of the separation that forms described polysilicon layer or polysilicon germanium layer, described first is as the second electrode of described capacitor;
On described second portion, form gate-dielectric and grid conductor;
The described grid conductor of take is mask, the second portion of described polysilicon layer or polysilicon germanium layer is carried out to Implantation, with source region and the drain region that forms described MOS transistor; And
Form interlayer insulating film;
Formation run through described interlayer insulating film arrive described polysilicon layer or polysilicon germanium layer first the first conductive path and run through the second conductive path that described interlayer insulating film arrives the drain region of described MOS transistor;
On described interlayer insulating film, form the conductive interconnection that connects described the first conductive path and the second conductive path.
Alternatively, described Semiconductor substrate is the substrate that high-purity metallurgical grade silicon wafer, technique silicon chip clout or low-cost polysilicon form.
According to a forth aspect of the invention, provide the method for another kind of manufacture one-time programmable memory cell, this one-time programmable memory cell comprises capacitor and MOS transistor, and the method comprises:
On the part of dielectric substrate, form conductive material layer, with the first electrode as described capacitor;
On described dielectric substrate and described conductive material layer, form dielectric layer;
On described dielectric layer, form polysilicon layer or polysilicon germanium layer;
The described polysilicon layer of patterning or polysilicon germanium layer, with first and the second portion of the separation that forms described polysilicon layer or polysilicon germanium layer, described first is as the second electrode of described capacitor;
On described second portion, form gate-dielectric and grid conductor;
The described grid conductor of take is mask, and the second portion of described polysilicon layer or polysilicon germanium layer is carried out to Implantation, with source region and the drain region that forms described MOS transistor, and
Form interlayer insulating film;
Formation run through described interlayer insulating film arrive described polysilicon layer or polysilicon germanium layer first the first conductive path and run through the second conductive path that described interlayer insulating film arrives the drain region of described MOS transistor;
On described interlayer insulating film, form the conductive interconnection that connects described the first conductive path and the second conductive path.
In the method aspect third and fourth according to the present invention, alternatively, be mask take described grid conductor, second portion to described polysilicon layer or polysilicon germanium layer carries out Implantation, during with the source region that forms described MOS transistor and drain region, simultaneously the first of described polysilicon layer or polysilicon germanium layer carried out to Implantation.
In the method aspect third and fourth according to the present invention, alternatively, comprise at the described polysilicon layer of formation on described dielectric layer: on described dielectric layer, form amorphous silicon layer, this amorphous silicon layer of annealing is to form polysilicon layer.Further alternatively, this amorphous silicon layer of annealing comprises to form polysilicon layer: this amorphous silicon layer of laser annealing be take and formed particle size as the 50nm-100um polysilicon layer.
In one-time programmable memory cell according to the present invention, owing to can adopting relatively inexpensive material, such as high-purity metallurgical grade silicon wafer, technique silicon chip clout, low-cost polysilicon, glass, polyester material etc., as substrate, make manufacturing cost greatly reduce.
By reading detailed description and the appended claims below in conjunction with accompanying drawing, the features and advantages of the present invention will be more apparent.
The accompanying drawing explanation
Fig. 1 a shows the schematic circuit that can use according to the part of an exemplary memory array of one-time programmable memory cell of the present invention.
Fig. 1 b shows the schematic circuit that can use according to the part of another exemplary memory array of one-time programmable memory cell of the present invention.
Fig. 2 shows the schematic sectional view according to a kind of structure of memory cell of the present invention.
Fig. 3 a-3e shows the schematic cross section of an illustrative methods stages of the structure of manufacturing memory cell shown in Figure 2.
Fig. 4 shows the schematic cross section that has formed the structure after interlayer insulating film, conductive path and conductive interconnection after the step shown in Fig. 3 a-3e.
Fig. 5 a-5d shows the schematic cross section of another illustrative methods stages of the structure of manufacturing memory cell shown in Figure 2.
Fig. 6 shows the schematic cross section that has formed the structure after interlayer insulating film, conductive path and conductive interconnection after the step shown in Fig. 5 a-5d.
Fig. 7 shows the schematic sectional view according to the another kind of structure of one-time programmable memory cell of the present invention.
Fig. 8 a-8d shows the schematic cross section of an illustrative methods stages of the structure of manufacturing memory cell shown in Figure 7.
Fig. 9 shows the schematic cross section that has formed the structure after interlayer insulating film, conductive path and conductive interconnection after the step shown in Fig. 8 a-8d.
Embodiment
In order to make technical scheme provided by the invention more clear and clear, referring to accompanying drawing also in conjunction with specific embodiments, the present invention is described in more detail.Accompanying drawing is schematically, might not draw in proportion, runs through the Reference numeral that accompanying drawing is identical and means same or analogous part.In order to make the present invention clearer, device architectures more well known to those skilled in the art (for example, being formed on the spacer on gate dielectric layer and grid conductor sidewall) and processing step omit at this.
The illustrative circuitry of Fig. 1 a illustrates the part that can use according to an exemplary memory array 1000 of disposable programmable memory cell 1111 of the present invention.Memory cell 1111 comprises MOS transistor 1101 and capacitor 1102.The grid of MOS transistor 1101 is connected to word line WL1, and source electrode is connected to earth potential Gnd, and drain electrode is connected with an electrode of capacitor 1102.Another electrode of capacitor 1102 is connected to bit line BL1.Writing and reading of storage array 1000 shown in Fig. 1 a is well known in the art, is not repeated at this.
The illustrative circuitry of Fig. 1 b illustrates the part that can use according to another exemplary memory array 2000 of one-time programmable memory cell 1111 of the present invention.In this storage array 2000, the grid of the MOS transistor 1101 of memory cell 1111 is connected to word line WL1, and source electrode is connected to bit line BL1, and drain electrode is connected with an electrode of capacitor 1102.Another electrode of capacitor 1102 is connected to line program PRG1.Writing and reading of storage array 2000 shown in Fig. 1 b is well known in the art, is not repeated at this.
Fig. 2 shows the schematic sectional view according to a kind of structure of memory cell 1111 of the present invention.This memory cell 1111 comprises MOS transistor 1101 and the capacitor 1102 that is formed on the separation on Semiconductor substrate 100.Described MOS transistor 1101 comprises: be positioned at polysilicon or polycrystalline germanium silicon layer 106 ' on the dielectric layer 104 ' on described Semiconductor substrate 100, be positioned at gate dielectric layer 108 and grid conductor 110 on described polysilicon or polycrystalline germanium silicon layer 106 ', the channel region of described MOS transistor 1101 is arranged in the described polysilicon of described gate dielectric layer 108 belows or the part of polycrystalline germanium silicon layer 106 ', and source region and drain region lay respectively at the both sides of described channel region.Described capacitor 1102 comprises as the doped region 102 in the described Semiconductor substrate 100 of the first electrode, the dielectric layer 104 on described doped region 102 and is used as polysilicon or the polycrystalline germanium silicon layer 106 on the described dielectric layer 104 of the second electrode.Described dielectric layer 104 and 104 ' is used identical manufacturing process to form simultaneously, and described polysilicon or polycrystalline germanium silicon layer 106,106 ' are used identical manufacturing process to form simultaneously.
Being connected of the grid of MOS transistor 1101 and word line WL1, source electrode and earth potential Gnd(or bit line) be connected, being connected of the second electrode of drain electrode and capacitor 1102, and the first electrode of capacitor 1102 and bit line BL1(or line program) be connected can be by forming interlayer insulating film, run through the conductive path of interlayer insulating film and the conductive interconnection (not shown) on interlayer insulating film is realized, these are all as known in the art, therefore at this, are not repeated.
Described Semiconductor substrate 100 can adopt cheap silicon substrate, the substrate of formation such as high-purity metallurgical grade (UMG) silicon wafer, technique silicon chip clout, low-cost polysilicon.Described doped region 102 can be P
+Doped region or N
+Doped region, doping content is preferably 1e20-1e22cm
-3.Described dielectric layer 104(104 ') can be by silica, silicon nitride, silicon oxynitride, silicon oxynitride, HfSiO
x, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, SrTiO
3, LaAlO
3Or it is combined to form, thickness is preferably 1nm-300nm.Preferably, described polysilicon or polycrystalline germanium silicon layer 106(106 ') by the larger polysilicon of particle size, formed.Described particle size can be 50nm-100um.In a specific example, described particle size is 0.3-10um.In another specific example, described particle size is 1um.Described polysilicon or polycrystalline germanium silicon layer 106(106 ') thickness be 5nm-200nm.Described gate dielectric layer 108 can be by silica, silicon nitride, silicon oxynitride, silicon oxynitride, HfSiO
x, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, SrTiO
3, LaAlO
3Or it is combined to form.Described grid conductor 110 can for example, be formed by doped polycrystalline silicon or any suitable metal (, Ti, W, Al etc.).
An illustrative methods of the structure of manufacturing memory cell 1111 shown in Figure 2 is described below in conjunction with Fig. 3 a-3e.
At first, as shown in Figure 3 a, by Implantation, form doped region 102 in the part of Semiconductor substrate 100, this doped region 102 is for the first electrode of the capacitor that will form.
Next, as shown in Fig. 3 b, on described Semiconductor substrate 100, form successively dielectric layer 104, polysilicon or polycrystalline germanium silicon layer 106 and sacrifice layer 101.Described dielectric layer 104 can utilize the metal-organic chemical vapor deposition equipment such as MOCVD(), the PECVD(plasma activated chemical vapour deposition), the ALCVD(atomic layer chemical vapor deposition), the common process of sputter, electron beam evaporation etc., cvd silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, HfSiO
x, HfO
2, ZrO
2, Al
2O
3, TiO
2, La
2O
3, SrTiO
3, LaAlO
3Or its combination and forming.Form described polysilicon or polycrystalline germanium silicon layer 106 can comprise: deposition one amorphous silicon layer on described dielectric layer 104, this amorphous silicon layer of crystallization is to form polysilicon or polycrystalline germanium silicon layer 106.This crystallization can utilize for example thermal annealing, laser annealing or infrared radiation annealing to realize.Preferably, the temperature of laser annealing is about 1,000 degree, and the time is about a few to tens of nanoseconds.Preferably, form the larger polysilicon of particle size, for example particle size is the polysilicon of 50nm-100um.In a specific example, described particle size is 0.3-10um.In another specific example, described particle size is 1um.The thickness of this polysilicon or polycrystalline germanium silicon layer 106 is preferably 5nm-200nm.Described sacrifice layer 101 for example can be formed by silicon nitride.
Then, as shown in Figure 3 c, adopt the graphical described sacrifice layer 101 of conventional photoetching and etch process, polysilicon or polycrystalline germanium silicon layer 106 and dielectric layer 104, to form the platform A and the B that separate formed by described sacrifice layer 101, polysilicon or polycrystalline germanium silicon layer 106 and dielectric layer 104, be respectively used in subsequent step, form described capacitor and MOS transistor, the projection of described platform A on substrate falls in the scope of described doped region 102.
Next, dielectric layer deposition 103, utilize the resulting structure of CMP technology planarization, until remove described sacrifice layer 101, thus form structure as shown in Figure 3 d.Expose portion at substrate 100 described in Fig. 3 d is coated with dielectric layer 103, and this dielectric layer 103 flushes with described polysilicon or polycrystalline germanium silicon layer 106.Preferably, described dielectric layer 103 is finer and close than described dielectric layer 104.
Then, adopt deposition well known in the art and chemical etching technique, on described platform B, form gate dielectric layer 108 and grid conductor 110, as shown in Figure 3 e, and take grid conductor 110 and carry out the doping in source region and the drain region of MOS transistor as mask, optionally, can be simultaneously described polysilicon or the polycrystalline germanium silicon layer of the second electrode of forming capacitor be carried out to identical doping.
After completing the step shown in Fig. 3 a-3e, can be according to method well known in the art, on resulting structure, form interlayer insulating film, in described interlayer insulating film, form conductive path, and need on described interlayer dielectric, form according to the connection of side circuit the conductive interconnection that connects conductive path.Fig. 4 schematically shows the cross-sectional view that has formed interlayer insulating film 112, conductive path 114,116,118,120 and conductive interconnection 122 rear resulting structures.
Another illustrative methods of the structure of manufacturing memory cell 1111 shown in Figure 2 is described below in conjunction with Fig. 5 a-5d.
At first, as shown in Figure 5 a, by Implantation, form doped region 102 in the part of Semiconductor substrate 100.
Next, as shown in Figure 5 b, on described Semiconductor substrate 100, form successively dielectric layer 104 and polysilicon or polycrystalline germanium silicon layer 106.The formation technique of described dielectric layer 104 and polysilicon or polycrystalline germanium silicon layer 106, material are identical with reference to the described step of Fig. 3 b with front, no longer repeat at this.
Then, as shown in Figure 5 c, the described polysilicon of patterning or polysilicon germanium layer 106, to form platform A ' and the B ' separated, be respectively used to form the second electrode of the capacitor that will form and the active area of MOS transistor.For example, can utilize photoetching well known in the art and etching technique with respect to described the dielectric layer 104 optionally described polysilicon of etching or polycrystalline germanium silicon layer 106.
Next, dielectric layer deposition 108 conformally on the structure shown in Fig. 5 c, this dielectric layer 108 is as the gate-dielectric of the MOS transistor 1101 that will form, described dielectric layer on described platform B ' 108 tops form grid conductor 110 afterwards, as shown in Fig. 5 d, and the grid conductor 110 of take carries out the doping in source region and the drain region of MOS transistor as mask, optionally, can be simultaneously described polysilicon or the polycrystalline germanium silicon layer of the second electrode of forming described capacitor 1102 be carried out to identical doping.
After completing the step shown in Fig. 5 a-5d, can be according to method well known in the art, on resulting structure, form interlayer insulating film, in described interlayer insulating film, form conductive path, and need on described interlayer dielectric, form according to the connection of side circuit the conductive interconnection that connects conductive path.Fig. 6 schematically shows the cross-sectional view that has formed interlayer insulating film 112, conductive path 114,116,118,120 and conductive interconnection 122 rear resulting structures.
Fig. 7 shows the schematic sectional view according to the another kind of structure of memory cell 1111 of the present invention.Memory cell 1111 shown in Fig. 7 comprises MOS transistor 1101 and the capacitor 1102 that is formed on the separation on dielectric substrate 200.Described MOS transistor 1101 comprises: be positioned at polysilicon or polycrystalline germanium silicon layer 206 ' on the dielectric layer 204 ' on described Semiconductor substrate 200, be positioned at gate dielectric layer 208 and grid conductor 210 on described polysilicon or polycrystalline germanium silicon layer 206 ', the channel region of described MOS transistor 1101 is arranged in the described polysilicon of described gate dielectric layer 208 belows or the part of polycrystalline germanium silicon layer 206 ', and source region and drain region lay respectively at the both sides of described channel region.Described capacitor 1102 comprises as the first electrode 202 on the described Semiconductor substrate 200 of the first electrode, the dielectric layer 204 on described metal electrode 202 and is used as polysilicon or the polycrystalline germanium silicon layer 206 on the described dielectric layer 204 of the second electrode.Described the first electrode 202 can be formed by metal or doped polycrystalline silicon.Described dielectric layer 204 and 204 ' is used identical manufacturing process to form simultaneously, and described polysilicon or polycrystalline germanium silicon layer 206,206 ' are used identical manufacturing process to form simultaneously.
The difference of the structure of the memory cell 1111 shown in Fig. 7 and structure shown in Figure 2 only is: adopt metal on dielectric substrate 200 or doped polysilicon layer the first electrode 202 as capacitor 1102.Described dielectric substrate 200 is for example formed by glass or polyester material, and described metal is for example copper, aluminium or nickel.Abovely for the dielectric layer 104 in Fig. 2, polysilicon or polycrystalline germanium silicon layer 106, gate dielectric layer 108 and grid conductor 110, describe and also be applicable to respectively the dielectric layer 204 shown in Fig. 7, polysilicon or polycrystalline germanium silicon layer 206, gate dielectric layer 208 and grid conductor 210.
Being connected of the grid of the MOS transistor 1101 shown in Fig. 7 and word line WL1, source electrode and earth potential Gnd(or bit line) be connected, being connected of the second electrode of drain electrode and capacitor 1102, and the first electrode of capacitor 1102 and bit line BL1(or line program) be connected can be by forming interlayer insulating film, run through the conductive path of interlayer insulating film and the conductive interconnection (not shown) on interlayer insulating film is realized, these are all as known in the art, therefore at this, are not repeated.
An illustrative methods of the structure of manufacturing memory cell 1111 shown in Figure 7 is described below in conjunction with Fig. 8 a-8d.
At first, as shown in Figure 8 a, on the zone that will form capacitor 1102 on dielectric substrate 200, form metal electrode layer 202, on this metal electrode layer 202, form dielectric layer 204 and utilize this dielectric layer 204 of technique planarization such as CMP.This metal electrode layer 202 can be by sputter or evaporated metal layer on dielectric substrate 200, afterwards graphical this metal level and forming.
Then, as shown in Figure 8 b, on described dielectric layer 204, form polysilicon or polysilicon germanium layer 206.The polysilicon layer that front is described in conjunction with Fig. 3 b or the formation of polycrystalline germanium silicon layer 106 also are applicable to the formation of this polysilicon or polysilicon germanium layer 206.
Next, as shown in Figure 8 c, the described polysilicon of patterning or polysilicon germanium layer 206, to form platform A ' ' and the B ' ' separated, be respectively used to form the second electrode of the capacitor that will form and the active area of MOS transistor.
Again next, dielectric layer deposition 208 conformally on the structure shown in Fig. 8 c, this dielectric layer 208 is as the gate-dielectric of the MOS transistor 1101 that will form, described dielectric layer on described platform B ' ' 108 tops form grid conductor 210 afterwards, as shown in Fig. 8 d, and the grid conductor 210 of take carries out the doping in source region and the drain region of MOS transistor as mask, optionally, can be simultaneously described polysilicon or the polycrystalline germanium silicon layer of the second electrode of forming described capacitor 1102 be carried out to identical doping.
After completing the step shown in Fig. 8 a-8d, can be according to method well known in the art, on resulting structure, form interlayer insulating film, in described interlayer insulating film, form conductive path, and need on described interlayer dielectric, form according to the connection of side circuit the conductive interconnection that connects conductive path.Fig. 9 schematically shows the cross-sectional view that has formed interlayer insulating film 212, conductive path 214,216,218,220 and conductive interconnection 222 rear resulting structures.
Should be appreciated that above described MOS transistor both can also can be the PMOS transistor for nmos pass transistor.Described interlayer insulating film, described conductive path and described conductive interconnection can select various material as known in the art to form, and give an example no longer one by one at this.
Abovely by exemplary embodiment, described the method according to manufacture one-time programmable memory cell of the present invention, yet this is not intended to limit the scope of the invention.Any modification of the above-described embodiment it may occur to persons skilled in the art that or modification all fall in the scope of the present invention be defined by the following claims.
Claims (13)
1. one-time programmable memory cell comprises:
Comprise the first electrode, be positioned at the first dielectric layer on the first electrode and be positioned at the capacitor of the second electrode on described the first dielectric layer, this first electrode in being formed on Semiconductor substrate doped region or the conductive material layer be formed on dielectric substrate form, described the second electrode is formed by the first polysilicon or polysilicon germanium layer;
MOS transistor, comprise active layer and be positioned at gate dielectric layer and the grid conductor on this active layer, the channel region of this MOS transistor is arranged in the described active layer that the described active layer of described gate dielectric layer below and source region and drain region lay respectively at described channel region both sides, described active layer is positioned at described the first dielectric layer and adopts identical technique to be formed on simultaneously on the second dielectric layer on described Semiconductor substrate or on dielectric substrate, and described active layer is formed by the second polysilicon or the polysilicon germanium layer with described the first polysilicon or polysilicon germanium layer adopt identical technique to form simultaneously, and
Be formed on the interlayer insulating film on described capacitor and described MOS transistor,
The second electrode of described capacitor is electrically connected to by the conductive interconnection that is formed on the conductive path in described interlayer insulating film and be formed on described interlayer insulating film with the drain region of described MOS transistor.
2. memory cell according to claim 1, described Semiconductor substrate are the substrates that high-purity metallurgical grade silicon wafer, technique silicon chip clout or low-cost polysilicon form, and described dielectric substrate is formed by glass or polyester material.
3. memory cell according to claim 1 and 2, wherein said the first and second polysilicon layers are that the 50nm-100um polysilicon forms by the particle size formed by the laser annealing amorphous silicon.
4. an One Time Programmable storage array, comprise one-time programmable memory cell as described as any one in claim 1-3.
5. method of manufacturing one-time programmable memory cell, this one-time programmable memory cell comprises capacitor and MOS transistor, the method comprises:
A part to Semiconductor substrate is carried out Implantation, to form the doped region as the first electrode of described capacitor;
Dielectric layer deposition on described Semiconductor substrate;
On described dielectric layer, form polysilicon layer or polysilicon germanium layer;
The described polysilicon layer of patterning or polysilicon germanium layer, with first and the second portion of the separation that forms described polysilicon layer or polysilicon germanium layer, described first is as the second electrode of described capacitor;
On described second portion, form gate-dielectric and grid conductor;
The described grid conductor of take is mask, the second portion of described polysilicon layer or polysilicon germanium layer is carried out to Implantation, with source region and the drain region that forms described MOS transistor; And
Form interlayer insulating film;
Formation run through described interlayer insulating film arrive described polysilicon layer or polysilicon germanium layer first the first conductive path and run through the second conductive path that described interlayer insulating film arrives the drain region of described MOS transistor;
On described interlayer insulating film, form the conductive interconnection that connects described the first conductive path and the second conductive path.
6. method according to claim 5, wherein be mask take described grid conductor, second portion to described polysilicon layer or polysilicon germanium layer carries out Implantation, during with the source region that forms described MOS transistor and drain region, simultaneously the first of described polysilicon layer or polysilicon germanium layer carried out to Implantation.
7. method according to claim 5, described Semiconductor substrate are the substrates that high-purity metallurgical grade silicon wafer, technique silicon chip clout or low-cost polysilicon form.
8. according to the described method of any one in claim 5-7, wherein at the described polysilicon layer of formation on described dielectric layer, comprise: on described dielectric layer, form amorphous silicon layer, this amorphous silicon layer of annealing is to form polysilicon layer.
9. method according to claim 8, this amorphous silicon layer of wherein annealing comprises to form polysilicon layer: this amorphous silicon layer of laser annealing be take and formed particle size as the 50nm-100um polysilicon layer.
10. method of manufacturing one-time programmable memory cell, this one-time programmable memory cell comprises capacitor and MOS transistor, the method comprises:
On the part of dielectric substrate, form conductive material layer, with the first electrode as described capacitor;
On described dielectric substrate and described conductive material layer, form dielectric layer;
On described dielectric layer, form polysilicon layer or polysilicon germanium layer;
The described polysilicon layer of patterning or polysilicon germanium layer, with first and the second portion of the separation that forms described polysilicon layer or polysilicon germanium layer, described first is as the second electrode of described capacitor;
On described second portion, form gate-dielectric and grid conductor;
The described grid conductor of take is mask, and the second portion of described polysilicon layer or polysilicon germanium layer is carried out to Implantation, with source region and the drain region that forms described MOS transistor, and
Form interlayer insulating film;
Formation run through described interlayer insulating film arrive described polysilicon layer or polysilicon germanium layer first the first conductive path and run through the second conductive path that described interlayer insulating film arrives the drain region of described MOS transistor;
On described interlayer insulating film, form the conductive interconnection that connects described the first conductive path and the second conductive path.
11. method according to claim 10, wherein be mask take described grid conductor, second portion to described polysilicon layer or polysilicon germanium layer carries out Implantation, during with the source region that forms described MOS transistor and drain region, simultaneously the first of described polysilicon layer or polysilicon germanium layer carried out to Implantation.
12.
According toThe described method of claim 10 or 11 wherein comprises at the described polysilicon layer of formation on described dielectric layer: on described dielectric layer, form amorphous silicon layer, this amorphous silicon layer of annealing is to form polysilicon layer.
13. method according to claim 12, this amorphous silicon layer of wherein annealing comprises to form polysilicon layer: this amorphous silicon layer of laser annealing be take the formation particle size as the 50nm-100um polysilicon layer.
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Citations (3)
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|---|---|---|---|---|
| CN1304547A (en) * | 1999-03-05 | 2001-07-18 | 精工爱普生株式会社 | Method for producing thin film semiconductor device |
| US6822888B2 (en) * | 2001-09-18 | 2004-11-23 | Kilopass Technologies, Inc. | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| CN101752380A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | OTP device |
-
2011
- 2011-08-02 CN CN2011102195922A patent/CN102324428B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1304547A (en) * | 1999-03-05 | 2001-07-18 | 精工爱普生株式会社 | Method for producing thin film semiconductor device |
| US6822888B2 (en) * | 2001-09-18 | 2004-11-23 | Kilopass Technologies, Inc. | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric |
| CN101752380A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | OTP device |
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