CN102332408A - Chip scale package and production method thereof - Google Patents
Chip scale package and production method thereof Download PDFInfo
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- CN102332408A CN102332408A CN2010102296401A CN201010229640A CN102332408A CN 102332408 A CN102332408 A CN 102332408A CN 2010102296401 A CN2010102296401 A CN 2010102296401A CN 201010229640 A CN201010229640 A CN 201010229640A CN 102332408 A CN102332408 A CN 102332408A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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Abstract
The invention discloses a chip scale package and a production method thereof. A protective layer is arranged on an acting surface of a chip, a non-acting surface of the chip is fixed on a rigid carrier, a package mold pressing process is performed and the protective layer is removed, and then a wire rearrangement technology is performed; therefore, the problems, such as adhesive film softening, package colloid overflow or warpage, chip displacement and pollution, and even waste product generation due to bad contact between a circuit layer and a chip solder pad in a subsequent wire rearrangement technology, caused by directly adhering the acting surface of the chip on the adhesive film in the prior art can be avoided; furthermore, the carrier can be repeatedly used in the production technology so that the production cost is saved.
Description
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, particularly relate to a kind of chip size package and method for making thereof.
Background technology
Evolution along with semiconductor technology; Semiconductor product has been developed different encapsulating products kenels; And be pursue semiconductor package part compact; Thereby develop a kind of chip size package (chip scale package CSP), is characterized in that this kind chip size package only has with chip size to equate or bigger size.
United States Patent (USP) the 5th, 892,179,6,103; 552,6,287,893,6,350; 668 and 6,433, No. 427 patent discloses a kind of traditional CSP structure; Be directly on chip, to form to increase layer and need not to use, and utilize and reroute that (redistribution layer, RDL) weld pad on the technological reprovision chip is extremely desired the position like chip bearing members such as substrate or lead frames.
Yet the shortcoming of above-mentioned CSP structure is the conductive trace that the enforcement of the technology of rerouting is used or is laid on the chip and often is subject to the size of chip or the area size of its acting surface; Especially under the situation that the integrated level of chip promotes and chip size dwindles day by day, chip even can't provide enough surfaces to come to electrically connect with extraneous with the soldered ball of settling greater number.
In view of this; United States Patent (USP) the 6th, 271, No. 469 patents disclose the method for making of a kind of crystal wafer chip dimension packaging part WLCSP (Wafer Level CSP); Be on chip, to form the packaging part increase layer, can provide comparatively sufficient surf zone to carry more I/O end or soldered ball.
Shown in Figure 1A, to prepare a glued membrane 11, and a plurality of chips 12 are pasted on this glued membrane 11 with acting surface 121, this glued membrane 11 for example is the thermoinduction glued membrane; Shown in Figure 1B, carry out the Encapsulation Moulds compression technology, utilize the non-acting surface 122 and the side that envelope chip 12 just like the packing colloid 13 of epoxy resin, heating removes this glued membrane 11 again, to expose outside this chip acting surface 121; Shown in Fig. 1 C; Utilize (RDL) technology that reroutes then, lay a dielectric layer 14 on the surface of the acting surface 121 of chip and packing colloid 13, and offer a plurality of openings that run through dielectric layer 14 with the weld pad on the exposed chip 120; Then on this dielectric layer 14, form line layer 15; And make line layer 15 be electrically connected to weld pad 120, and on line layer 15, lay again and refuse layer 16 and the line layer precalculated position plants soldered ball 17, carry out cutting operation afterwards.
Through aforementioned manufacturing process, because of the surface of the packing colloid of coating chip can provide the surf zone big than the chip acting surface can settle more soldered ball effectively to reach and extraneous electric connection.
Yet; The shortcoming of above-mentioned manufacturing process is chip is pasted on the glued membrane and fixing mode with acting surface; Often because of glued membrane is heated flexible problem taking place, cause to glue to place the chip position on the glued membrane to squint, even when the encapsulation mold pressing, causes the chip displacement because of glued membrane receives thermal softening in technology; So cause follow-up when rerouting technology, line layer can't be connected to cause on the chip pad electrically bad.Moreover the glued membrane that uses is expendable material in this manufacturing process, causes the increase of manufacturing cost.
In addition, see also Fig. 2, when aforementioned encapsulation mold pressing; Meet thermal softening because of glued membrane 11, packing colloid 13 is prone to take place glue 130 to the chip acting surface 121 that overflows, even pollute weld pad 120; Cause the line layer and the chip pad loose contact of the follow-up technology that reroutes, and cause the waste product problem.
Moreover; See also Fig. 3 A, aforementioned Encapsulation Moulds compression technology only supports a plurality of chips 12 through glued membrane 11, and this glued membrane 11 and packing colloid 13 are prone to take place serious warpage (warpage) 110 problems; Especially when the very thin thickness of packing colloid 13; Warpage issues is even more serious, thereby causes follow-up rerouting during technology, on chip, has the uneven thickness problem during coating dielectric layer; So promptly the extra hard carrier 18 (shown in Fig. 3 B) that provides again of palpus flattens so that packing colloid 13 is fixed on this hard carrier 18 through a viscose glue 19; So not only cause manufacturing process complicated, and increase many manufacturing costs, reroute technology and when removing this carrier in completion simultaneously, be prone to occur in and have residual 190 problems of the viscose glue that before had been fixed on the carrier (shown in Fig. 3 C) on the packing colloid.The disclosure of other related art such as United States Patent (USP) the 6th, 498,387,6,586,822,7,019,406 and 7,238, No. 602.
Therefore, how a kind of chip size package and method for making being provided, thereby can guaranteeing the electric connection quality between line layer and weld pad, and promote the reliability of product, reduce manufacturing cost, is an important techniques problem in fact.
Summary of the invention
Because the shortcoming of above-mentioned prior art the purpose of this invention is to provide a kind of chip size package and method for making, guaranteeing the electric connection quality between line layer and weld pad, and promote the reliability of product, reduce manufacturing cost.
For achieving the above object; The present invention provides a kind of method for making of chip size package; Comprise: a chip and a carrier that a plurality of tool relativity faces and non-acting surface are provided; This chip acting surface is provided with a plurality of weld pads, on this chip acting surface, is coated with protective layer and is provided with first coating layer in this carrier surface, so that this chip is fixed on this first coating layer through its non-acting surface; Coat this chip and expose outside the protective layer on this chip acting surface with second coating layer; Remove this protective layer to expose outside this chip acting surface; On this chip acting surface and second coating layer, dielectric layer is set, and makes this dielectric layer form opening to expose outside this weld pad; On this dielectric layer, form line layer, and make this line layer be electrically connected to this weld pad; And on this dielectric layer and line layer, be provided with and refuse layer, and make this refuse layer to form a plurality of openings to plant soldered ball.Follow-up is removable this carrier, and carries out cutting operation to form a plurality of crystal wafer chip dimension packaging parts (WLCSP).
Be thinning packaging part and also removable this first coating layer of lifting chip cooling effect.The technology of rerouting capable of using in addition forms circuit and increases layer (build-up) structure on this line layer.In the method for making of chip size package of the present invention; Because of the adhesive force of this second coating layer and first coating layer adhesive force greater than first coating layer and carrier; And can in follow-up manufacturing process, remove this carrier easily; Manufacturing process efficient is provided thus, reuses this carrier, and then save manufacturing cost.
Through aforementioned method for making, the present invention also provides a kind of chip size package, comprising: chip, this chip have relative acting surface and non-acting surface, and are provided with a plurality of weld pads at this chip acting surface; Second coating layer is coated on around this chip, and the height of this second coating layer is greater than the height of this chip; Dielectric layer is located on this chip acting surface and second coating layer, and a plurality of openings of this dielectric layer tool are to expose this weld pad; And line layer, be located on this dielectric layer and be electrically connected to this weld pad.
This packaging part also includes: refuse layer, be located on this dielectric layer and the line layer, this is refused layer and has a plurality of openings to expose outside the line layer predetermined portions; And soldered ball, be located on this line layer predetermined portions.
In addition, this packaging part also can be established first coating layer on the non-acting surface of this chip and second coating layer.
Therefore; Chip size package of the present invention and method for making are mainly established a protective layer on the chip acting surface, and chip is fixed on the hard carrier with non-acting surface, then carry out the Encapsulation Moulds compression technology and remove this protective layer; Technology more then reroutes; Use and avoid existing directly sticking the placing of chip acting surface glued membrane is taken place on the glued membrane received thermal softening, packing colloid overflow glue and chip offset and pollution problem,, cause the waste product problem even cause the line layer and the chip pad loose contact of the follow-up technology that reroutes; And among the present invention this carrier in manufacturing process because of the adhesive force of second coating layer and first coating layer adhesive force greater than first coating layer and carrier; But and easy removal and repeated use, to save manufacturing cost, the present invention simultaneously need not use glued membrane; Event can be avoided having now use glued membrane in the manufacturing process and warpage issues takes place, and needs the extra carrier that provide to be caused manufacturing process complicacy, cost increase and packing colloid that problems such as cull are arranged by solving this warpage issues.
Description of drawings
Figure 1A to Fig. 1 C is a U.S. Pat 6,271, the method for making sketch map of 469 disclosed crystal wafer chip dimension packaging parts;
Fig. 2 is a U.S. Pat 6,271, and the sketch map of excessive glue problem takes place 469 disclosed crystal wafer chip dimension packaging parts;
Fig. 3 A to Fig. 3 C is a U.S. Pat 6,271,469 disclosed crystal wafer chip dimension packaging part generation packing colloid warpages, sets up the sketch map of carrier and packing colloid surface cull problem;
Fig. 4 A to Fig. 4 H is chip size package of the present invention and the method for making first embodiment sketch map thereof;
Fig. 5 is chip size package of the present invention and the method for making second embodiment sketch map thereof;
Fig. 6 is chip size package of the present invention and method for making the 3rd embodiment sketch map thereof;
Fig. 7 A to Fig. 7 D is chip size package of the present invention and method for making the 4th embodiment sketch map thereof.
The main element symbol description:
11 glued membranes, 12 chips
13 packing colloids, 14 dielectric layers
15 line layers 16 are refused layer
17 soldered balls, 18 carriers
19 viscose glues, 21 protective layers
22 chip 22A wafers
23 carriers, 24 viscose glues
25 second coating layers, 26 dielectric layers
26a second dielectric layer 27 line layers
27a second line layer 28 is refused layer
29 soldered balls, 31 protective layers
32 chips, 33 carriers
34 viscose glues, 35 second coating layers
36 dielectric layers, 37 line layers
38 refuse layer 39 soldered balls
110 warpages, 120 weld pads
121 acting surfaces, 122 non-acting surfaces
130 excessive glue 190 viscose glues are residual
220 weld pads, 221 acting surfaces
222 non-acting surface 230 first coating layers
330 first coating layers, 333 any enhanced protection layers
Embodiment
Below through particular specific embodiment execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
See also Fig. 4 A to Fig. 4 H, be the sketch map of chip size package of the present invention and method for making first embodiment thereof.
Shown in Fig. 4 A and Fig. 4 B; The wafer 22A of a plurality of chips 22 of one tool is provided; This wafer 22A and chip 22 have relative acting surface 221 and non-acting surface 222, and this chip acting surface 221 is provided with a plurality of weld pads 220, and on this wafer acting surface 221, lay thick about 3 to 20 a microns protective layer 21; Then carry out wafer 22A cutting, to form the chip 22 that a plurality of acting surfaces 221 are provided with protective layer 21.
Shown in Fig. 4 C; Other provides a hard carrier 23; And coating first coating layer 230 on carrier 23, thus a plurality of chips 22 that aforementioned acting surface 221 are provided with protective layer 21 glue through viscose glue 24 with its non-effect 222 and place on this first coating layer 230, and toast (cure) and fix.This first coating layer 230 for example is the epoxy resin of printing ink.
Shown in Fig. 4 D, coat this chip 22 and expose outside the protective layer 21 on this chip acting surface 221 to make second coating layer 25 like press moulding mode like epoxy resin encapsulating material.This second coating layer 25 for example is the encapsulating material of epoxy resin; Wherein the material of this carrier 23, first coating layer 230 and second coating layer 25 selects to make the adhesive force of the adhesive force of this second coating layer 25 and first coating layer 230 greater than first coating layer 230 and carrier 23, with convenient follow-up this carrier 23 that removes.
Shown in Fig. 4 E, remove exposed chip acting surface 221 beyond this protective layer with mode like chemical agent.So the height of this second coating layer 25 is promptly greater than the height of this chip acting surface 221.
Shown in Fig. 4 F, on the chip acting surface 221 and second coating layer 25, dielectric layer 26 is set, and utilizes for example gold-tinted (photo-lithography) technology or laser technology, make this dielectric layer be formed with a plurality of openings to expose outside this weld pad 220.This dielectric layer 26 is to use for follow-up line layer to adhere to the Seed Layer (seed layer) on it.
Then, utilize (RDL) technology that reroutes on this dielectric layer 26, to form line layer 27, and make this line layer 27 be electrically connected to this weld pad 220.
Shown in Fig. 4 G, on this dielectric layer 26 and line layer 27, be provided with and refuse layer 28, and make this refuse layer 28 to form a plurality of openings exposing outside this line layer 27 predetermined portions, thereby supply to plant soldered ball 29 in this line layer predetermined portions.
Shown in Fig. 4 H; Afterwards because of the adhesive force of this second coating layer 25 and first coating layer 230 greater than the adhesive force of first coating layer 230 with carrier 23; Get final product this carrier 23 of easy removal, carry out cutting operation again, to form a plurality of crystal wafer chip dimension packaging parts (WLCSP).
Through aforementioned method for making, the present invention also provides a kind of chip size package, comprising: chip 22, and this chip 22 has relative acting surface 221 and non-acting surface 222, and is provided with a plurality of weld pads 220 at this chip acting surface 221; Second coating layer 25 is coated on around this chip 22, and the height of this second coating layer 25 is greater than the height of this chip 22; Dielectric layer 26 is located on these chip 22 acting surfaces and second coating layer 25, and this dielectric layer 26 has a plurality of openings to expose this weld pad 220; Line layer 27 is located on this dielectric layer 26 and is electrically connected to this weld pad 220; Refuse layer 28, be located on this dielectric layer 26 and the line layer 27, this is refused layer 28 and has a plurality of openings to expose outside line layer 27 predetermined portions; Soldered ball 29 is located on these line layer 27 predetermined portions.In addition, this packaging part is established first coating layer 230 on the non-acting surface 222 of this chip and second coating layer 25.
Therefore; Chip size package of the present invention and method for making are mainly established a protective layer on the chip acting surface, and chip is fixed on the hard carrier with non-acting surface, then carry out the Encapsulation Moulds compression technology and remove this protective layer; Technology more then reroutes; Use and avoid prior art that directly sticking the placing of chip acting surface glued membrane is taken place on the glued membrane received thermal softening, packing colloid overflow glue and chip offset and pollution problem,, cause the waste product problem even cause the line layer and the chip pad loose contact of the follow-up technology that reroutes; And among the present invention this carrier in manufacturing process because of the adhesive force of second coating layer and first coating layer adhesive force greater than first coating layer and carrier; But and easy removal and repeated use, to save manufacturing cost, the present invention simultaneously need not use glued membrane; Event can be avoided having now use glued membrane in the manufacturing process and warpage issues takes place, and needs the extra carrier that provide to be caused manufacturing process complicacy, cost increase and packing colloid that problems such as cull are arranged by solving this warpage issues.
Seeing also Fig. 5, is the generalized section that shows chip size package of the present invention and method for making second embodiment thereof.As shown in the figure; What this chip size package and previous embodiment provided is roughly the same; Its difference is in follow-up for also removable first coating layer of thinning packaging part, helps heat that 32 operations of dissipation chip are produced to extraneous simultaneously, promotes the radiating efficiency of packaging part.
See also Fig. 6 again, for showing the generalized section of chip size package of the present invention and method for making the 3rd embodiment thereof.As shown in the figure; What this chip size package and previous embodiment provided is roughly the same, and its difference is in the technology of rerouting capable of using and continues to form layer reinforced structure on formerly formed dielectric layer and the line layer, forms the second dielectric layer 26a and the second line layer 27a on for example formerly formed dielectric layer 26 and the line layer 27; And make this second line layer 27a be electrically connected to this first line layer 27; Then, on the second line layer 27a, lay again and refuse layer 28, and offer a plurality of openings of refusing layer 28 that run through; To expose outside the predetermined portions of the second line layer 27a; Then on the predetermined portions of the second line layer 27a, plant soldered ball 29,, supply to electrically connect with external device with I/O end as packaging part.So can be through increasing increasing number of layers and can promote the elasticity that circuit is laid in the packaging part on the chip.
See also Fig. 7 A to Fig. 7 D, for showing the generalized section of chip size package of the present invention and method for making the 4th embodiment thereof.As shown in the figure, it is roughly the same that present embodiment and previous embodiment are provided, and main difference is can on the non-acting surface of chip, set up an any enhanced protection layer with the protection chip.
Shown in Fig. 7 A; One hard carrier 33 is provided; And coating first coating layer 330 on carrier 33; Again on this first coating layer 330 to form like press moulding mode as any enhanced protection layer 333 of epoxy resin encapsulating material (EMC, Epoxy Molding Compound), wherein the adhesive force of this any enhanced protection layer 333 and first coating layer 330 is greater than the adhesive force of this first coating layer 330 and carrier 33.
Shown in Fig. 7 B, the chip 32 that acting surface is provided with protective layer 31 glues through viscose glue 34 with its non-acting surface and places on this any enhanced protection layer 333.
Shown in Fig. 7 C, coat this chip 32 and expose outside the protective layer 31 on this chip acting surface to make second coating layer 35 like press moulding mode like epoxy resin encapsulating material; Then remove this protective layer 31 to expose outside this chip acting surface, on this chip acting surface and second coating layer 35, dielectric layer 36 is set again, and on this dielectric layer 36, form line layer 37.
Then on this dielectric layer 36 and line layer 37, be provided with and refuse layer 38, and plant soldered ball 39.
Shown in Fig. 7 D, be removable this carrier 33 afterwards, and carry out cutting operation.
So promptly be provided with an any enhanced protection layer 333 on the non-acting surface of this chip 32, to provide chip better protection.
The foregoing description is merely illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, rights protection scope of the present invention should be foundation with the scope of claims.
Claims (22)
1. the method for making of a chip size package is characterized in that, comprising:
The chip and a carrier of a plurality of tool relativity faces and non-acting surface are provided, and this chip acting surface is provided with a plurality of weld pads; On this chip acting surface, be coated with protective layer; Be provided with first coating layer in this carrier surface; Chip is fixed on this first coating layer through its non-acting surface;
Coat this chip and expose outside the protective layer on this chip acting surface with second coating layer;
Remove this protective layer to expose outside this chip acting surface;
On this chip acting surface and second coating layer, dielectric layer is set, and makes this dielectric layer form opening to expose outside this weld pad; And
On this dielectric layer, form line layer, and make this line layer be electrically connected to this weld pad.
2. the method for making of chip size package according to claim 1 is characterized in that, also comprises: on this dielectric layer and line layer, be provided with and refuse layer, and make this refuse layer to form a plurality of openings to plant soldered ball.
3. the method for making of chip size package according to claim 2 is characterized in that, also comprises: remove this carrier, and carry out cutting operation.
4. the method for making of chip size package according to claim 1 is characterized in that, the adhesive force of this second coating layer and first coating layer is greater than the adhesive force of first coating layer and carrier.
5. the method for making of chip size package according to claim 1 is characterized in that, the height of this second coating layer is greater than the height of this chip.
6. the method for making of chip size package according to claim 3 is characterized in that, also comprises: remove this first coating layer.
7. the method for making of chip size package according to claim 1 is characterized in that, also comprises: on this dielectric layer and line layer, form layer reinforced structure with the technology of rerouting.
8. the method for making of chip size package according to claim 1; It is characterized in that the manufacturing process of this chip and carrier comprises: the wafer of a plurality of chips of a tool is provided, and this wafer and chip have relative acting surface and non-acting surface; On this wafer acting surface, to lay protective layer; Then carry out the wafer cutting, to form the chip that a plurality of acting surfaces are provided with protective layer, so that this chip is fixed on first coating layer of carrier through its non-acting surface.
9. the method for making of chip size package according to claim 1 is characterized in that, also is formed with any enhanced protection layer on this first coating layer, connects for this chip to place on this any enhanced protection layer.
10. the method for making of chip size package according to claim 9 is characterized in that, this any enhanced protection layer is to form through press moulding mode.
11. the method for making of chip size package according to claim 10 is characterized in that, this any enhanced protection layer is an epoxide resin material.
12. the method for making of chip size package according to claim 9 is characterized in that, the adhesive force of this any enhanced protection layer and first coating layer is greater than the adhesive force of this first coating layer and carrier.
13. the method for making of chip size package according to claim 1 is characterized in that, this second coating layer is to make encapsulating material coat this chip through press moulding mode.
14. the method for making of chip size package according to claim 1 is characterized in that, this first coating layer is the printing ink that contains epoxy resin.
15. a chip size package is characterized in that, comprising:
Chip, this chip have relative acting surface and non-acting surface, and are provided with a plurality of weld pads at this chip acting surface;
Second coating layer is coated on around this chip, and the height of this second coating layer is greater than the height of this chip;
Dielectric layer is located on this chip acting surface and second coating layer, and a plurality of openings of this dielectric layer tool are to expose this weld pad; And
Line layer is located on this dielectric layer and is electrically connected to this weld pad.
16. chip size package according to claim 15 is characterized in that, also comprises:
Refuse layer, be located on this dielectric layer and the line layer, this is refused layer and has a plurality of openings to expose outside the line layer predetermined portions; And
Soldered ball is located on this line layer predetermined portions.
17. chip size package according to claim 15 is characterized in that, also comprises: first coating layer, be located on the non-acting surface of this chip and second coating layer.
18. chip size package according to claim 15 is characterized in that, also comprises: any enhanced protection layer, be located on the non-acting surface of this chip and second coating layer.
19. chip size package according to claim 18 is characterized in that, this any enhanced protection layer is an epoxide resin material.
20. chip size package according to claim 15 is characterized in that, also comprises layer reinforced structure, is formed on this dielectric layer and the line layer.
21. chip size package according to claim 15 is characterized in that, this second coating layer is an epoxide resin material.
22. chip size package according to claim 15 is characterized in that, this first coating layer is the printing ink that contains epoxy resin.
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| CN201010229640.1A CN102332408B (en) | 2010-07-13 | 2010-07-13 | Chip scale package and production method thereof |
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| CN201010229640.1A CN102332408B (en) | 2010-07-13 | 2010-07-13 | Chip scale package and production method thereof |
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| CN102332408B (en) | 2015-05-13 |
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