CN102355235B

CN102355235B - Multiple input and multiple clock D trigger with maintaining obstructive type

Info

Publication number: CN102355235B
Application number: CN201110219023.8A
Authority: CN
Inventors: 赵不贿
Original assignee: Jiangsu University
Current assignee: Jiangsu University
Priority date: 2011-08-02
Filing date: 2011-08-02
Publication date: 2014-12-24
Anticipated expiration: 2031-08-02
Also published as: CN102355235A

Abstract

The invention discloses a multiple input and multiple clock D trigger with a maintaining obstructive type. The trigger comprises a multiple-input basic latch and two or more than two input units. Two output terminals of any the input unit are respectively connected with an input terminal of the multiple-input basic latch so as to form a maintaining obstructive D trigger. The input units include data input terminals and clock trigger terminals. According to the invention, the D trigger can be utilized as a common memory; and the D trigger can also be applied to a design of a sequential circuit, especially to designs of a distributed system and an asynchronous circuit, wherein the distributed system and the asynchronous circuit are driven by events. Moreover, compared with the current trigger, the D trigger enables the circuit of trigger to be directly driven by events in a multi-path data input situation; circuit selection by data is simple; and the storage speed is fast.

Description

A kind of multi input-clock maintenance obstruction type JK d type flip flop

Technical field

The invention belongs to electronic technology field, be specifically related to a kind of flip-flop circuit, particularly a kind of have the maintenance obstructive type d type flip flop of multichannel data input and multiple clock trigger end and have the preferential circuit of triggering.

Background technology

Trigger is a kind of device with memory function, for forming various sequential logical circuit in Digital Electronic Technique.Trigger has polytype: be divided into level triggers by triggering mode, principal and subordinate triggers, edging trigger; Trigger, d type flip flop, JK flip-flop, T trigger etc. are divided by logic function.The characteristic triggering mode of trigger and logic function are described, and triggering mode, for determining state variation feature, namely receives the mode that input signal changes state; Logic function determines the direction of state variation, i.e. secondary state value.Existing trigger is all individual data input and single clock trigger end.

Because existing trigger only has a clock trigger end, therefore in the design of synchronous circuit, the clock trigger end of all triggers all links together.Along with improving constantly of integrated circuit integrated level, the clock skew that this mode causes, clock load electric current, power consumption, electromagnetic interference etc. are particularly thorny, be that the distributed system that drives and asynchronous circuit overcome the above-mentioned shortcoming of synchronous circuit well with event, but the inconvenience of existing trigger is used for event being the design of distributed system and the asynchronous circuit driven.

Summary of the invention

The object of the present invention is to provide a kind of maintenance obstructive type d type flip flop with multichannel data input and multiple clock trigger end, the every circuit-switched data input of this d type flip flop is a corresponding clock trigger end respectively, and each clock trigger end is used for acceptance external trigger.

Technical scheme of the present invention is: a kind of multi input-clock maintenance obstruction type JK d type flip flop, comprises a basic latch of multi input and two and above input unit; Two outputs of arbitrary described input unit are connected respectively to the input of the basic latch of described multi input, maintain obstructive type d type flip flop to form; Described input unit comprises data input pin and clock trigger end.

Further, described input unit is made up of two basic latchs.

Further, described multi input-clock maintenance obstruction type JK d type flip flop comprises priority circuit, and described priority circuit output is linked into the clock trigger end of described input unit.

Further, described priority circuit comprises more than one AND circuit, fewer than described input unit number one of the number of described AND circuit; Except the described input unit that priority is the highest, the input of arbitrary described AND circuit connects the clock signal of all high priority input units and the clock signal of be connected input unit.

Further, described input unit is 3.

Advantageous Effects of the present invention is: all corresponding clock trigger end of each data input pin of multi input-clock maintenance obstruction type JK d type flip flop, and the clock trigger end of trigger is used for acceptance external trigger.When external event occurs, the data in corresponding data input pin are latched.When multiple event arrives simultaneously, in order to avoid causing data collision, have employed priority circuit, improving described multi input-clock maintenance obstruction type JK d type flip flop circuit, the clock trigger end that priority can be allowed the highest triggers.The present invention can be used as common storage, is applied to the design of sequence circuit, particularly by the design of event driven distributed system and asynchronous circuit, compared with existing trigger, when multichannel data inputs, directly by event-driven, data selection circuit is simple, and storage speed is fast.

Accompanying drawing explanation

Fig. 1 is the circuit theory diagrams that 3 input-3 clocks maintain obstructive type d type flip flop

Fig. 2 is that 3 input-3 clocks maintain obstructive type d type flip flop functional simulation figure

Fig. 3 is the circuit theory diagrams of 3 input-3 clocks maintenance obstructive type d type flip flops of band priority

Fig. 4 is that 3 input-3 clocks of band priority maintain obstructive type d type flip flop functional simulation figure

embodiment

Fig. 1 is the circuit theory diagrams of one embodiment of the present of invention, is the d type flip flop of the maintenance choke structure of 3 input-3 clock trigger ends.Wherein NAND gate I20, I21, I22, I25 form the first input unit, NAND gate I17, I18, I19, I24 form the second input unit, NAND gate I14, I15, I16, I23 form the 3rd input unit, and it comprises three clock trigger ends cp1, cp2, cp3 of three data input pins d1, d2, d3 and correspondence respectively.I12, I13 form the basic latch of multi input.NAND gate I20, I21, I22, I25, I12, I13 NAND gate circuit form the d type flip flop that first group maintains choke structure, NAND gate I17, I18, I19, I24, I12, I13 form the d type flip flop that second group maintains choke structure, and NAND gate I14, I15, I16, I23, I12, I13 form the d type flip flop that the 3rd group maintains choke structure.

In embodiment, the d type flip flop of each group maintenance choke structure forms with the basic latch that NAND gate is formed by 3, as first group maintains two basic responsive outer input data d1 and clock cp1 of NAND gate I20, I21 and NAND gate I25 in the d type flip flop of choke structure, I22 formation, their output is as S, R signal, control the state of the 3rd the basic latch be made up of NAND gate I12, I13, namely first group maintains the state of the d type flip flop of choke structure.The d type flip flop operation principle that second and third group maintains choke structure is identical with first group.Three groups of inputs, only have one group under normal circumstances effectively, other two groups is all high level.Other multi input-clock maintenance obstruction type JK d type flip flop, according to the difference of data input pin number, can expand and obtain by circuit structure according to Fig. 1.

Now for first group in three groups of inputs, first group of of forming maintains the d type flip flop of choke structure.This trigger forms with the basic latch that NAND gate is formed by 3, wherein two basic responsive outer input data d1 and clock cp1 of NAND gate I20, I21 and NAND gate I25, I22 formation, their output, as the direct reduction (R) of the 3rd the basic latch be made up of I12, I13 and direct asserts signal (S), determines the state of trigger.Its operation principle is as follows:

(1) as cp1=0, NAND gate I21 and I25 is blocked, and its output is 1, output latch is made to be in hold mode, output q and nq of trigger does not change state, and NAND gate I20 and I22 two doors open by the feedback signal of NAND gate I21 and I25 respectively simultaneously, NAND gate I22 is exported be , I20 exports as d1.D1 signal enters trigger, for flip-flop states refreshes ready.

(2) moment after cp1 becomes 1 by 0, NAND gate I21 and I25 opens, and their output state is determined by the output state of I20 and I22, and the two is complementary forever, ensure that latch constraints=0, from the logic function of basic latch, at this moment , the logical value that d1 before this pressed by trigger refreshes.

(3) during cp1=1, two the basic latchs be made up of respectively NAND gate I20, I21 and NAND gate I25, I22 can ensure that the output state of NAND gate I21, I25 is constant, make flip-flop states not by the impact that input signal d1 changes.When q=1, NAND gate I21 output state is 0, then blocked by NAND gate I20 and I25.It is 1 that the feedback line of NAND gate I21 to I20 makes NAND gate I20 export, and plaing a part to maintain NAND gate I21 output is 0, thus maintains 1 state of trigger, is called and puts 1 maintenance line; It is 1 that the feedback line exporting NAND gate I25 to of NAND gate I21 makes NAND gate I25 export, although the change during this period of d1 signal may make I22 export corresponding change, but the output state of NAND gate I25 can not be changed, thus block d1 end input set to 0 signal, be called and set to 0 choke line.When q=0, it is 0 that NAND gate I25 exports, then NAND gate I22 is blocked, it is 1 that NAND gate I22 is exported, and namely blocks the approach that d1=1 signal enters trigger, the output of NAND gate I22 again with cp1=1, it is 1 acting in conjunction that NAND gate I21 exports, NAND gate I25 is exported and is maintained 0, and trigger is maintained 0 state, therefore feedback line NAND gate I25 being exported to NAND gate I22 is called and puts 1 obstruction, sets to 0 maintenance line.

Functional simulation (D1 in Fig. 2, D2, D3, the CP1 that 3 input-3 clocks maintain obstructive type d type flip flop shown in Fig. 2, CP2, CP3, Q, NQ corresponds respectively to the d1 in Fig. 1, d2, d3, cp1, cp2, cp3, q, nq), as can be seen from Figure 2, when CP1 first pulse arrives, the state due to data input pin D1 is low level (0 state), and thus output Q is low level; When CP1 second pulse arrives, the state due to data input pin D1 is high level (1 state), and thus output Q becomes high level at the rising edge time of CP1.Can see equally, when the rising edge of CP2 pulse arrives, data D2 be delivered to output Q; When the rising edge of CP3 pulse arrives, data D3 is delivered to output Q.

Multi input-clock maintenance obstruction type JK d type flip flop can realize the latch of multichannel data, the feature of the common storage be made up of it is that memory has multiple data input pin, each data channel respectively corresponding its stores instruction, access flexibly, improve the storage speed of memory, reduce the complexity of control circui, be particularly suitable for the design by event driven distributed system and asynchronous circuit.

Fig. 3 makes each shot clock signal cp1, cp2, cp3 receive the input of priority circuit on the basis that 3 input-3 clocks shown in Fig. 1 maintain obstructive type d type flip flop, priority circuit is made up of two AND circuit I26, I27, and each clock trigger end of multi input-multi-clock trigger end d type flip flop is received in the output of priority circuit again.In figure, cp1 and cp2 accesses AND circuit I26, AND circuit I26 and outputs to the clock trigger end that second group maintains the d type flip flop of choke structure; Cp1, cp2 and cp3 access AND circuit I27, AND circuit I27 and output to the clock trigger end that the 3rd group maintains the d type flip flop of choke structure.

When cp1 rising edge arrives, AND circuit I26 and I27 is blocked, cp2 and cp3 is ineffective; When cp1 is low level and cp2 rising edge arrives, I27 is blocked, and cp3 is ineffective.Therefore, the priority orders of this circuit is cp1>cp2>cp3.

Fig. 4 is the functional simulation figure (D1 in Fig. 4, D2, D3, CP1, CP2, CP3, Q, NQ correspond respectively to the d1 in Fig. 3, d2, d3, cp1, cp2, cp3, q, nq) of 3 input-3 clocks maintenance obstructive type d type flip flops of band priority.As shown in Figure 4, Q=D1 when 3rd pulse of CP1 and second pulse of CP2 arrive simultaneously, Q=D2 when 3rd pulse of CP2 and first pulse of CP3 arrive simultaneously, Q=D1 when 4th pulse of CP1 and second pulse of CP3 arrive simultaneously, trigger exports in strict accordance with expection priority orders, and the correct output of waveform describes the correctness of the priority orders of the multi input-clock maintenance obstruction type JK d type flip flop of band priority.

The present invention can be used as common storage, is applied to the design of sequence circuit, and compared with existing trigger, when multichannel data inputs, directly by event-driven, data selection circuit is simple, and storage speed is fast.It is in the distributed system and asynchronous circuit driven with event that the present invention is particularly suitable for those, and for Handshake Protocol, FPGA circuit etc.

The present invention has more than and is confined to above-mentioned embodiment; persons skilled in the art are according to technology contents disclosed by the invention; other multiple embodiments can be adopted to implement the present invention; therefore; the project organization of every employing multi input-multi-clock of the present invention, clock priority circuit and thinking; be applied to other versions or through the trigger of conversion and the application circuit that is made up of these triggers, all fall into the scope of protection of the invention.

Claims

1. multi input-clock maintenance obstruction type JK d type flip flop, comprises a basic latch of multi input and two and above input unit; It is characterized in that: two outputs of arbitrary described input unit are connected respectively to the input of the basic latch of described multi input, maintain obstructive type d type flip flop to form; Described input unit comprises data input pin and clock trigger end; Described input unit is made up of two basic latchs; Described two basic latchs have an input to be described clock trigger end; Described clock trigger end sends pulse signal, and described pulse signal is edging trigger mode, and described each clock trigger end is used for acceptance external trigger.

2. a kind of multi input-clock maintenance obstruction type JK d type flip flop according to claim 1, it is characterized in that: described multi input-clock maintenance obstruction type JK d type flip flop comprises priority circuit, described priority circuit output is linked into the clock trigger end of described input unit.

3. a kind of multi input-clock maintenance obstruction type JK d type flip flop according to claim 2, is characterized in that: described priority circuit comprises one and above AND circuit, fewer than described input unit number one of the number of described AND circuit; Except the described input unit that priority is the highest, the input of arbitrary described AND circuit connects the clock signal of all high priority input units and the clock signal of be connected input unit.

4. a kind of multi input-clock maintenance obstruction type JK d type flip flop according to claim 3, is characterized in that: described input unit is 3.