CN102360342A - Solid state disk for rapidly storing and displaying massive image data - Google Patents
Solid state disk for rapidly storing and displaying massive image data Download PDFInfo
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- CN102360342A CN102360342A CN2011103053685A CN201110305368A CN102360342A CN 102360342 A CN102360342 A CN 102360342A CN 2011103053685 A CN2011103053685 A CN 2011103053685A CN 201110305368 A CN201110305368 A CN 201110305368A CN 102360342 A CN102360342 A CN 102360342A
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Abstract
The invention relates to a solid state disk for rapidly storing and displaying massive image data, which comprises a hardware architecture and a software algorithm for rapidly storing and displaying the massive image data. On the hardware architecture, solid state storage medium is reasonably and efficiently organized through comprehensive utilization of a channel internal bus extension technology, a channel internal pipelining technology and a multichannel parallel technology, so that the access speed of the storage medium is improved, and the data-transfer capacity of a system is improved through utilizing a PCIE (Peripheral Component Interconnect Express) interface to transfer data; and on a software architecture, rapid storage and display of the image data is mainly realized through a blocking storage and address mapping technology of the image data. The channel internal bus extension technology, the channel internal pipelining technology and the multichannel parallel technology are comprehensively utilized aiming at the characteristics of the massive image data, so that the organization of FLASH is more reasonable and efficient.
Description
Technical field
The present invention relates to solid state hard disc and magnanimity image data field of storage, is a kind of quick storage and quick viewing hardware framework and software algorithm to the magnanimity image data.Specifically, be exactly through reasonable effective organization solid storage medium (Flash), comprehensively use passage internal bus expansion technique, the interior pipelining of passage and multi-channel parallel technology to constitute and be applicable to magnanimity image data quick storage and viewing hardware framework; Subdivision storage and map addresses technology through image data have constituted software algorithm of the present invention.
Background technology
Along with the development that images such as remote sensing and aerial survey obtain technology, various novel sensors continue to bring out, and type, the rank of image data are enriched constantly, demonstrate the characteristic of multi-format, polymorphic type, multiple dimensioned, magnanimity and distributed storage.In recent years, as the air map picture on digital earth basis, more and more widely in the application of survey of territorial resources, forest fire protection, mitigation, city planning, superprojects design aspects such as (sending) like Three Gorges Projects, the south water to north, western gas east.With regard to present level of hardware, can obtain the especially big coloured image of GB.The mass image data storehouse that constitutes with remote sensing or aerial survey reaches the TB level.To high-resolution coloured image like this, in order to see details, generally without lossy compression method.The single width size is just reached the image more than the GB; The user generally can be not once show all Data Loadings in the internal memory or handles; Even if strengthened internal memory, once with all Data Loadings in internal memory, computing machine also can slow in reacting, film flicker.In the face of the large nuber of images of TB level, some are nonconforming if do not pass through the fast browsing rejecting, will cause googol according to redundancy.
At present; The magnanimity image data is carried out quick storage; Mainly be to utilize disk to make up RAID; Be RAID (Redundant Array of Independent Disks) technology, its basic thought is through a parallel jumbo disk array, the function of realization raising hard-disk capacity and performance of being merged into of a plurality of hard disks that capacity is less.But because the intrinsic shortcoming of disk itself (as speed slowly, random access performance difference etc.), though memory capacity can satisfy the storage demand of system, speed far can not meet the demands.The method that the magnanimity image data shows fast; Mainly be to utilize memory management technology at present; Mainly comprise piecemeal technology, image pyramid generation technique, image cache generation technique of magnanimity remote sensing image data etc.; Because the Installed System Memory capacity is limited, the method can not fundamentally solve the fast access difficult problem of mass data.
Summary of the invention
The present invention relates to solid state hard disc and magnanimity image data field of storage, is a kind of quick storage and quick viewing hardware framework and software algorithm to the magnanimity image data.Mainly be to come reasonable effective organization solid storage medium (Flash) on the hardware structure through pipelining and multi-channel parallel technology in comprehensive use passage internal bus expansion technique, the passage; To improve the access speed of storage medium, improve the ability of system transmissions data through utilizing PCIE interface transmission data; Mainly quick storage and the demonstration that piecemeal storage and map addresses technology through image data realize image data on the software architecture.
System mainly is made up of hardware structure and software architecture two parts.Hardware structure mainly comprises the PCIE interface, based on hard disk controller and the FLASH memory module of FPGA, wherein the hard disk controller based on FPGA is the control core of total system, is connected with hard disk Host through the PCIE interface; Hard disk controller based on FPGA is connected with the FLASH memory module through the FLASH interface logic.Software architecture mainly comprises the piecemeal storage policy of image data and the map addresses strategy of block data etc.
The PCIE interface is the general data path of native system, accomplishes data transfer task between main frame Host and the hard disk.Native system adopts the PCIE interface of 8 Lane, and each Lane is made up of two pairs of differential lines, and 8 Lane are totally 16 pairs of differential lines, inserts 16 pairs of RocketIO pins of FPGA respectively.It is right that the difference pin of assurance PCIE inserts the difference pin of FPGA, and guarantee that at least two pairs of differential lines of same Lane insert among the same Bank of FPGA simultaneously.PCIE adopts PCI Express 1.0 standards.
Hard disk controller based on FPGA is the control core of native system, and the task of its completion mainly comprises three aspects: the realization of the PCIE agreement of 8 Lane, the realization of the interface logic of FLASH and the conversion of file system etc.The PCIE agreement that realizes based on the hard disk controller of FPGA comprises transaction layer, data link layer and Physical layer in data message transmission and the reception process; Wherein Physical layer is realized by the RocketIO that FPGA carries, and transaction layer, data link layer are realized by the Hardware Description Language VHDL programming; The interface logic of FLASH is mainly accomplished the reading and writing of FLASH and operation such as is wiped; Document conversion system is accomplished the conversion of the file system of main frame Host to FLASH, mainly comprises map addresses, bad block management and loss equalizing etc.
The FLASH memory module is the storage medium part of native system, and through reasonable effective organization multi-disc FLASH collaborative work, the main task of completion is to realize depositing in, read and preservation etc. of data under based on the control of the hard disk controller of FPGA.The FLASH organizational form that native system uses comprises pipelining technique and multi-channel parallel method in internal bus extended method, the passage.Pipelining technique mainly is to be used for reducing the influence of FLASH automated programming time to system speed in the passage, shared data bus between each the sheet FLASH in the streamline and control bus is separate, and this is the application of traditional pipelining technique in solid-state storage; Expansion of passage internal bus and multi-channel parallel method then are the special applications to solid-state storage; Extension to the conventional bus extended method; Wherein passage internal bus extended method is that data line is expanded, and shares control signal between each chip of expansion and data bit width is the summation of each sheet FLASH; The multi-channel parallel method is based on the thought of multidiameter delay, parallel carrying out between each passage, and each passage all comprises the bus expansion in streamline and the passage, and data bus and the address bus of expanding each sheet FLASH are all separate.
The piecemeal storage policy of image data mainly is under traditional mode, to store and visit all very slow deficiency to jumbo image data; Jumbo image data is divided into a lot of pieces; To deposit in FLASH different in the same passage or the different FLASH passage storage through the bus expanding method in the passage and pipelining technique or multi-channel parallel method quickening image especially coherent video data and reading and display speed by the piecemeal that connects each other in.Solved the difficult problem that image data shows fast.
Address mapping method is the major part of filesystem conversion, and the main task of its completion is to accomplish the conversion of the file system (like FAT32 under the Windows and NTFS) of main frame Host to the FLASH file system.On the basis of traditional map addresses; The design makes full use of the organizational structure of multi-disc FLASH; Proposed piecemeal and relevant image data deposit different phy chips in, realize image data among the FLASH storage, read acceleration, improve the display speed of magnanimity image data simultaneously.
Detailed process is: data are write fashionable; The PCIE interface receives the data message from main frame Host; After Physical layer, link layer and the transaction layer of PCIE, obtain address, instruction and data-signal in the data message; FPGA is according to the big or small of image number and combine the characteristics of FLASH that image data is carried out piecemeal, by piecemeal image data map addresses strategy different image data piecemeals is mapped to different physics FLASH unit, is accomplished the write operation of data by the FLASH interface logic; When data are read; Receive data message by the PCIE interface equally from main frame Host; After Physical layer, link layer and the transaction layer of PCIE, obtain the size of address, instruction and reading of data in the data message; Accomplish the read operation of data by the FLASH interface logic, the data of reading in by different FLASH through before the contrary strategy of image data partition strategy obtain the complete image data that need read, and be sent to main frame by the PCIE interface.
Major advantage of the present invention is:
1, use the PCIE interface of 8 Lane to eliminate the bottleneck on the hard disc data transmission mode, the speed summation of 8 Lane reaches 2000MB/S;
2, FPGA has accomplished multi-functionals such as comprising PCIE agreement, FLASH interface protocol, filesystem conversion and system's control, has greatly improved the integrated level of system;
3, to the characteristics of magnanimity image data,, make that organizing of FLASH is reasonable more, efficient through the comprehensive use of pipelining and multi-channel parallel technology in the bus expansion technique in the passage, the passage.
4, proposed to the piecemeal memory technology of magnanimity image data and the map addresses strategy of different piecemeal image datas; In conjunction with pipelining and multi-channel parallel technology in the passage internal bus expansion technique of FLASH, the passage, make to be greatly improved for the storage of mass data and visit and display speed.
Description of drawings does
Fig. 1 is the system architecture synoptic diagram.
Fig. 2 is the system hardware detailed maps.
Fig. 3 is image data piecemeal and map addresses detailed maps.
The practical implementation method
The practical implementation of magnanimity image data storage hard disk mainly comprises the enforcement of hardware structure and enforcement two parts of software architecture.The wherein enforcement of hardware structure mainly comprises interconnected between tissue and above three parts of PCIE Interface design, FPGA circuit design, storage medium FLASH; The enforcement of software architecture mainly comprises the realization of PCIE agreement, conversion, image block and the map addresses of file system and the design of FLASH interface logic etc.
The practical implementation of hardware structure
The practical implementation of hardware structure is signal path to be provided and to guarantee efficiently interconnected between the multi-disc FLASH for system.Mainly comprise interconnected between tissue and above three parts of PCIE Interface design, FPGA circuit design, storage medium FLASH.
The PCIE interface is accomplished the transmission tasks of data message between main frame Host and the hard disk.The PCIE interface that native system adopts is made up of 8 Lane; Each Lane all has two pairs of differential lines; A pair of being used for is sent to hard disk with data from main frame, and another is sent to main frame with data from hard disk to being used for, and 8 Lane are totally 16 pairs of differential lines; Insert 16 pairs of RocketIO pins of FPGA respectively; It is right that the difference pin of assurance PCIE inserts the difference pin of FPGA, and guarantee that at least two pairs of differential lines of same Lane insert among the same Bank of FPGA simultaneously, and PCIE of the present invention adopts PCI Express 1.0 standards.
The FPGA circuit is the control core of native system, and the task of its completion mainly comprises realization and the conversion of file system of interface logic of realization, the FLASH of PCIE agreement.The PCIE agreement of 8 Lane realizes mainly comprising the realization of transaction layer, data link layer and Physical layer in data message transmission and the reception process; Wherein Physical layer is realized by the RocketIO that FPGA carries; PCIE 1.0 standards that the present invention adopts; The serial rate of each Lane is 2.5Gbps, and the FPGA that XILINX company has the RocketIO function all can satisfy this rate requirement; Transaction layer, data link layer are realized by the Hardware Description Language VHDL programming, comprise the merging of 8/10bit coding and each Lane data.The interface logic of FLASH requires to accomplish the read-write sequence of the chip that uses according to the read-write of FLASH, and accomplishes corresponding read-write operation according to the instruction based on the hard disk controller of FPGA.Document conversion system is accomplished the conversion of the file system of main frame Host to FLASH; Mainly comprise mapping, bad block management and the loss equalizing etc. of host address to the FLASH address; Wherein bad block management is to accomplish to prevent to cause the mistake that reads and writes data because of the bad piece that occurs in the FLASH course of work; Loss equalizing is to guarantee that each unit read-write number of times is balanced, prolongs the serviceable life of hard disk.
The tissue of storage medium FLASH is through organizing multi-disc FLASH collaborative work, and the main task of its completion is under the control based on the hard disk controller of FPGA, to realize that the parallel of data deposits in, reads and preserve.The FLASH organizational form that native system uses comprises pipelining technique and multi-channel parallel method in internal bus extended method, the passage.Wherein passage internal bus extended method is that the data bus is expanded, and shares control signal between each chip of expansion and data bit width is the summation of each sheet FLASH data bit width; Pipelining technique mainly is to be used for reducing the influence of FLASH automated programming time to system speed in the passage; Shared data bus and control bus is separate between each sheet FLASH of expansion; Guarantee that a slice FLASH another sheet FLASH when programming has so just increased the utilization factor of data bus at loading data; The multi-channel parallel method is based on the parallel thought of quickening; The parallel storage between each passage; Data bus and the address bus of expanding each sheet FLASH are all separate; After data were sent to the FIFO of each passage, the read-write operation of each passage all was parallel carrying out, and has no influence each other.
The practical implementation of software architecture
Software architecture mainly comprises the piecemeal storage policy of image data and the map addresses strategy of block data; The quick storage of accomplishing the magnanimity image data jointly by deblocking strategy and map addresses strategy with read, and realize that magnanimity counts the quick demonstration of image certificate.
The piecemeal storage policy of image data mainly is under traditional mode, to store and visit all very slow deficiency to jumbo image data; Jumbo image data is divided into a lot of pieces; Deposit the piecemeal that connects each other among the FLASH different in the same passage (being pipelining technique); The piecemeal that perhaps connects each other deposits in the different FLASH passages (being the multi-channel parallel method); Through the bus expanding method in the passage and pipelining technique and multi-channel parallel method, accelerate image especially the coherent video data storage and read and display speed.The size of image block is got 2 power power usually, the concrete characteristics that when selecting, will consider the FLASH data-storing and the least unit of Installed System Memory management.For NANDFLASH; Every page byte number should be 2KB, 4KB or 8KB etc.; Will consider the needs of data compression and the speed of hard disc data transmission in addition, the present invention takes the fixed size method of partition, and guarantees that the branch block size is the integral multiple of FLASH page or leaf size.According to so big or small piecemeal. the data of the integral multiple of each hard disk transmission one page or page or leaf capacity are consuming time very short; And because every page all has complete data; The transfer efficiency of data also is the highest like this, can be because of the data (least unit of reading among the FLASH is one page) that need read whole page or leaf in order to obtain some data in one page.
Address mapping method is the major part of filesystem conversion; The main task of its completion is to accomplish the conversion of the file system (like FAT32 under the Windows and NTFS) of main frame Host to the FLASH file system; Make full use of the organizational structure of multi-disc FLASH; Deposit the image data of piecemeal in different phy chip, realize image data among the FLASH storage, read acceleration, improve the display speed of magnanimity image data simultaneously.
Accompanying drawing 2 is a system hardware detailed data process flow diagram:
1.PCIE interface adopts the mode of 8 Lane; Accord with PCI Express1.0 standard; Accomplish the transmission of data message between this hard disk and the main frame Host in conjunction with the PCIE agreement of utilizing Hardware Description Language VHDL to write among the FPGA; Protocol analysis, wherein data message comprises information such as state that address, instruction, data and this hard disk that main frame sends upload, capacity.
2.FPGA circuit comprises that FPGA and FPGA are configuration circuits, the FPGA that selects for use will comprise the Physical layer that 16 RocketIO are used for realizing the PCIE agreement at least.
3. storage medium partly adopts internal bus extended method, the interior pipelining of passage and multi-channel parallel method that multi-disc FLASH is carried out effective organization; The progression of streamline is determined by the page or leaf automated programming time and the page data transmission time of selected chip jointly in the passage, and the parallel channel is counted viewing system total volume and rate request and decided.
4. power circuit is that system provides power supply.
5. clock circuit is that system provides required clock.
Accompanying drawing 3 is image data piecemeal and map addresses detailed maps:
1, the high capacity image data carries out piecemeal to it in system cache after the PCIE interface imports hard disk into, adopts fixed size, square piecemeal principle, and guaranteeing to divide block size is the integral multiple of FLASH page or leaf size.The size of each piecemeal is by the size of image data and the common decision of size of FLASH page or leaf, and the size of image block is got 2 power power usually, the concrete characteristics of when selecting, considering the FLASH data-storing and the least unit of Installed System Memory management.
2, on the different physical channel that the map addresses strategy of block data shines upon the image data after the piecemeal respectively, and the address mapping table in the change document conversion system.
Claims (6)
1. magnanimity image data quick storage shows solid state hard disc; Comprise quick storage and quick viewing hardware framework and software algorithm; It is characterized in that; Hardware structure mainly comprises the PCIE interface, based on hard disk controller and the FLASH memory module of FPGA, wherein the hard disk controller based on FPGA is the control core of total system, is connected with hard disk Host through the PCIE interface; Hard disk controller based on FPGA links to each other with the FLASH memory module through the FLASH interface logic; Adopt the PCIE interface of 8 Lane, each Lane is made up of two pairs of differential lines, and 8 Lane are totally 16 pairs of differential lines, inserts 16 pairs of RocketIO pins of FPGA respectively.
2. magnanimity image data quick storage according to claim 1 shows solid state hard disc; It is characterized in that; It is right that the difference pin of assurance PCIE inserts the difference pin of FPGA; And two pairs of differential lines that guarantee same Lane at least insert among the same Bank of FPGA simultaneously, and PCIE adopts PCI Express 1.0 standards.
3. magnanimity image data quick storage according to claim 1 shows solid state hard disc; It is characterized in that; The tissue of storage medium FLASH is through organizing multi-disc FLASH collaborative work, and the main task of its completion is under the control based on the hard disk controller of FPGA, to realize that the parallel of data deposits in, reads and preserve.
4. magnanimity image data quick storage according to claim 1 shows solid state hard disc; It is characterized in that; Software architecture mainly comprises the piecemeal storage policy of image data and the map addresses strategy of block data; The quick storage of accomplishing the magnanimity image data by the map addresses strategy of the piecemeal storage policy of image data and block data jointly with read, and realize that magnanimity counts the quick demonstration of image certificate.
5. magnanimity image data quick storage according to claim 1 shows solid state hard disc; It is characterized in that; The high capacity image data carries out piecemeal to it in system cache after the PCIE interface imports hard disk into, adopt fixed size; Square piecemeal principle, guaranteeing to divide block size is the integral multiple of FLASH page or leaf size.
6. magnanimity image data quick storage according to claim 1 shows solid state hard disc; It is characterized in that; On the different physical channel that the map addresses strategy of block data shines upon the image data after the piecemeal respectively, and the address mapping table in the change document conversion system.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103135945A (en) * | 2013-03-25 | 2013-06-05 | 中国人民解放军国防科学技术大学 | Multi-channel dynamic read-write dispatching method used in solid state drive (SSD) |
| WO2014094250A1 (en) * | 2012-12-19 | 2014-06-26 | 华为技术有限公司 | Data processing method and device |
| CN105426517A (en) * | 2015-12-02 | 2016-03-23 | 上海越峰信息科技有限公司 | Intelligent storage device with image processing function |
| CN105718411A (en) * | 2016-01-27 | 2016-06-29 | 哈尔滨工业大学 | Instrument-module universal interface assembly based on AXIe |
| CN107015629A (en) * | 2017-03-30 | 2017-08-04 | 联想(北京)有限公司 | Processing method and electronic equipment |
| CN107526691A (en) * | 2016-06-21 | 2017-12-29 | 深圳市中兴微电子技术有限公司 | A kind of buffer memory management method and device |
| WO2018006393A1 (en) * | 2016-07-08 | 2018-01-11 | SZ DJI Technology Co., Ltd. | Method and system for storing images |
| CN108008919A (en) * | 2017-12-22 | 2018-05-08 | 中国电子科技集团公司第五十四研究所 | A kind of high-speed data handles SSD |
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| WO2019228098A1 (en) * | 2018-05-30 | 2019-12-05 | 华为技术有限公司 | Data compression method and device |
| CN117472288A (en) * | 2023-12-27 | 2024-01-30 | 成都领目科技有限公司 | IO writing method and model based on RAID0 hard disk group |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030188099A1 (en) * | 2002-03-29 | 2003-10-02 | Emc Corporation | Communications architecture for a high throughput storage processor employing extensive I/O parallelization |
| US20080040520A1 (en) * | 2006-08-08 | 2008-02-14 | Jason Caulkins | Methods For Eliminating Intermediate Bussing And Bridging Requirements Between A Solid State Memory Device With PCI Controller And A Main System Bus |
| CN101833424A (en) * | 2010-03-26 | 2010-09-15 | 中国科学院光电技术研究所 | High speed storage and transmission device based on FPGA |
-
2011
- 2011-10-11 CN CN2011103053685A patent/CN102360342A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030188099A1 (en) * | 2002-03-29 | 2003-10-02 | Emc Corporation | Communications architecture for a high throughput storage processor employing extensive I/O parallelization |
| US20080040520A1 (en) * | 2006-08-08 | 2008-02-14 | Jason Caulkins | Methods For Eliminating Intermediate Bussing And Bridging Requirements Between A Solid State Memory Device With PCI Controller And A Main System Bus |
| CN101833424A (en) * | 2010-03-26 | 2010-09-15 | 中国科学院光电技术研究所 | High speed storage and transmission device based on FPGA |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014094250A1 (en) * | 2012-12-19 | 2014-06-26 | 华为技术有限公司 | Data processing method and device |
| CN103135945A (en) * | 2013-03-25 | 2013-06-05 | 中国人民解放军国防科学技术大学 | Multi-channel dynamic read-write dispatching method used in solid state drive (SSD) |
| CN105426517A (en) * | 2015-12-02 | 2016-03-23 | 上海越峰信息科技有限公司 | Intelligent storage device with image processing function |
| CN105426517B (en) * | 2015-12-02 | 2020-02-18 | 上海越峰信息科技有限公司 | Intelligent storage device with image processing function |
| CN105718411A (en) * | 2016-01-27 | 2016-06-29 | 哈尔滨工业大学 | Instrument-module universal interface assembly based on AXIe |
| CN107526691A (en) * | 2016-06-21 | 2017-12-29 | 深圳市中兴微电子技术有限公司 | A kind of buffer memory management method and device |
| WO2018006393A1 (en) * | 2016-07-08 | 2018-01-11 | SZ DJI Technology Co., Ltd. | Method and system for storing images |
| CN109478166A (en) * | 2016-07-08 | 2019-03-15 | 深圳市大疆创新科技有限公司 | For storing the method and system of image |
| CN107015629A (en) * | 2017-03-30 | 2017-08-04 | 联想(北京)有限公司 | Processing method and electronic equipment |
| CN107015629B (en) * | 2017-03-30 | 2022-05-31 | 联想(北京)有限公司 | Processing method and electronic device |
| CN108008919A (en) * | 2017-12-22 | 2018-05-08 | 中国电子科技集团公司第五十四研究所 | A kind of high-speed data handles SSD |
| WO2019228098A1 (en) * | 2018-05-30 | 2019-12-05 | 华为技术有限公司 | Data compression method and device |
| CN109446578A (en) * | 2018-09-28 | 2019-03-08 | 成都大公博创信息技术有限公司 | A kind of circuit design method of analog/digital and D/A converter |
| CN117472288A (en) * | 2023-12-27 | 2024-01-30 | 成都领目科技有限公司 | IO writing method and model based on RAID0 hard disk group |
| CN117472288B (en) * | 2023-12-27 | 2024-04-16 | 成都领目科技有限公司 | IO writing method and model based on RAID0 hard disk group |
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Application publication date: 20120222 |