CN102376673A - Packaging substrate and formation method thereof - Google Patents

Packaging substrate and formation method thereof Download PDF

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Publication number
CN102376673A
CN102376673A CN2010102491813A CN201010249181A CN102376673A CN 102376673 A CN102376673 A CN 102376673A CN 2010102491813 A CN2010102491813 A CN 2010102491813A CN 201010249181 A CN201010249181 A CN 201010249181A CN 102376673 A CN102376673 A CN 102376673A
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CN
China
Prior art keywords
conductive pattern
packaging
base plate
electroplated lead
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010102491813A
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Chinese (zh)
Inventor
吴东融
何昌立
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NANYA CIRCUIT BOARD CO Ltd
Nan Ya Printed Circuit Board Corp
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NANYA CIRCUIT BOARD CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NANYA CIRCUIT BOARD CO Ltd filed Critical NANYA CIRCUIT BOARD CO Ltd
Priority to CN2010102491813A priority Critical patent/CN102376673A/en
Publication of CN102376673A publication Critical patent/CN102376673A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

An embodiment of the invention provides a packaging substrate and a formation method thereof. The packaging substrate comprises the following parts: a substrate, a first conductive pattern with a first thickness on the substrate, a second conductive pattern with a second thickness on the second conductive pattern, wherein the second thickness is larger than the first thickness, and material of the first conductive pattern is same with material of the second conductive pattern; at least a first electroplated lead which is on the substrate and is electrically connected with at least a part of the first conductive pattern; at least a second electroplated lead which is on the substrate and is electrically connected with at least a part of the second conductive pattern, wherein a resistance value of the first electroplated lead is larger than a resistance value of the second electroplated lead. The embodiment of the invention provides a method of forming conductive patterns of different thicknesses on the substrate in one electroplate technical process, and technical time and cost are greatly reduced.

Description

Base plate for packaging and forming method thereof
Technical field
The present invention relates to a kind of base plate for packaging, particularly a kind of base plate for packaging with mould geat (mold gate) district.
Background technology
The normal gold (gold) that uses forms inner conductive path, the for example pad area on the base plate for packaging in the packaging body.Can be in routing between packaged chip and the base plate for packaging so that electrical signals between base plate for packaging and chip, transmit.
Yet the price of gold is very expensive and day by day rare, for loss of saving earth resource and the cost of manufacture that reduces packaging body.Industry is needed the technology of the consumption that reduces gold badly.
Summary of the invention
For overcoming defective of the prior art, one embodiment of the invention provides a kind of base plate for packaging, comprising: a substrate; One first conductive pattern is positioned on this substrate and has one first thickness; One second conductive pattern is positioned on this substrate and has one second thickness, and this second thickness is greater than this first thickness, and the material of this first conductive pattern is same as the material of this second conductive pattern; At least one first electroplated lead is positioned on this substrate and has electrical contact to this first conductive pattern of few part; And at least one second electroplated lead, be positioned on this substrate and have electrical contact to this second conductive pattern of few part, wherein the resistance value of this first electroplated lead is greater than the resistance value of this second electroplated lead.
One embodiment of the invention provides a kind of formation method of base plate for packaging, comprising: a substrate is provided; On this substrate, form at least one first electroplating region; On this substrate, form at least one second electroplating region; Form one first electroplated lead, electrically contact this first electroplating region; Form one second electroplated lead, electrically contact this second electroplating region, wherein the resistance value of this second electroplated lead is less than the resistance value of this first electroplated lead; This substrate is positioned in the electroplate liquid, and this electroplate liquid comprises a metal ion; And respectively through this first electroplated lead and this second electroplated lead and this first electroplated lead and this second electroplated lead are applied an electric current simultaneously; This metal ion is plated on respectively on this first electroplating region and this second electroplating region on and respectively at forming one first conductive pattern and one second conductive pattern on this first electroplating region and on this second electroplating region, wherein the thickness of this second conductive pattern is greater than the thickness of this first conductive pattern.
The embodiment of the invention provides the method that can in electroplating technology, just can on substrate, form out the conductive pattern of variable thickness; Can significantly reduce process time and cost, the economic benefits the when material of the conductive pattern of wherein electroplating with desire especially is noble metal are more remarkable.
For let above-mentioned purpose of the present invention, characteristic, and advantage can be more obviously understandable, following conjunction with figs. is elaborated.
Description of drawings
Figure 1A shows the vertical view of a kind of base plate for packaging that this case inventor is known.
Figure 1B shows the profile of the base plate for packaging of Figure 1A along tangent line B '-B '.
Fig. 2 shows the vertical view of base plate for packaging according to an embodiment of the invention.
The base plate for packaging of Fig. 3 A-Fig. 3 C displayed map 2 is along the series of process profile of tangent line 3-3 '.
Fig. 4 A-Fig. 4 J shows the vertical view of the electroplated lead of a plurality of embodiment according to the present invention.
Wherein, description of reference numerals is following;
100,200~substrate;
102~mould geat district;
102a, 104a~patterned conductive layer;
102b, 104b~gold layer;
104~pad area;
106,206~zone;
108,208~chip;
110,210~bonding wire;
202,204~conductive pattern;
202a, 204a~electroplating region;
202b, 204b~metal level;
L1, L2~electroplated lead;
T1, t2, t3, t4~thickness.
Embodiment
Below specify the present invention with embodiment and conjunction with figs., will be appreciated that following narration provides many various embodiment or example, in order to the same attitude of embodiment of the present invention.Element that the following stated is specific and arrangement mode are to the greatest extent simple description of the present invention.Certainly, these are only in order to give an example but not qualification of the present invention.In addition, in different embodiment, possibly use the label or the sign of repetition.These repeat to be merely simply clearly narrates the present invention, does not necessarily represent between the different embodiment that discussed and/or the structure to have any association.Moreover, when address that one first material layer is positioned on one second material layer or on the time, comprise that first material layer directly contacts with second material layer or be separated with one or the situation of more other materials layers.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.Moreover, the not shown or element described, the form of knowing for the those of ordinary skill in the affiliated technical field.
Before the explanation that gets into the present invention's enforcement, Figure 1A-Figure 1B explains the problem that this case inventor is found in the conjunction with figs..Figure 1A shows the vertical view of a kind of base plate for packaging that this case inventor is known.Figure 1B shows the profile of the base plate for packaging of Figure 1A along tangent line B '-B '.
Shown in Figure 1A and Figure 1B, base plate for packaging can comprise substrate 100, can have a plurality of regional 106 on it.Comprise at least one pad area 104 in each zone 106.Zone 106 can be in order to being provided with chip 108, and can between electrode (not shown) on the chip 108 and pad area 104, form bonding wire 110 (seeing Figure 1B) and make electrical signals be able between chip 108 and base plate for packaging, transmit.Usually, the bottom of base plate for packaging is also alternative to form soldered ball, and integrates with other electronic components through soldered ball.
Substrate 100 also comprises mould geat district 102, comprises a gold medal layer as the one of which.When a plurality of chips 108 being arranged at respectively on the corresponding zone 106, and form after the bonding wire 110, in chip, pad area 104, and bonding wire 110 on mould is set, and packing colloid is injected mould to form protective layer through the mould geat.Because the gold layer and the zygosity between packing colloid in mould geat district 102 are relatively poor, thereby can make things convenient for the carrying out of the subsequent technique behind the injecting glue.
Please with reference to Figure 1B, the generation type in general pad area 104 and mould geat district 102 is to adopt the mode of electroplating.For example, can be prior to forming patterned conductive layer 102a and patterned conductive layer 104a on the substrate 100.Patterned conductive layer 102a and patterned conductive layer 104a can through be formed on the substrate 100 or in electroplated lead and be electrically connected to the electrode (not shown) on the substrate 100 respectively.Then, can substrate 100 be positioned in the electroplate liquid that contains gold ion, and patterned conductive layer 102a and patterned conductive layer 104a be applied electric current via electrode.Then, through electrochemical reaction, the gold ion in the plating bath can be gone up deposition in patterned conductive layer 102a and patterned conductive layer 104a, thereby forms gold layer 102b and gold layer 104b, and wherein gold layer 102b has identical thickness with gold layer 104b.Patterned conductive layer 102a and gold layer 102b form mould geat district 102 jointly, and patterned conductive layer 104a and gold layer 104b form pad area 104 jointly.Therefore, on the whole the thickness t 1 in mould geat district 102 equals the thickness t 2 of pad area 104.
Pad area 104 forms the bonding wire 110 that electrically connects with chip because of need through routing technology on it, so the gold layer 104b of pad area 104 need have enough thickness so that routing technology is smooth.Yet for mould geat district 102, mainly in order to provide and the relatively poor surface of packing colloid engaging force, its thickness does not need to have higher thickness as the gold layer 104b of pad area 104 to gold layer 102b.Yet, when forming mould geat district 102 and pad area 104, with making the not high mould geat district 102 of thickness demand still have gold layer like pad area 104 general thick with above-mentioned technology.Moreover the area that mould geat district 102 is shared is generally the about more than 70% of all gold-plated zones on the substrate 100.So, will have the gold ion of suitable high-load expend the golden demand of reality not high mould geat district 102 on, the consumption that makes gold plating bath is increased, improve the technology cost greatly.
Gold ion in electroplate liquid expends in vain in the not high mould geat district 102 of the golden demand of reality; Or can use part that the patterning dry film forms pad area 104 with desire (promptly earlier; Patterned conductive layer 104a) cover and patterned conductive layer 102a exposed, then in patterned conductive layer 102a go up electroplate thinner thickness gold layer 102b to accomplish the making in mould geat district 102.Then, divest dry film, and form a patterning dry film in addition and patterned conductive layer 104a is exposed to cover mould geat district 102.Then, go up the thicker gold layer 104b of electroplating thickness to accomplish the making of pad area 104 in the patterned conductive layer 104a that exposes.At last, also need dry film is divested.
Though said method can form the mould geat district 102 of golden thinner thickness and practice thrift golden consumption of plating; Yet mould geat district 102 needs gradation to form with pad area 104; And need numerous and diverse Patternized technique, electroplating technology, with remove technology, quite expend cost of manufacture and time.
In order on base plate for packaging, to form the different conductive pattern of thickness more efficiently, this case inventor proposes another kind of novel base plate for packaging formation method.Below, conjunction with figs. is explained some possible execution modes of the embodiment of the invention.It should be noted that be convenient and simplified illustration, following explanation is an example with pad area in the base plate for packaging and mould geat district still.But those of ordinary skills have the conductive pattern demander of variable thickness such as when understanding on substrate, all can adopt the method for the embodiment of the invention to reach.Therefore, the embodiment of the invention is not defined for pad area and the mould geat district that forms in the base plate for packaging.
Fig. 2 shows the vertical view of base plate for packaging according to an embodiment of the invention.In one embodiment, base plate for packaging comprises substrate 200.Base plate for packaging also comprises first conductive pattern 202 that is positioned on the substrate 200, and is positioned at second conductive pattern 204 on the substrate, and it for example is positioned among the zone 206.The material of first conductive pattern 202 is same as the material of second conductive pattern 204.Base plate for packaging also comprises at least one first electroplated lead L1; Be positioned on the substrate 200 and have electrical contact to first conductive pattern 202 of few part; And at least one second electroplated lead L2, be positioned on the substrate 200 and have electrical contact to second conductive pattern 204 of few part.Wherein, the first electroplated lead L1 makes the resistance value of the resistance value of the electroplated lead of winning greater than second electroplated lead through special design.The thickness of first conductive pattern 202 is also thin than the thickness of second conductive pattern 204.Because the resistance value of the first electroplated lead L1 is bigger; When carrying out electroplating technology with during forming first conductive pattern 202 and second conductive pattern 204; Be passed to first conductive pattern, 202 current densities with less; Thereby can in electroplating technology among, on substrate, electroplate and be formed up to few two kinds of conductive patterns that thickness is different.
The base plate for packaging of Fig. 3 A-Fig. 3 C displayed map 2 is along the series of process profile of tangent line 3-3 '.Below, with the production method of the base plate for packaging of the process section explanation one embodiment of the invention that cooperates Fig. 3 A-Fig. 3 C.
Shown in Fig. 3 A, substrate 200 is provided, it for example is (but being not limited to) insulated substrate.Then, for example on substrate 200, form a conductive layer, and then it is patterned as the first electroplating region 202a and the second electroplating region 204a through printing, coating, physical vapour deposition (PVD), chemical vapour deposition (CVD) or other technology that is fit to.For example, can adopt exposure, development, and etch process and with conductive layer patternization.The material of the first electroplating region 202a and the second electroplating region 204a for example can include, but is not limited to the material or the aforesaid combination of copper, aluminium, tungsten, gold, other metals, other tool conductivity.
In subsequent technique, the first electroplating region 202a will plate conductive layer and become first conductive pattern, and the second electroplating region 204a also will plate the conductive layer of same kind in same electroplating technology and become second conductive pattern.Second conductive pattern can be positioned among the zone 206.
In one embodiment, will form (but being not limited to) mould geat district, promptly form first conductive pattern 202 (Fig. 3 B) in the first electroplating region 202a place.Therefore, the first electroplating region 202a can be along the edge of substrate 202 and is horizontally disposed with.In one embodiment, will form (but being not limited to) pad area, promptly form second conductive pattern 204 (Fig. 3 B) in the second electroplating region 204a.In one embodiment, the shared area of first conductive pattern 202 is greater than the shared area of second conductive pattern 204.For example, first conductive pattern, 202 shared areas can be about 1~1000 times of the shared area of second conductive pattern 204.In another embodiment, first conductive pattern, 202 shared areas can be about 5~100 times of the shared area of second conductive pattern 204.In another embodiment, first conductive pattern, 202 shared areas can be about 10~50 times of the shared area of second conductive pattern 204.Perhaps, under other situations, the shared area of first conductive pattern 202 can be less than the shared area of second conductive pattern 204.In one embodiment, first conductive pattern, 202 shared areas can be about 0.05~100 times of the shared area of second conductive pattern 204.
The first electroplating region 202a and the second electroplating region 204a can electrically contact with the first electroplated lead L1 and the second electroplated lead L2 respectively.The first electroplated lead L1 has the also high resistance value than the second electroplated lead L2 through special design.The first electroplated lead L1 and the second electroplated lead L2 are not shown among Fig. 3 A, and its position can be with reference to the sketch map of Fig. 2.It should be noted that so the first electroplated lead L1 and the second electroplated lead L2 are not limited to be formed at position shown in Figure 2, and its can be formed on the substrate 200 or among.The first electroplated lead L1 and the second electroplated lead L2 can be for example partly or entirely in patterned conductive layer when forming the first electroplating region 202a and the second electroplating region 204a, patterned simultaneously and form.Perhaps, the first electroplated lead L1 and the second electroplated lead L2 can comprise the intraconnections that is pre-formed in substrate 200.
Then, shown in Fig. 3 B, the structure shown in Fig. 3 A is positioned in the electroplate liquid to carry out electroplating technology.For example can comprise precious metal ion in the electroplate liquid and can be in order to electroplate noble metal, wherein noble metal for example includes, but is not limited to gold, silver, platinum, other suitable noble metals or aforesaid combination.It should be noted that so though the embodiment of the invention has than the remarkable economical effect, the embodiment of the invention is not limited thereto on the application surface of electroplating noble metal.In other embodiments, also can comprise non-noble metal metal ion in the electroplate liquid and can be, for example (but being not limited to) copper, aluminium, other suitable metals or aforesaid combination in order to electroplate other metal level.
After substrate 200 is put into electroplate liquid, can be through preformed electroplated electrode (not shown) on the substrate 200, and via the first electroplated lead L1 and the second electroplated lead L2 the first electroplating region 202a and the second electroplating region 204a are applied electric current respectively.After energising, the metal ion in the electroplate liquid will be gone up deposition and form metal level 202b and 204b respectively in the first electroplating region 202a and the second electroplating region 204a.Because the resistance value of the first electroplated lead L1 is higher than the resistance value of the second electroplated lead L2, the current density that therefore is passed to the first electroplating region 202a is with less and make metal level 202b thinner.Shown in Fig. 3 B, the first electroplating region 202a and metal level 202b are common to form first conductive pattern 202, and common second conductive pattern 204 that forms of the second electroplating region 204a and metal level 204b.The thickness t 3 of first conductive pattern 202 is less than the thickness t 4 of second conductive pattern 204.In first conductive pattern 202 and second conductive pattern 204, the metal level 202b of institute's electroplating deposition and metal level 204b also all become conductive pattern respectively.The thickness of conductive pattern (metal level 202b) is less than the thickness of conductive pattern (metal level 204b).
Then, shown in Fig. 3 C, in one embodiment, can in zone 206, chip be set, and between chip and pad area 204, form bonding wire 210.Then, technology that can be well known to those of ordinary skill in the art and accomplish the injection of packing colloid.Though, the thinner thickness of first conductive pattern 202, when its material for example is when gold, still not good and can be beneficial to the carrying out of subsequent technique with the zygosity of packing colloid.
Therefore,, the different conductive pattern of thickness can be in electroplating technology, formed out, process time and cost can be significantly reduced through above-mentioned method.Especially, when the material of being electroplated is expensive noble metal, more cost of manufacture can be significantly reduced, unnecessary waste can be avoided.
Below, illustrate the method that the resistance value that makes the first electroplated lead L1 is higher than the resistance value of the second electroplated lead L2.In one embodiment, the first electroplated lead L1 can comprise a resistance part and its resistance value is improved.Yet the cost of resistance part is higher, and needs extra technology.In another preferred embodiment, the method through patterning makes the resistance value of the first electroplated lead L1 be higher than the resistance value of the second electroplated lead L2.In addition, the first electroplated lead L1 and the second electroplated lead L2 also patternable from order to form the same conductive layer of the first electroplating region 202a and the second electroplating region 204a.Therefore, can need not increase any cost of manufacture fully, just can form out the first higher electroplated lead L1 of resistance value.
Fig. 4 A-Fig. 4 J shows the vertical view of the first electroplated lead L1 of a plurality of embodiment according to the present invention.Can find out by vertical view and can make the first electroplated lead L1 comprise hole part, sweep, sharp-pointed part, serrated portion, bending part or aforesaid combination via Patternized technique.And its pattern and quantity all can adjust according to circumstances.Via above-mentioned various patterning modes, the resistance value of the first electroplated lead L1 is improved, and the conductive pattern of different-thickness can be formed in same electroplating technology.
As above-mentioned; The embodiment of the invention provides the method that can in electroplating technology, just can on substrate, form out the conductive pattern of variable thickness; Can significantly reduce process time and cost, the economic benefits the when material of the conductive pattern of wherein electroplating with desire especially is noble metal are more remarkable.
Though the present invention has disclosed preferred embodiment as above; Right its is not in order to limit the present invention; Any those of ordinary skills; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the protection range that claim defined of enclosing.

Claims (15)

1. base plate for packaging comprises:
One substrate;
One first conductive pattern is positioned on this substrate and has one first thickness;
One second conductive pattern is positioned on this substrate and has one second thickness, and this second thickness is greater than this first thickness, and the material of this first conductive pattern is same as the material of this second conductive pattern;
At least one first electroplated lead is positioned on this substrate and has electrical contact to this first conductive pattern of few part; And
At least one second electroplated lead is positioned on this substrate and has electrical contact to this second conductive pattern of few part, and wherein the resistance value of this first electroplated lead is greater than the resistance value of this second electroplated lead.
2. base plate for packaging as claimed in claim 1, wherein this first conductive pattern comprises a noble metal.
3. base plate for packaging as claimed in claim 2, wherein this noble metal comprises gold.
4. base plate for packaging as claimed in claim 1, wherein the shared area of this first conductive pattern is greater than the shared area of this second conductive pattern.
5. base plate for packaging as claimed in claim 1, wherein this first conductive pattern is a mould geat district.
6. base plate for packaging as claimed in claim 1, wherein this second conductive pattern is a pad area.
7. base plate for packaging as claimed in claim 1, wherein this first electroplated lead comprises hole part, a sweep, a sharp-pointed part, a serrated portion, a bending part or aforesaid combination.
8. the formation method of a base plate for packaging comprises:
One substrate is provided;
On this substrate, form at least one first electroplating region;
On this substrate, form at least one second electroplating region;
Form one first electroplated lead, electrically contact this first electroplating region;
Form one second electroplated lead, electrically contact this second electroplating region, wherein the resistance value of this second electroplated lead is less than the resistance value of this first electroplated lead;
This substrate is positioned in the electroplate liquid, and this electroplate liquid comprises a metal ion; And
Respectively through this first electroplated lead and this second electroplated lead and this first electroplated lead and this second electroplated lead are applied an electric current simultaneously; This metal ion is plated on respectively on this first electroplating region and this second electroplating region on and respectively at forming one first conductive pattern and one second conductive pattern on this first electroplating region and on this second electroplating region, wherein the thickness of this second conductive pattern is greater than the thickness of this first conductive pattern.
9. the formation method of base plate for packaging as claimed in claim 8, wherein this metal ion comprises a precious metal ion.
10. the formation method of base plate for packaging as claimed in claim 8, wherein this metal ion comprises a gold ion.
11. the formation method of base plate for packaging as claimed in claim 8, wherein the formation step of this first electroplating region and this second electroplating region comprises:
On this substrate, form a conductive layer; And
This conductive layer pattern is turned to this first electroplating region and this second electroplating region.
12. the formation method of base plate for packaging as claimed in claim 11, wherein the formation step of this first electroplated lead and this second electroplated lead comprises this conductive layer patternization to form this first electroplating region, this second electroplating region, this first electroplated lead simultaneously, to reach this second electroplated lead.
13. the formation method of base plate for packaging as claimed in claim 8, wherein this first electroplated lead comprises hole part, a sweep, a sharp-pointed part, a serrated portion, a bending part or aforesaid combination.
14. the formation method of base plate for packaging as claimed in claim 8, wherein the shared area of this first conductive pattern is greater than the shared area of this second conductive pattern.
15. the formation method of base plate for packaging as claimed in claim 8, wherein this first conductive pattern is a mould geat district, and this second conductive pattern is a pad area.
CN2010102491813A 2010-08-06 2010-08-06 Packaging substrate and formation method thereof Pending CN102376673A (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446625A (en) * 1993-11-10 1995-08-29 Motorola, Inc. Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface
CN1536631A (en) * 2003-04-09 2004-10-13 全懋精密科技股份有限公司 Electrically-connecting pad electroplated metal layer structrure of semiconductor package base plate and its making metod
CN2847794Y (en) * 2005-07-28 2006-12-13 威盛电子股份有限公司 Circuit board with electroplating conductor
US20070278701A1 (en) * 2006-06-02 2007-12-06 Siliconware Precision Industries Co., Ltd. Semiconductor package and method for fabricating the same
CN101330799A (en) * 2007-06-22 2008-12-24 健鼎科技股份有限公司 Non-conductor electroplating method for independent soldering pad
TW200913092A (en) * 2007-09-12 2009-03-16 Powertech Technology Inc Semiconductor packaging process enabling completely performing non-stick test of wire-bonding on a substrate strip
CN101610638A (en) * 2008-06-16 2009-12-23 欣兴电子股份有限公司 Line motherboard
CN102005427A (en) * 2009-08-31 2011-04-06 三星电机株式会社 Printed circuit board strip and panel

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446625A (en) * 1993-11-10 1995-08-29 Motorola, Inc. Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface
CN1536631A (en) * 2003-04-09 2004-10-13 全懋精密科技股份有限公司 Electrically-connecting pad electroplated metal layer structrure of semiconductor package base plate and its making metod
CN2847794Y (en) * 2005-07-28 2006-12-13 威盛电子股份有限公司 Circuit board with electroplating conductor
US20070278701A1 (en) * 2006-06-02 2007-12-06 Siliconware Precision Industries Co., Ltd. Semiconductor package and method for fabricating the same
CN101330799A (en) * 2007-06-22 2008-12-24 健鼎科技股份有限公司 Non-conductor electroplating method for independent soldering pad
TW200913092A (en) * 2007-09-12 2009-03-16 Powertech Technology Inc Semiconductor packaging process enabling completely performing non-stick test of wire-bonding on a substrate strip
CN101610638A (en) * 2008-06-16 2009-12-23 欣兴电子股份有限公司 Line motherboard
CN102005427A (en) * 2009-08-31 2011-04-06 三星电机株式会社 Printed circuit board strip and panel

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Application publication date: 20120314