CN102394617B - Dead zone enhanced protection high speed complementation switch drive circuit - Google Patents
Dead zone enhanced protection high speed complementation switch drive circuit Download PDFInfo
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- CN102394617B CN102394617B CN2011103076598A CN201110307659A CN102394617B CN 102394617 B CN102394617 B CN 102394617B CN 2011103076598 A CN2011103076598 A CN 2011103076598A CN 201110307659 A CN201110307659 A CN 201110307659A CN 102394617 B CN102394617 B CN 102394617B
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Abstract
The invention relates to the integrated circuit signal driving technology field, concretely relating to a high speed complementation switch signal drive circuit with a dead zone enhanced protection structure. The high speed complementation switch signal drive circuit is obtained through connection of a complementation signal generation circuit and a dead zone enhanced protection circuit, continuity of current output by a complementation switch can be ensured, and since an overturn speed of a single tube is higher than a speed of state simultaneous overturn of N-P two Mos tubes, the high speed complementation switch signal drive circuit has a higher work speed.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of high speed complementation switching signal drive circuit.
Technical background
Along with the making rapid progress of CMOS technology, the processing speed of microprocessor, multimedia, virtual reality, light transmission connection, intelligent router and network technology continued to promote in the last few years, and impelled that plate level processing speed reaches GHz between the chip.What traditional plate level high-speed interface circuit adopted is large-scale parallel processing structure, and the shortcoming of this kind structure is that the encapsulation of IC is too high with power consumption, complexity and the cost of the pcb board of correspondence.For the battery powered mobile portable treatment system of various employings, low-power consumption is the most important condition; And for other system, low-power consumption can reduce to encapsulate and the cost of the cooling device that dispels the heat.Therefore, the chip processing speed that constantly advances presses for a kind of chip chamber transmission technology of high-speed low-power-consumption.
Low Voltage Differential Signal (LVDS) is exactly a kind of for the high-speed low-power-consumption interface transmission technology that substitutes traditional high speed transmission technology.The core of LVDS technology is to adopt extremely low voltage swing high speed differential transmission data, can realize point-to-point or a bit to the connection of multiple spot, has advantages such as low-power consumption, low noise, low cost simultaneously.Because adopt the fully differential structure, the LVDS technology improves greatly for signal sending end and the receiving terminal immunocompetence that do not match over the ground; Simultaneously, because the electric current of signal pair is closely-coupled electric current loop, so fringing field is tending towards eliminating, thereby has reduced electromagnetic interference.Because once the research focus that proposes just to become the high speed data transfer field, having had in a large number in recent ten years, the plurality of advantages of LVDS technology, LVDS standard report based on the design of different application occasion.
Fig. 1 is LVDS transmission technology principle schematic.Fully differential load Z among the figure
LBe in order to improve the impedance matching of transmission path.LVDS is a kind of electric current loop signal transmission technology, the direction of its electric current loop (clockwise or inhour) decision logic level (high state or low state).Electric current on online right 1 line about excitation 3.5mA, and return by right 1 line in addition of line.At terminating resistor R
T-RProduce approximately ± 350mV voltage (± 3.5mA * 100 Ω=± 350mV).Receiver measures the polarity of this pressure drop, positive voltage counterlogic high state, the low state of negative voltage counterlogic.Constant relatively, the little output current of LVDS has reduced power supply/ground noise.Because the electric current of signal pair is closely-coupled electric current loop, so fringing field is tending towards eliminating, thereby has reduced electromagnetic interference.Simultaneously, adopt differential mode to transmit data, have the common-mode noise stronger than single-ended transmission mode to suppress ability.Because a pair of differential lines is opposite to the last sense of current, when the noise of common mode mode misfortune was incorporated into line when last, cancel out each other in the effect that the receiver input produces, thereby very little to the influence of signal.There are non-ideal characteristics such as encapsulation parasitic capacitance, signal cross-talk in the application scenario that reaches Gbps for speed owing to receiving terminal, these imperfect meetings are reflected and are superimposed upon and transmit on the signal during high-speed data, therefore add a terminal resistance R at launch terminal usually
T-T, to suppress the reflection of interference waveform.
The basic principle of LVDS transtation mission circuit as shown in Figure 2.The basic principle of transtation mission circuit be a full-bridge type drive circuit shown in Fig. 2 (a), the constant-current source I of 3.5mA
bUnder the control of input signal D and Dn, flow through the sense of current transmission logical signal of terminal resistance by change.When the D switch is effective, I
bFlow through Von through terminal resistance to the right from Vop; When the Dn switch is effective, I
bFlow through Vop through terminal resistance left from Von.Fig. 2 (b) is a kind of implementation of this full-bridge type drive circuit, M1 is the identical PMOS pipe of dimension process with M3, M2 is the identical NMOS pipe of dimension process with M4, D and Dn are the anti-phase signals each other of being derived by same Vin input cmos signal, output Vop and Von externally connect the terminal resistance that resistance is 100 Ω, constitute the loop.When Dn is high level, when D is low level, M1 and the conducting of M4 pipe, M2 and M3 pipe end, and electric current flows to Von from Vop, and produces the pressure drop of 350mV; Otherwise, when Dn is low level, when D is high level, M2 and the conducting of M3 pipe, M1 and M4 pipe end, and electric current flows to Vop from Von, and produces the pressure drop of 350mV.So just a cmos signal has been converted to the LVDS signal.
Fig. 3 is the structure principle chart of practical a kind of high speed LVDS transtation mission circuit, and circuit mainly is made up of full-bridge type drive circuit, common-mode feedback control circuit and 3 modules of switch driving circuit.M1-M6 has formed the full-bridge type drive circuit, so that the constantly electric current of the 3.5mA of switching of output current direction to be provided; Driving switch pipe (M1-M4) size of full-bridge type drive circuit is generally all bigger, and needs the driving signal of a pair of complementation, and input signal is the digital logic signal without any driving force, so we need a switch driving circuit; Because the common mode electrical level of LVDS output signal must be stabilized in about 1.2V, therefore a common mode feedback circuit need be set stablizes the common mode output voltage.
As can be seen, the output signal transmission speed of circuit depends on the switch speed of the 3.5mA electric current that the full-bridge type drive circuit of M1-M6 composition provides from the structure principle chart of high speed LVDS transtation mission circuit shown in Figure 3.Therefore the actuating speed of complementary switch drive circuit directly determines the data transmission capabilities of LVDS transtation mission circuit.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of dead band to strengthen protection high speed complementation switch driving circuit, can significantly improve the data transmission capabilities of LVDS transtation mission circuit.
According to technical scheme provided by the invention, described dead band strengthens protection high speed complementation switch driving circuit and comprises that mutual supplementary signal generation circuit and dead band strengthen protective circuit; It is the digital logic signal that does not have driving force that the dead band strengthens protection high speed complementation switch driving circuit input signal, converts complementary driving signal to through described mutual supplementary signal generation circuit; Enhancing protective circuit in dead band is converted to the switching drive signal with Dead Time protection with the driving signal of described complementation then;
Described mutual supplementary signal generation circuit is connected and composed by 9 inverters, circuit connecting relation is: the first inverter input is connected to the dead band and strengthens protection high speed complementation switch driving circuit input signal, and first inverter output is connected to the input of second inverter; Second inverter output is connected to the input of the 3rd inverter and the 5th inverter and the output of the 4th inverter; The 3rd inverter output is connected to the inversion signal output of mutual supplementary signal generation circuit, is also connected to the input of the 7th inverter and the output of hex inverter simultaneously; The 8th inverter input is connected to the dead band and strengthens protection high speed complementation switch driving circuit input signal, and the 8th inverter output is connected to input and the output of the 5th inverter and the input of the 4th inverter of the 9th inverter; The 9th inverter output is connected to the in-phase signal output of mutual supplementary signal generation circuit, is also connected to the output of the 7th inverter and the input of hex inverter simultaneously;
Described dead band strengthens protective circuit and comprises first nmos pass transistor, the 2nd PMOS transistor, the 3rd nmos pass transistor, the 4th PMOS transistor, the 5th nmos pass transistor, the 6th PMOS transistor, the 7th nmos pass transistor and the 8th PMOS transistor, circuit connecting relation is: the grid of first nmos pass transistor is connected to the inversion signal output of mutual supplementary signal generation circuit, the first nmos pass transistor source electrode is connected to ground, and first nmos transistor drain is connected to source electrode and the 4th PMOS transistor drain of the 3rd nmos pass transistor; The transistorized grid of the 2nd PMOS is connected to the inversion signal output of mutual supplementary signal generation circuit, and the 2nd PMOS transistor source is connected to power supply, and the 2nd PMOS transistor drain is connected to drain electrode and the transistorized source electrode of the 4th PMOS of the 3rd nmos pass transistor; The 3rd nmos pass transistor grid and the 4th PMOS transistor gate also are connected to the inversion signal output of mutual supplementary signal generation circuit; The 5th nmos pass transistor grid is connected to the in-phase signal output of mutual supplementary signal generation circuit, and the 5th nmos pass transistor source electrode is connected to ground, and the 5th nmos transistor drain is connected to source electrode and the 8th PMOS transistor drain of the 7th nmos pass transistor; The transistorized grid of the 6th PMOS is connected to the in-phase signal output of mutual supplementary signal generation circuit, and the 6th PMOS transistor source is connected to power supply, and the 6th PMOS transistor drain is connected to drain electrode and the transistorized source electrode of the 8th PMOS of the 7th nmos pass transistor; The 7th nmos pass transistor grid and the 8th PMOS transistor gate also are connected to the in-phase signal output D of mutual supplementary signal generation circuit.
Advantage of the present invention is: this high speed complementation switching signal drive circuit strengthens protective circuit by mutual supplementary signal generation circuit and dead band and is connected and obtains; can guarantee the continuity of complementary switch output current; simultaneously because the reversal rate of single tube also overturns fast than the state of two metal-oxide-semiconductors of N-P simultaneously; improved the operating rate of circuit, be very suitable for being applied in the complementary output drive circuit.
Description of drawings
Fig. 1 is LVDS transmission basic principle;
Fig. 2 (a) is LVDS signal sending circuit basic principle figure;
Fig. 2 (b) is a kind of realization circuit theory diagrams of Fig. 2 (a).
Fig. 3 is a kind of LVDS signal sending circuit structure principle chart of practicality;
Fig. 4 strengthens protection high speed complementation switch driving circuit schematic diagram for dead band of the present invention;
Fig. 5 strengthens protection high speed complementation switch driving circuit simulation curve for dead band of the present invention.
Embodiment
Below in conjunction with accompanying drawing and example the present invention is described in more detail.
The switching drive signal of the full-bridge type drive circuit of LVDS transtation mission circuit is anti-phase D and Dn signal each other among Fig. 2.Suppose that D overturns to 1 by 0, because there is certain rise time in energizing signal, at voltage M1 and M2 conducting " dead band " simultaneously situation in a period of time can appear like this during for intermediate level, the operating state of M1 and M2 can change simultaneously, can can fluctuate the direction reversal rate of the output current signal that slows down by output current like this.Change the D1 that certain time-delay is arranged each other and the D2 signal with certain " Dead Time enhancing " into by the D signal that will be added on M1 and the M2, suppose that D1 still is 0 when the D2 signal begins turning to 1 by 0, when the stable working state of M2 pipe, the D1 signal just begins turning to 1 by 0.Work as the M2 pipe like this and be changed to saturation condition by cut-off state, the operating state of MI pipe does not change, and after the operating state conducting of M2 pipe is stable, the operating state of MI pipe just changes, so just can guarantee the continuity of output current, the reversal rate of single tube also overturns simultaneously and will therefore, also improve the operating rate of circuit soon than the state of two metal-oxide-semiconductors of N-P simultaneously.
Fig. 4 is the schematic diagram of the switch driving circuit in the designed transtation mission circuit of the present invention.Switch driving circuit strengthens protective circuit 2 by mutual supplementary signal generation circuit 1 and dead band and is connected and obtains.Input signal Vin is the digital logic signal that does not have driving force, switch driving circuit at first convert supplied with digital signal Vin to complementary drive signal D and Dn through mutual supplementary signal generation circuit 1; Enhancing protective circuit 2 in dead band is converted to the switching drive signal D1-D4 with certain Dead Time protection with complementary drive signal D and Dn then.Obtain the regular hour delay and adopt traditional digital circuit to be easy to realize, but for Gbps circuit at a high speed, the time-delay that two reversers of digital circuit produce after connecting will be excessive, therefore need the continuous mode of employing simulation to realize this time-delay.
Described mutual supplementary signal generation circuit 1 is connected and composed by 9 inverter a, b, c, d, e, f, g, h, i.The first inverter a input is connected to input signal Vin, and the first inverter a output is connected to the input of the second inverter b; The second inverter b output is connected to the input of the 3rd inverter c and the 5th inverter e and the output of the 4th inverter d; The 3rd inverter c output is connected to the inversion signal output Dn of mutual supplementary signal generation circuit 1, is also connected to the input of the 7th inverter g and the output of hex inverter f simultaneously; The 8th inverter h input is connected to input signal Vin, and the 8th inverter h output is connected to input and the output of the 5th inverter e and the input of the 4th inverter d of the 9th inverter i; The 9th inverter i output is connected to the in-phase signal output D of mutual supplementary signal generation circuit 1, is also connected to the output of the 7th inverter g and the input of hex inverter f simultaneously.
Described dead band strengthens protective circuit 2 and comprises the first nmos pass transistor M1A, the 2nd PMOS transistor M1B, the 3rd nmos pass transistor M1C, the 4th PMOS transistor M1D, the 5th nmos pass transistor M2A, the 6th PMOS transistor M2B, the 7th nmos pass transistor M2C and the 8th PMOS transistor M2D.The grid of the first nmos pass transistor M1A is connected to the inversion signal output Dn of mutual supplementary signal generation circuit 1, and source electrode is connected to ground GND, and drain electrode is connected to the drain electrode of source electrode and the 4th PMOS transistor M1D of the 3rd nmos pass transistor M1C; The grid of the 2nd PMOS transistor M1B is connected to the inversion signal output Dn of mutual supplementary signal generation circuit 1, and source electrode is connected to power vd D, and drain electrode is connected to the drain electrode of the 3rd nmos pass transistor M1C and the source electrode of the 4th PMOS transistor M1D; The grid of the 3rd nmos pass transistor M1C and the 4th PMOS transistor M1D also is connected to the inversion signal output Dn of mutual supplementary signal generation circuit 1.The grid of the 5th nmos pass transistor M2A is connected to the in-phase signal output D of mutual supplementary signal generation circuit 1, and source electrode is connected to ground GND, and drain electrode is connected to the drain electrode of source electrode and the 8th PMOS transistor M2D of the 7th nmos pass transistor M2C; The grid of the 6th PMOS transistor M2B is connected to the in-phase signal output D of mutual supplementary signal generation circuit 1, and source electrode is connected to power vd D, and drain electrode is connected to the drain electrode of the 7th nmos pass transistor M2C and the source electrode of the 8th PMOS transistor M2D; The grid of the 7th nmos pass transistor M2C and the 8th PMOS transistor M2D also is connected to the in-phase signal output D of mutual supplementary signal generation circuit 1.
The work of novel " dead band strengthens protection " circuit can be described below in the invention described above: overturn to low by height for the D signal, when the D signal level is begun to descend V by VDD
DWhen dropping to VDD-Vth2B, M2B begins conducting, and the D2 point voltage begins to rise, and D1 voltage still is 0 constant; V
DWhen continuing to drop to VDD-Vth2D-Vds2B, the M2D pipe just begins conducting, and the D1 point voltage just begins to rise, and the D2 point voltage continues to rise; V
DWhen continuing to drop to Vth2C+Vds2A, the M2C pipe ends, and it is constant that the D2 point voltage almost arrives VDD, and the D1 point voltage continues to rise; Last V
DContinue to drop to Vth2A when following, the M2A pipe ends, and it is constant that the D2-D1 point voltage all reaches VDD, has so just formed the rising edge time-delay of D1 with respect to D2.
Overturn from low to high for the D signal, working condition is complementary fully opposite.When the D signal level begins to rise V by 0
DWhen rising to Vth2A, M2A begins conducting, and the D1 point voltage begins to descend, and D2 voltage still is that VDD is constant; V
DWhen continuing to rise to Vth2C+Vds2A, the M2C pipe just begins conducting, and the D2 point voltage just begins to descend, and the D1 point voltage continues to descend; V
DWhen continuing to rise to VDD-Vth2D-Vds2B, the M2D pipe ends, and it is 0 constant that the D1 point voltage almost arrives, and the D2 point voltage continues to descend; Last V
DContinue to rise to VDD-Vth2B when above, the M2B pipe ends, and it is 0 constant that the D2-D1 point voltage all reaches, and so just formed the trailing edge time-delay of D2 with respect to D1.
Fig. 5 strengthens LVDS output drive signal that the switch driving circuit of defencive function obtains in the emulation comparing result of the output waveform of traditional drive circuit for the dead band that has after the employed improvement of this paper.Though the circuit output waveform after improving as can be seen has certain spike, waveform slope obviously increases, so speed obviously promotes.
Claims (1)
1. the dead band strengthens protection high speed complementation switch driving circuit, and it is characterized in that comprising: mutual supplementary signal generation circuit and dead band strengthen protective circuit; The dead band strengthens protection high speed complementation switch driving circuit input signal (Vin) for there not being the digital logic signal of driving force, converts complementary driving signal to through described mutual supplementary signal generation circuit; Enhancing protective circuit in dead band is converted to the switching drive signal with Dead Time protection with the driving signal of described complementation then;
Described mutual supplementary signal generation circuit is connected and composed by 9 inverters, circuit connecting relation is: first inverter (a) input is connected to the dead band and strengthens protection high speed complementation switch driving circuit input signal (Vin), and first inverter (a) output is connected to the input of second inverter (b); Second inverter (b) output is connected to the input of the 3rd inverter (c) and the 5th inverter (e) and the output of the 4th inverter (d); The 3rd inverter (c) output is connected to the inversion signal output (Dn) of mutual supplementary signal generation circuit, is also connected to the input of the 7th inverter (g) and the output of hex inverter (f) simultaneously; The 8th inverter (h) input is connected to the dead band and strengthens protection high speed complementation switch driving circuit input signal (Vin), and the 8th inverter (h) output is connected to input and the output of the 5th inverter (e) and the input of the 4th inverter (d) of the 9th inverter (i); The 9th inverter (i) output is connected to the in-phase signal output (D) of mutual supplementary signal generation circuit, is also connected to the output of the 7th inverter (g) and the input of hex inverter (f) simultaneously;
Described dead band strengthens protective circuit and comprises first nmos pass transistor (M1A), the 2nd PMOS transistor (M1B), the 3rd nmos pass transistor (M1C), the 4th PMOS transistor (M1D), the 5th nmos pass transistor (M2A), the 6th PMOS transistor (M2B), the 7th nmos pass transistor (M2C) and the 8th PMOS transistor (M2D), circuit connecting relation is: the grid of first nmos pass transistor (M1A) is connected to the inversion signal output (Dn) of mutual supplementary signal generation circuit, first nmos pass transistor (M1A) source electrode is connected to ground, and first nmos pass transistor (M1A) drain electrode is connected to the drain electrode of source electrode and the 4th PMOS transistor (M1D) of the 3rd nmos pass transistor (M1C); The grid of the 2nd PMOS transistor (M1B) is connected to the inversion signal output (Dn) of mutual supplementary signal generation circuit, the 2nd PMOS transistor (M1B) source electrode is connected to power supply, and the drain electrode of the 2nd PMOS transistor (M1B) is connected to the drain electrode of the 3rd nmos pass transistor (M1C) and the source electrode of the 4th PMOS transistor (M1D); The 3rd nmos pass transistor (M1C) grid and the 4th PMOS transistor (M1D) grid also are connected to the inversion signal output (Dn) of mutual supplementary signal generation circuit; The 5th nmos pass transistor (M2A) grid is connected to the in-phase signal output (D) of mutual supplementary signal generation circuit, the 5th nmos pass transistor (M2A) source electrode is connected to ground, and the 5th nmos pass transistor (M2A) drain electrode is connected to the drain electrode of source electrode and the 8th PMOS transistor (M2D) of the 7th nmos pass transistor (M2C); The grid of the 6th PMOS transistor (M2B) is connected to the in-phase signal output (D) of mutual supplementary signal generation circuit, the 6th PMOS transistor (M2B) source electrode is connected to power supply, and the drain electrode of the 6th PMOS transistor (M2B) is connected to the drain electrode of the 7th nmos pass transistor (M2C) and the source electrode of the 8th PMOS transistor (M2D); The 7th nmos pass transistor (M2C) grid and the 8th PMOS transistor (M2D) grid also are connected to the in-phase signal output (D) of mutual supplementary signal generation circuit.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760620A (en) * | 1996-04-22 | 1998-06-02 | Quantum Effect Design, Inc. | CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks |
| CN1929305A (en) * | 2005-09-05 | 2007-03-14 | 中兴通讯股份有限公司 | Low-voltage differential signal driver circuit |
| CN201365236Y (en) * | 2008-10-27 | 2009-12-16 | 苏州力宝电子有限公司 | Complementary commutation drive circuit |
| US7724026B1 (en) * | 2008-11-12 | 2010-05-25 | Xilinx, Inc. | Single-ended input-output block with reduced leakage current |
| CN202261207U (en) * | 2011-10-11 | 2012-05-30 | 中国电子科技集团公司第五十八研究所 | High-speed complementary switch drive circuit with dead zone enhanced protection |
-
2011
- 2011-10-11 CN CN2011103076598A patent/CN102394617B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760620A (en) * | 1996-04-22 | 1998-06-02 | Quantum Effect Design, Inc. | CMOS limited-voltage-swing clock driver for reduced power driving high-frequency clocks |
| CN1929305A (en) * | 2005-09-05 | 2007-03-14 | 中兴通讯股份有限公司 | Low-voltage differential signal driver circuit |
| CN201365236Y (en) * | 2008-10-27 | 2009-12-16 | 苏州力宝电子有限公司 | Complementary commutation drive circuit |
| US7724026B1 (en) * | 2008-11-12 | 2010-05-25 | Xilinx, Inc. | Single-ended input-output block with reduced leakage current |
| CN202261207U (en) * | 2011-10-11 | 2012-05-30 | 中国电子科技集团公司第五十八研究所 | High-speed complementary switch drive circuit with dead zone enhanced protection |
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