CN102403018A - Matching detection method and circuit of content addressable memory cell - Google Patents
Matching detection method and circuit of content addressable memory cell Download PDFInfo
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- CN102403018A CN102403018A CN2011103479283A CN201110347928A CN102403018A CN 102403018 A CN102403018 A CN 102403018A CN 2011103479283 A CN2011103479283 A CN 2011103479283A CN 201110347928 A CN201110347928 A CN 201110347928A CN 102403018 A CN102403018 A CN 102403018A
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Abstract
The invention relates to a matching detection method and circuit of a content addressable memory cell. The matching detection method comprises the steps of: carrying out charging or charging control on a charge circuit of a first matching signal wire and a feedback control circuit of a second matching signal wire; when contents of an NOR memory cell are matched and a voltage difference exists between the matching signal wires, outputting a matching signal; and when the contents of the NOR memory cell are mismatched and no voltage difference exists between the matching signal wires, not outputting the matching signal. The matching detection method is simple and reliable, and has the advantages of reduction in additional offset voltage and offset current and further reduction in power consumption in comparison with the traditional matching detection method of the memory cell.
Description
Technical field
The present invention relates to Content Addressable Memory, relate in particular to Content Addressable Memory storage unit matching detection Method and circuits.
Background technology
(Content-Addressable Memory CAM) is a kind of content adressable memory that is used for the certain high-speed search application to Content Addressable Memory.Whether its principle of work is: when the user provided data, CAM can travel through whole storage space, search for these data and be present in the storer, if exist, CAM can return the address that one or more hiting datas exist.CAM can search for whole storer as a kind of special memory in the single computing.Therefore, in search application, CAM is fast more a lot of than normal memory.The quick search attribute of CAM makes CAM be specially adapted in the application such as the network equipment, central processing unit and the hard encoding and decoding of video.
The memory cell structure of traditional Content Addressable Memory is divided into and non-type storage unit and or/no type storage unit according to the similarities and differences of match-type.Fig. 1 be traditional 9T (Transistor, transistor) structure with non-type storage unit.With non-type storage unit matched signal line (Match Line) through being interconnected to form whole matched line with the storage unit of closing on.The source electrode that is transistor T 1 is connected with the drain electrode of previous storage unit, and the drain electrode of T1 is connected with the source electrode of back one storage unit.As long as with the structures shape of non-type storage unit the content of being searched for have a place and memory contents not to match, then whole piece matched signal line will can not discharge.With the shortcoming of non-type storage unit be, if content is when all mating, the matched signal line discharges through the transistor T 1 of cascade, and that the velocity of discharge will be very more for a long time is slow when memory contents.
Fig. 2 is the or/no type storage unit, forms whole matched signal line through connecting the drain electrode of opening a way in the different storage unit.Adopt the mode of parallel connection, avoid the cascade with non-type storage unit internal transistor, make the or/no type storage unit be highly suitable in the middle of the high-speed structures.If the content in a certain position in the search content and the storage unit does not match, just the matched signal line of or/no type storage unit begins discharge.And if only if when seeking content match, and the matched signal line just can not discharge.The velocity of discharge of the storage unit of or/no type is very fast, but because frequent discharge and charging make that the power consumption of Content Addressable Memory is very big.
In order to reduce the power problems of or/no type storage unit matched signal line, multiple detection method has appearred at present.Fig. 3 is that the electric current contest detects schematic diagram.As shown in Figure 3, need do contrast signal by one group of virtual matched signal line (Dummy ML) based on the detection method of electric current contest.This DML is in the state of coupling all the time.This method is when carrying out the detection of matched signal line states, and at first matched signal line reset signal (MLrst) is effective, and (ML) is initialised to low level with the matched signal line; Match line enable signal (MLen) is uprised by low then, opens the charge path of matched signal line.Be charged to the threshold values of sense amplifier (SA) as DML after, produce matched signal line cut-off signals (MLoff), this cut-off signals will turn-off the charge path of all matched signal lines.Have only the matched signal line of coupling in this duration of charging, just can make sense amplifier (SA) produce output signal (MLout), in case there is unmatched matched signal line can not charge above the threshold values of sense amplifier (SA).This method has reduced the power consumption of whole matching signal wire through the charging amplitude of oscillation that reduces the matched signal line.
Fig. 4 saves the current detecting schematic diagram.The similar electric current contest of this scheme detection method; Utilize the duration of charging of the threshold voltage control matched signal line of virtual matched signal line (DML) and sense amplifier (SA) equally; Reduce overall power; The difference of this scheme is through the current savings technology charging current that will reduce matched line under the situation of losing is arranged at the matched signal line, thereby further reduces overall power.
Fig. 5 is that the positive feedback formula detects schematic diagram.The matched line detection method of the similar saving electric current of this scheme is utilized positive feedback to be reduced in to lose under the matching status the charging current of matched signal line, reduces overall power.
Can know that by above-mentioned traditional 3 kinds of schemes initialization is still wasted very big power consumption to the discharge of matched signal line; Adopt current savings technology and positive feedback technique can reduce under content does not match state charging current to the matched signal line, but need extra bias voltage and on the control branch road the extra quiescent current of consumption be cost.Therefore, how further the power consumption of reduction or non-storage unit matched signal line is that major issue to be solved is arranged at present.
Summary of the invention
The invention provides a kind of Content Addressable Memory storage unit matching detection Method and circuits that can overcome the above problems.
In first aspect; The invention provides a kind of Content Addressable Memory storage unit matching detection method; The parallel connection of wherein some or non-storage unit forms the first matched signal line (MLA) and the second matched signal line (MLB), and said method comprises: the charging circuit that the said first matched signal line is charged, the feedback control circuit that is connected said second matched line; When said some or non-memory cell content is all mated, exist voltage difference to be enough to cause exporting matched signal between said first matched signal line and the said second matched signal line; When at least one content does not match in the said some or non-storage unit; The said first matched signal line charges to the said second matched signal line through the unmatched or non-storage unit of said content; And impel said feedback control circuit to turn-off said charging circuit, the voltage difference between said thus first matched signal line and the said second matched signal line is not enough to export matched signal.
In second aspect; The invention provides a kind of Content Addressable Memory storage unit match detection circuit; Comprise pre-charge circuit, charging circuit, feedback control circuit, equalizing circuit and some or non-storage unit; Said pre-charge circuit is connected with said charging circuit and feedback control circuit, forms the first matched signal line and the second matched signal line by said some or non-storage unit parallel connection, and said charging circuit is connected with the said first matched signal line; Said feedback control circuit is connected with the said second matched signal line, and said equalizing circuit is connected between said first matched signal line and the said second matched signal line.
In the third aspect; The invention provides a kind of complementary Content Addressable Memory storage unit matching detection method; Wherein some or non-storage unit parallel connection forms the first matched signal line (MLA) and the second matched signal line (MLB); Said method comprises: the feedback control circuit, the discharge circuit to discharging at the second matched signal line that are connected the said first matched signal line; When said some or non-memory cell content is all mated, exist voltage difference to be enough to cause exporting matched signal between said first matched signal line and the said second matched signal line; When at least one content does not match in the said some or non-storage unit; Unmatched or the non-storage unit of said content is through said discharge circuit discharge; And impel said feedback control circuit to turn-off said discharge circuit, the voltage difference between said thus first matched signal line and the said second matched signal line is not enough to export matched signal.
In fourth aspect; The invention provides a kind of complementary Content Addressable Memory storage unit match detection circuit; Comprise pre-arcing circuit, discharge circuit, feedback control circuit, equalizing circuit and some or non-storage unit; Said pre-arcing circuit is connected with said discharge circuit and feedback control circuit, and by the first matched signal line and the second matched signal line that said some or non-storage unit parallel connection forms, said feedback control circuit is connected with the said first matched signal line; Said discharge circuit is connected with the said second matched signal line, and said equalizing circuit is connected between said first matched signal line and the said second matched signal line.
The present invention utilizes the charging method of dynamic control matched line to reduce current drain, according to the voltage differential signal testing result of coupling wire size line generation.The present invention is simple and reliable; Compare with traditional matched signal line detecting method, reduce current drain, reduce extra bias voltage and bias current.
Description of drawings
Fig. 1 is traditional structure and non-type storage unit;
Fig. 2 is the or/no type storage unit;
Fig. 3 is that the electric current contest detects schematic diagram;
Fig. 4 saves the current detecting schematic diagram;
Fig. 5 is that the positive feedback formula detects schematic diagram;
Fig. 6 is or non-storage unit match detection circuit block diagram;
Fig. 7 is or non-storage unit match detection circuit schematic diagram;
Fig. 8 is or non-storage unit match detection circuit sequential control figure;
Fig. 9 is complementary or non-storage unit match detection circuit block diagram;
Figure 10 is complementary or non-storage unit match detection circuit schematic diagram;
Figure 11 is complementary or non-storage unit match detection circuit sequential control figure.
Embodiment
Below with reference to accompanying drawings specific embodiment of the present invention is carried out more detailed explanation, Fig. 6 is the embodiment of the invention or non-storage unit match detection circuit block diagram, and Fig. 7 is or non-storage unit match detection circuit schematic diagram.As shown in Figure 6; Or non-storage unit match detection circuit comprises: pre-charge circuit, charging circuit, feedback control circuit, equalizing circuit or non-storage unit, sense amplifier (SA), power supply and ground; Wherein, Or the quantity of non-storage unit greater than 1, the first matched signal line MLA and the second matched line signal MLB by several or non-storage unit be formed in parallel (hereinafter to be referred as matched signal line MLA and matched line signal MLB).
As shown in Figure 7, this circuit transistor N1, N2, N3, N4, N5 and or non-storage unit inside be nmos pass transistor; Transistor P1 and P2 are the PMOS pipe.Pre-charge circuit comprises a P transistor npn npn P1.Charging circuit comprises the 2nd P transistor npn npn P2 and the 4th N transistor npn npn N4, and its function is to control the charging to matched signal line MLA according to the change dynamics ground of feedback control circuit.Feedback control circuit comprises the 2nd N transistor npn npn N2, the 3rd N transistor npn npn N3 and a N transistor npn npn N1; Wherein, The 2nd N transistor npn npn N2 and the 3rd N transistor npn npn N3 constitute current mirror; The function of feedback control circuit is the variation FEEDBACK CONTROL charging circuit according to matched signal line MLB voltage, also realizes the function to matched line MLB discharge simultaneously.Equalizing circuit the 5th N type comprises transistor N5 in the present embodiment, and its function is to matched signal line MLA and matched signal line MLB initialization.
In the pre-charge circuit in the source electrode of a P transistor npn npn P1 and the charging circuit source electrode of the 2nd P transistor npn npn P2 be connected on the power supply; And the grid of a P transistor npn npn P1 is by precharging signal PRE (hereinafter to be referred as the PRE signal) control, and its drain electrode is connected in the A point with the drain electrode of the 2nd N transistor npn npn N2; The grid of the 2nd P transistor npn npn P2 is by non-assessing signal NEVAL (hereinafter to be referred as the NEVAL signal) control, and its drain electrode links to each other with the drain electrode of the 4th N transistor npn npn N4 in the charging circuit, and the 2nd N transistor npn npn N2 and the 4th N transistor npn npn N4 form series connection; The grid of the 4th N transistor npn npn N4 is connected in the A point; Matched signal line MLA is connected between the drain electrode of the 5th N transistor npn npn N5 in source electrode and the equalizing circuit of the 4th N transistor npn npn N4; The grid of the 3rd N transistor npn npn N 3 all is connected on the matched signal line MLB with drain electrode in the feedback control circuit; Matched signal line MLB one end links to each other with the grid of the 2nd N transistor npn npn N2 and the 3rd N transistor npn npn N3, and the other end links to each other with the source electrode of the 5th N transistor npn npn N5, and the grid of the 5th N transistor npn npn N5 is controlled by reset signal RST (hereinafter to be referred as the RET signal); The 2nd N transistor npn npn N2 links to each other with the 3rd N transistor npn npn N3 grid, and the two transistor source electrode links to each other as the output branch road of current mirror; The drain electrode of a N transistor npn npn N1 is connected with the source electrode of the 2nd N transistor npn npn N2 and the 3rd N transistor npn npn N3 in the feedback control circuit, and its grid is controlled by assessing signal EVAL (hereinafter to be referred as the EVAL signal); The positive and negative input end of sense amplifier is connected on matched signal line MLA and the matched signal line MLB, and the output terminal of sense amplifier is matched signal line output signal MLSO (hereinafter to be referred as the MLSO signal).
Below in conjunction with Fig. 8 the course of work of the testing circuit of Fig. 7 is done specific descriptions.Fig. 8 is or non-storage unit match detection circuit sequential control figure.
When comparing coupling first, as shown in Figure 8, system works under clock signal clk, and RST signal high level is effective, will be balanced to matched signal line MLA and matched signal line MLB.Balanced back matched signal line MLA and MLB are low level.The PRE signal is that low level is effective, a P transistor npn npn P1 conducting, and the A point at first is pre-charged to supply voltage.The EVAL signal is a low level, and the NEval signal is a high level, and making the 2nd a P transistor npn npn P2 and a N transistor npn npn N1 is off state.
When the saltus step of EVAL signal was high level, the NEval signal was a low level, and the 2nd a P transistor npn npn P2 and a N transistor npn npn N1 are conducting state.Because node A at first is pre-charged to power supply, the 4th N transistor npn npn N4 is a conducting state this moment, and the 2nd P transistor npn npn P2 will charge to matched line MLA through the 4th N transistor npn npn N4.If this moment or non-memory cell content do not match, then the matched signal line does not match, matched signal line MLB also will through or the inner discharge path charging in non-unit, the rising of matched signal line MLB voltage.After the voltage of matched signal line MLB surpasses the threshold values of the 3rd N transistor npn npn N3, the 3rd N transistor npn npn N3 and the 2nd N transistor npn npn N2 conducting.Because the conducting of the 2nd N transistor npn npn N2, node A will descend the voltage of node A through the feedback control circuit discharge, cause the 4th N transistor npn npn N4 to be turned off.At this moment, feedback control circuit turn-offs charging circuit, and charging circuit no longer continues the charging to matched signal line MLA, and matched signal line MLA voltage is not continuing to rise whole charging process end.
Because or non-memory cell content do not match, and makes the voltage of matched signal line MLA and matched signal line MLB be consistent basically, thereby can not make sense amplifier SA upset, not produce and mate the MLSO signal.
If or non-memory cell content coupling; Then matched signal line MLB not can by or internal discharge path, non-unit charging; This moment, charging circuit continued the charging to matched signal line MLA, its voltage is risen, and the voltage of matched signal line MLB remained unchanged; Voltage difference between matched signal line MLA and the matched signal line MLB can make sense amplifier SA upset, produces coupling MLSO signal.
Need to prove that equalizing circuit also can realize its function by the transmission gate that the 6th N transistor npn npn and the 3rd P transistor npn npn are formed; The source electrode of the drain electrode of the 6th N transistor npn npn and the 3rd P transistor npn npn all is connected on the first matched signal line; The drain electrode of the source electrode of the 6th N transistor npn npn and the 3rd P transistor npn npn all is connected on the said second matched signal line; The grid of the 6th N transistor npn npn connects reset signal, and the grid of the 3rd P transistor npn npn connects non-reset signal.
Above-described is when comparing coupling first, and the method for charging and coupling comparative approach embody the characteristics of saving power consumption at follow-up charging method and coupling comparative approach.
Particularly, when comparing for the second time coupling, system works under clock signal, and RST signal high level is effective, will be balanced to matched signal line MLA and matched signal line MLB.Owing to carry out that the voltage of matched signal line two kinds of situation occur according to comparative result after the comparison match for the first time; During non-memory cell content coupling matched signal line voltage inconsistent with or non-memory cell content matched signal line voltage basically identical when not matching; Two matched signal line voltages are consistent basically, and the voltage of balanced back matched signal line MLB is the threshold voltage of a little higher than the 3rd N transistor npn npn N3.The PRE signal is that low level is effective, a P transistor npn npn P1 conducting, and node A is pre-charged to power supply.The EVAL signal is a low level, and the NEval signal is a high level, makes that the 2nd a P transistor npn npn P2 and a N transistor npn npn N1 are off state.
When the saltus step of EVAL signal is a high level, the NEval signal is a low level, and the 2nd a P transistor npn npn P2 and a N transistor npn npn N1 are conducting state.Because node A is pre-charged to power supply, the 4th N transistor npn npn N4 is a conducting state this moment, and the 2nd P transistor npn npn P2 will charge to matched signal line MLA through the 4th N transistor npn npn N4.Because the threshold voltage of a little higher than the 3rd N transistor npn npn N3 of voltage of balanced back matched signal line MLB is so matched signal line MLB discharges into the threshold voltage of the 3rd N transistor npn npn N3 through the 3rd N transistor npn npn N3; Because the 3rd N transistor npn npn N3 and the 2nd N transistor npn npn N2 conducting; Make node A through the feedback control circuit discharge, node A voltage descends, and causes the 4th N transistor npn npn N4 to be turned off; Feedback control circuit turn-offs charging circuit; Charging circuit is not continuing the charging to matched signal line MLA, and matched signal line MLA voltage is not continuing to rise the charging process end.
The process of so each charging only has pair time (Δ T) of node A discharge; During this period of time; If or non-memory cell content coupling, then matched signal line MLA can be recharged the Δ T time, makes voltage raise; And matched signal line MLB discharges into the threshold voltage of the 3rd N transistor npn npn N3 through feedback control circuit, the voltage official post sense amplifier SA upset that matched signal line MLA and matched signal line MLB produce; If or non-memory cell content does not match; Then constantly matched signal line MLA and matched signal line MLB are charged simultaneously at Δ T; And matched signal line MLA and matched signal line MLB are also simultaneously through the feedback control circuit discharge; Make the electric charge kept in balance, thereby can not make sense amplifier SA upset, do not produce coupling MLSO signal.
Because the Δ T time exists extremely short; So this scheme can be reduced in effectively or non-memory cell content does not match with match condition under current drain; Nor need extra bias voltage and bias current, and there is not quiescent dissipation, the initialization of this scheme simultaneously simply is convenient to realize with control.
It may be noted that the transistor that removes forming circuit schematic diagram shown in Figure 7, can also adopt the transistor of other type.
In complementary or non-storage unit match detection circuit; As shown in Figure 9; This complementary testing circuit comprises: pre-arcing circuit, discharge circuit, feedback control circuit, equalizing circuit or non-storage unit, sense amplifier SA, power supply and ground; Wherein, or the quantity of non-storage unit greater than 1, the first matched signal line MLA and the second matched signal line MLB by several or non-storage unit and connect and form (hereinafter to be referred as matched signal line MLA and matched line signal MLB).
Shown in figure 10, transistor P1 in the complementary or non-storage unit match detection circuit, P2, P3, P4, P5 and or non-storage unit inside be the PMOS transistor, transistor N1 and N2 are nmos pass transistor.The pre-arcing circuit comprises a N transistor npn npn N1; Comprise the 5th P transistor npn npn P5 and the 2nd N transistor npn npn N2 in the discharge circuit; Feedback control circuit comprises the 2nd P transistor npn npn P2, the 3rd P transistor npn npn P3 and the 4th P transistor npn npn P4; The 3rd P transistor npn npn P3 and the 4th P type P4 constitute current mirror; Its function is the conducting state control discharge circuit according to the 5th P transistor npn npn P5 in the discharge circuit, also realizes the charge function to matched line MLA simultaneously; Equalizing circuit comprises a P transistor npn npn P1 in the present embodiment, and its function is to matched signal line MLA and matched signal line MLB initialization.
The grid of the 2nd P transistor npn npn P2 is by the NEVAL signal controlling in the feedback control circuit; Its source electrode is connected with power supply; The 3rd P transistor npn npn P3 and the 4th P transistor npn npn P4 constitute current mirror; The 3rd P transistor npn npn P3 is connected with the 4th P transistor npn npn P4 source electrode and is connected with the drain electrode of the 2nd P transistor npn npn P2; The drain electrode of a N transistor npn npn N1 is connected node A in the drain electrode of the 3rd P transistor npn npn P3 and the pre-arcing circuit, and the grid of the 3rd P transistor npn npn P3 and the 4th P transistor npn npn P4 links to each other, and matched signal line MLA is connected on the grid of the 3rd P transistor npn npn P3 and the 4th P transistor npn npn P4; And as sense amplifier SA positive input terminal, the drain electrode of the 4th P transistor npn npn P4 is connected on the matched signal line MLA; Matched signal line MLB one end is connected on the source electrode of the 5th P transistor npn npn P5 in the discharge circuit, and the other end is as the negative input end of sense amplifier, and the sense amplifier output terminal is the MLSO signal; The grid of the 5th P transistor npn npn P5 is connected node A in the discharge circuit, and its drain electrode is connected with the drain electrode of the 2nd N transistor npn npn N2; The grid of the 2nd N transistor npn npn N2 is by the EVAL signal controlling; The grid of a N transistor npn npn N1 is by pre-arcing signal DIS (hereinafter to be referred as the DIS signal) control in the pre-arcing circuit, and the source electrode of a N transistor npn npn N1 all is connected ground in the source electrode of the 2nd N transistor npn npn N2 and the pre-arcing circuit; The grid of a P transistor npn npn P1 connects the RST signal in the equalizing circuit, and its source electrode and drain electrode are connected on the first matched signal line MLA and the second matched signal line MLB.
When comparing coupling, shown in figure 11, system works under clock signal clk; RST signal low level is effective, will be balanced to matched signal line MLA and matched signal line MLB, and balanced back matched line MLA and matched line MLB voltage are consistent; The DIS signal is that high level is effective, a N transistor npn npn N1 conducting, and node A is at first through N transistor npn npn N1 discharge; Be initialized to ground, the 5th P transistor npn npn P5 that is connected with node A is in conducting state.The EVAL signal is a low level, and the NEval signal is a high level, makes that the 2nd N transistor npn npn N2 and the 2nd P transistor npn npn P2 are off state.When the saltus step of EVAL signal is high level; The NEval signal is a low level, and the 2nd N transistor npn npn N2 and the 2nd P transistor npn npn P2 are conducting state, because the 2nd P transistor npn npn P2 conducting; Make the current mirror conducting; Node A is through the 3rd P transistor npn npn P3 charging, and the voltage that A is ordered rises, and matched signal line MLA is through current mirror charging in the feedback circuit.
Can be clear that in Figure 10 matched signal line MLB is through the discharge discharge, because in matching detection at the beginning; Node A is initialized to ground, and the 5th P transistor npn npn P5 is in conducting state always, and node A is through the 3rd P transistor npn npn P3 charging of current mirror; Node A voltage rises since 0, be elevated in the time of turn-offing the 5th P transistor npn npn P5 (Δ T) from 0 at the voltage of node A, if or non-memory cell content coupling; Then the matched signal line matees, and current mirror continues the charging to matched signal line MLA in the feedback control circuit at this moment, and its voltage is risen; And matched signal line MLB and discharge circuit constitute path, and its voltage is descended, and have voltage difference between matched signal line MLA and the matched signal line MLB; This voltage difference makes and sense amplifier SA upset produces coupling MLSO signal.
Voltage at node A is elevated in the time of turn-offing the 5th P transistor npn npn P5 (Δ T) from 0; If or non-memory cell content do not match, then the matched signal line does not match, or non-storage unit will be discharged through discharge circuit; Matched signal line MLA and matched signal line MLB voltage are descended; Voltage between the matched signal line is consistent basically, thereby can not make sense amplifier SA counter-rotating, does not produce coupling MLSO signal.
After the voltage of node A was elevated to shutoff the 5th P transistor npn npn P5, promptly feedback control circuit turn-offed discharge circuit, and discharge circuit no longer constitutes path with matched signal line MLB; Matched signal line MLB is in hold mode, if or non-memory cell content coupling, then matched signal line coupling; Current mirror continues matched signal line MLA is charged in the feedback control circuit; Its voltage is risen, and the voltage of matched signal line MLB keep, and has voltage difference between matched line MLA and the matched line MLB; This voltage official post sense amplifier SA upset produces the output of coupling MLSO signal.If or non-memory cell content do not match, then the matched signal line does not match, or the discharge of non-storage unit, and the voltage between the matched signal line is consistent basically, thereby can not make sense amplifier SA upset, does not produce coupling MLSO signal.
Need to prove that equalizing circuit also can realize its function by the transmission gate that the 3rd N transistor npn npn and the 6th P transistor npn npn are formed; The source electrode of the drain electrode of the 3rd N transistor npn npn and the 6th P transistor npn npn all is connected on the first matched signal line; The drain electrode of the source electrode of the 3rd N transistor npn npn and the 6th P transistor npn npn all is connected on the second matched signal line; The grid of the 6th P transistor npn npn connects reset signal, and the grid of said the 3rd N transistor npn npn connects non-reset signal.
The present invention can utilize the charging method of dynamic control matched signal line, in the coupling comparison procedure, reduces current drain, the voltage differential signal testing result of utilizing Δ T to produce constantly.The present invention is simple and reliable; Compare with traditional matched line detection method, reduce current drain, reduce extra bias voltage and bias current, can be applied in detection occasion different or non-structure matching line.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within these claims institute covering scope.The present invention's scope required for protection is only limited described claims.
Claims (12)
1. Content Addressable Memory storage unit matching detection method; The parallel connection of wherein some or non-storage unit forms the first matched signal line (MLA) and the second matched signal line (MLB), and said method comprises: the charging circuit that the said first matched signal line is charged, the feedback control circuit that is connected said second matched line; When said some or non-memory cell content is all mated, exist voltage difference to be enough to cause exporting matched signal between said first matched signal line and the said second matched signal line; When at least one content does not match in the said some or non-storage unit; The said first matched signal line charges to the said second matched signal line through the unmatched or non-storage unit of said content; And impel said feedback control circuit to turn-off said charging circuit, the voltage difference between said thus first matched signal line and the said second matched signal line is not enough to export matched signal.
2. Content Addressable Memory storage unit match detection circuit; Comprise pre-charge circuit, charging circuit, feedback control circuit, equalizing circuit and some or non-storage unit; Said pre-charge circuit is connected with said charging circuit and feedback control circuit; Form the first matched signal line and the second matched signal line by said some or non-storage unit parallel connection; Said charging circuit is connected with the said first matched signal line, and said feedback control circuit is connected with the said second matched signal line, and said equalizing circuit is connected between said first matched signal line and the said second matched signal line.
3. testing circuit as claimed in claim 2 is characterized in that,
Said pre-charge circuit comprises a P transistor npn npn (P1);
Said feedback control circuit comprises a N transistor npn npn (N1), the 2nd N transistor npn npn (N2) and the 3rd N transistor npn npn (N3);
Said the 2nd N transistor npn npn (N2) links to each other with the grid of said the 3rd N transistor npn npn (N3); Said the 2nd N transistor npn npn (N2) all is connected in the drain electrode of a said N transistor npn npn (N1) with the source electrode of said the 3rd N transistor npn npn (N3); The grid of a said N transistor npn npn (N1) connects assessing signal, and the source electrode of a said N transistor npn npn (N1) connects ground;
Said charging circuit comprises the 2nd P transistor npn npn (P2) and the 4th N transistor npn npn (N4);
The source electrode of a said P transistor npn npn (P1) is connected high level with the source electrode of said the 2nd P transistor npn npn (P2); The grid of a said P transistor npn npn (P1) connects precharging signal, and the drain electrode of the drain electrode of a said P transistor npn npn (P1) and said the 2nd N transistor npn npn (N2) is connected node (A); The grid of said the 2nd P transistor npn npn (P2) connects non-assessing signal, and the drain electrode of said the 2nd P transistor npn npn (P2) links to each other with the drain electrode of said the 4th N transistor npn npn (N4); The grid of said the 4th N transistor npn npn (N4) is connected node (A); The source electrode of said the 4th N transistor npn npn (N4) is connected with the said first matched signal line; Said the 2nd N transistor npn npn (N2) links to each other with the grid of said the 3rd N transistor npn npn (N3); Said the 2nd N transistor npn npn (N2) all is connected in the drain electrode of a said N transistor npn npn (N1) with the source electrode of said the 3rd N transistor npn npn (N3); The grid of a said N transistor npn npn (N1) connects assessing signal, and the source electrode of a said N transistor npn npn (N1) connects ground; The said second matched signal line is connected on the grid of said the 2nd N transistor npn npn (N2) and said the 3rd N transistor npn npn (N3), and the drain electrode of said the 3rd N transistor npn npn (N3) is connected on the said second matched signal line.
4. like claim 2 or 3 described testing circuits; It is characterized in that said testing circuit also comprises sense amplifier; Said sense amplifier is connected with the said second matched signal line with the said first matched signal line, is used for amplifying and output coupling or mismatch signal.
5. like claim 2 or 3 described testing circuits, it is characterized in that said equalizing circuit comprises the 5th N transistor npn npn (N5); The grid of said the 5th N transistor npn npn (N5) connects reset signal, and the drain electrode of said the 5th N transistor npn npn (N5) is connected with the said first coupling wire size line, and the source electrode of said the 5th N transistor npn npn (N5) is connected with the said second coupling wire size line.
6. like claim 2 or 3 described equalizing circuits, it is characterized in that said equalizing circuit comprises the transmission gate of being made up of the 6th N transistor npn npn and the 3rd P transistor npn npn;
The source electrode of the drain electrode of said the 6th N transistor npn npn and said the 3rd P transistor npn npn all is connected on the said first matched signal line; The drain electrode of the source electrode of said the 6th N transistor npn npn and said the 3rd P transistor npn npn all is connected on the said second matched signal line; The grid of said the 6th N transistor npn npn connects reset signal, and the grid of said the 3rd P transistor npn npn connects non-reset signal.
7. complementary Content Addressable Memory storage unit matching detection method; Wherein some or non-storage unit parallel connection forms the first matched signal line (MLA) and the second matched signal line (MLB); Said method comprises: the feedback control circuit, the discharge circuit to discharging at the second matched signal line that are connected the said first matched signal line; When said some or non-memory cell content is all mated, exist voltage difference to be enough to cause exporting matched signal between said first matched signal line and the said second matched signal line; When at least one content does not match in the said some or non-storage unit; Unmatched or the non-storage unit of said content is through said discharge circuit discharge; And impel said feedback control circuit to turn-off said discharge circuit, the voltage difference between said thus first matched signal line and the said second matched signal line is not enough to export matched signal.
8. complementary Content Addressable Memory storage unit match detection circuit; Comprise pre-arcing circuit, discharge circuit, feedback control circuit, equalizing circuit and some or non-storage unit; Said pre-arcing circuit is connected with said discharge circuit and feedback control circuit; By the parallelly connected first matched signal line and the second matched signal line that forms of said some or non-storage unit; Said feedback control circuit is connected with the said first matched signal line, and said discharge circuit is connected with the said second matched signal line, and said equalizing circuit is connected between said first matched signal line and the said second matched signal line.
9. testing circuit as claimed in claim 9 is characterized in that,
Said pre-arcing circuit comprises a N transistor npn npn (N1);
Said feedback control circuit comprises the 2nd P transistor npn npn (P2), the 3rd P transistor npn npn (P3) and the 4th P transistor npn npn (P4);
The grid of said the 2nd P transistor npn npn (P2) connects non-assessing signal; The source electrode of said the 2nd P transistor npn npn (P2) connects high level; Said the 3rd P transistor npn npn (P3) is connected and is connected with the drain electrode of said the 2nd P transistor npn npn (P2) with said the 4th P transistor npn npn (P4) source electrode, and the grid of said the 3rd P transistor npn npn (P3) and said the 4th P transistor npn npn (P4) links to each other;
Said discharge circuit comprises the 5th P transistor npn npn (P5) and the 2nd N transistor npn npn (N2);
The grid of said the 2nd P transistor npn npn (P2) connects non-assessing signal; The source electrode of said the 2nd P transistor npn npn (P2) connects high level; Said the 3rd P transistor npn npn (P3) is connected with said the 4th P transistor npn npn (P4) source electrode and is connected with the drain electrode of said the 2nd P transistor npn npn (P2); The drain electrode of the drain electrode of said the 3rd P transistor npn npn (P3) and a said N transistor npn npn (N1) is connected node (A); Said the 3rd P transistor npn npn (P3) links to each other with the grid of said the 4th P transistor npn npn (P4); The said first matched signal line is connected on the grid of said the 3rd P transistor npn npn (P3) and said the 4th P transistor npn npn (P4), and the drain electrode of said the 4th P transistor npn npn (P4) is connected with the said first matched signal line; The said second matched signal line is connected with the source electrode of said the 5th P transistor npn npn (P5), and the grid of said the 5th P transistor npn npn (P5) is connected node (A), and the drain electrode of said the 5th P transistor npn npn (P5) is connected with the drain electrode of said the 2nd N transistor npn npn (N2); The grid of said the 2nd N transistor npn npn (N2) connects assessing signal, and the grid of a said N transistor npn npn (N1) connects the pre-arcing signal, and the source electrode of said the 2nd N transistor npn npn (N2) all is connected low level with the source electrode of a said N transistor npn npn (N1).
10. like claim 2 or 3 described complementary testing circuits; It is characterized in that said testing circuit also comprises sense amplifier; Said sense amplifier is connected with the said second matched signal line with the said first matched signal line, is used for amplifying and output coupling or mismatch signal.
11. like claim 2 or 3 described complementary testing circuits; It is characterized in that said equalizing circuit comprises a P transistor npn npn; The grid of a said P transistor npn npn (P1) connects reset signal; The drain electrode of a said P transistor npn npn (P1) is connected on the said first coupling wire size line, and the source electrode of a said P transistor npn npn (P1) is connected on the said second coupling wire size line.
12., it is characterized in that said equalizing circuit comprises the transmission gate of being made up of the 6th P transistor npn npn and the 3rd N transistor npn npn like claim 2 or 3 described complementary testing circuits;
The source electrode of the drain electrode of said the 3rd N transistor npn npn and said the 6th P transistor npn npn all is connected on the said first matched signal line; The drain electrode of the source electrode of said the 3rd N transistor npn npn and said the 6th P transistor npn npn all is connected on the said second matched signal line; The grid of said the 6th P transistor npn npn connects reset signal, and the grid of said the 3rd N transistor npn npn connects non-reset signal.
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| CN201110347928.3A CN102403018B (en) | 2011-11-07 | 2011-11-07 | Matching detection method and circuit of content addressable memory cell |
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| CN201110347928.3A CN102403018B (en) | 2011-11-07 | 2011-11-07 | Matching detection method and circuit of content addressable memory cell |
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| CN102411995A (en) * | 2011-11-22 | 2012-04-11 | 中国科学院声学研究所 | Detection circuit and method for memory cell match line of content addressable memory |
| CN104756452A (en) * | 2012-08-15 | 2015-07-01 | 马维尔国际贸易有限公司 | Switched continuous time linear equalizer with integrated sampler |
| CN107437425A (en) * | 2016-05-25 | 2017-12-05 | 格罗方德半导体公司 | Matched line for the matched line sensing of self reference is pre-charged framework |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102411995A (en) * | 2011-11-22 | 2012-04-11 | 中国科学院声学研究所 | Detection circuit and method for memory cell match line of content addressable memory |
| CN102411995B (en) * | 2011-11-22 | 2014-03-12 | 中国科学院声学研究所 | Detection circuit and method for memory cell match line of content addressable memory |
| CN104756452A (en) * | 2012-08-15 | 2015-07-01 | 马维尔国际贸易有限公司 | Switched continuous time linear equalizer with integrated sampler |
| CN104756452B (en) * | 2012-08-15 | 2018-07-06 | 马维尔国际贸易有限公司 | Switching regulator continuous time linear equalizer with integrated sampler |
| CN107437425A (en) * | 2016-05-25 | 2017-12-05 | 格罗方德半导体公司 | Matched line for the matched line sensing of self reference is pre-charged framework |
| CN107437425B (en) * | 2016-05-25 | 2020-12-08 | 马维尔亚洲私人有限公司 | Matchline precharge architecture for self-referenced matchline sensing |
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| CN102403018B (en) | 2014-04-30 |
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