CN102436853A - Design method of memory capacity variable SAS-RAID (Serial Attached SCSI (Small Computer System Interface)-Redundant Array of Independent Disk) card - Google Patents
Design method of memory capacity variable SAS-RAID (Serial Attached SCSI (Small Computer System Interface)-Redundant Array of Independent Disk) card Download PDFInfo
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- CN102436853A CN102436853A CN2011103601891A CN201110360189A CN102436853A CN 102436853 A CN102436853 A CN 102436853A CN 2011103601891 A CN2011103601891 A CN 2011103601891A CN 201110360189 A CN201110360189 A CN 201110360189A CN 102436853 A CN102436853 A CN 102436853A
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Abstract
The invention provides a design method of a memory capacity variable SAS-RAID (Serial Attached SCSI (Small Computer System Interface)-Redundant Array of Independent Disk) card. DDR2 (Double Data Rate 2) memory particle configuration of a system reaches an optimal configuration by adjusting DDR2 memory particles and replacing different DDR2 memory particle configurations. The design method comprises the following concrete steps of: (1), connecting a 15th address line of the DDR2 memory particles to an SAS-RAID master controller according to the memory capacity specification, so that the memory capacity specification supported by the card reaches 1GN at most; (2) connecting five memory particles with the SAS-RAID card by using a gold finger slot way, wherein the total memory capacity of the card is realized by using the five memory particles, and one of the memory particles is used for ECC (Error Correction Code) checking; (3) inserting corresponding memory particles to slot positions of the five gold finger slots according to the capacity specification of the selected single memory particle and the data caching capacity requirement of a user on the SAS-RAID card; and (4) connecting the 15 address line of the DDR 2 memory particles to the SAS-RAID master controller, wherein the highest address line, namely the 15th address line, is increased, and a corresponding connecting line needs to be corrected in the process of manufacturing a PCB (Printed Circuit Board) panel.
Description
Technical field
The present invention relates to computer communication field, specifically is the method for designing of utilizing the variable memory size of a kind of SAS-RAID card, solves different system to SAS-RAID card buffer memory capacity problem, has greatly made things convenient for upgrading of SAS-RAID card buffer memory capacity and performance boost.
Background technology
Current server product; The continuous variation of client's application demand needs RAID to form disk array and ensures that server is long-term continual stable, in order to guarantee the stable transfer of system data; Be integrated with internal memory particle chip mostly at the SAS-RAID card; As the buffer zone of data, the SAS-RAID card of present main flow, the buffer zone of its data is that memory size is between 128MB～1GB; Therefore in the functional test of carrying out the server system level, SAS-RAID card metadata cache zone is that the memory size size is one of extremely important factor that influences server performance.
Before the SAS-RAID card use, the user generally is that the SAS-RAID card outer plug-in card with the fixed cache capacity is directly installed in the server system, when the user strengthens the hard disk operation data traffic; SAS-RAID card metadata cache becomes one of important indicator that influences transmission performance; Improve performance if want to strengthen buffer memory capacity this moment, can only be through changing the mode of SAS-RAID card; The user will greatly rise to the management input cost of data, and causes unnecessary waste.
Summary of the invention
The method for designing that the purpose of this invention is to provide a kind of variable memory size SAS-RAID card.
The objective of the invention is to realize that adjustment DDR2 internal memory particle is changed different DDR2 internal memory particle configurations, the DDR2 internal memory particle of system is disposed reach allocation optimum by following mode; Concrete steps are following
1) according to the memory size specification, 15 address wires of DDR2 internal memory particle to be linked on the SAS-RAID master controller, the memory size specification maximum that card is supported can reach 1GB;
2) total memory size of card is realized by five internal memory particles, and wherein a slice is as the ECC verification, and the mode that five internal memory particles pass through the golden finger slot links to each other with the SAS-RAID card;
3) according to the capacity specifications and the capacity requirement of user to SAS-RAID card metadata cache of single selected internal memory particle, the corresponding internal memory particle of insertion gets final product on the groove position of five golden finger slots;
4) 15 address wires of DDR2 internal memory particle are linked on the SAS-RAID master controller, increase be the highest addresses line, also i.e. the 15th bit address line need be revised respective gut when the manufacturing PCB integrated circuit board.
Five internal memory particles link to each other with the SAS-RAID card through the mode of golden finger slot; Five golden finger slots independently, respectively corresponding five internal memory particles, one of them does the operation of ECC verification need do mark; If need the ECC verification, the internal memory particle must be inserted in this groove position.
On the groove position of five golden finger slots, insert corresponding internal memory particle, five golden finger slots are welded on the PCB, and golden finger interface is provided.
The invention has the beneficial effects as follows: we can carry out the updating operation of memory size under the system very easily, have not only reached the requirement to memory size, and have saved the cost of research and development neocaines, have improved work efficiency, have improved the dirigibility of system configuration.Thereby, have good value for applications.
Description of drawings
Fig. 1 is the design procedure process flow diagram of variable memory size SAS-RAID card.
Embodiment
Explanation at length below with reference to Figure of description method of the present invention being done.
The method for designing of variable memory size SAS-RAID card of the present invention is with internal memory particle theory support point, solves different system to SAS-RAID card buffer memory capacity problem, and concrete summary of the invention can be realized through following steps:
1) according to the memory size specification, 15 address wires of DDR2 internal memory particle to be linked on the SAS-RAID master controller, the memory size specification maximum that card is supported can reach 1GB;
2) total memory size of card is realized by five internal memory particles, and wherein a slice is as the ECC verification, and the mode that five internal memory particles pass through the golden finger slot links to each other with the SAS-RAID card;
3) according to the capacity specifications and the capacity requirement of user to SAS-RAID card metadata cache of single selected internal memory particle, the corresponding internal memory particle of insertion gets final product on five groove positions;
4) 15 address wires of DDR2 internal memory particle are linked on the SAS-RAID master controller, increase be the highest addresses line, also i.e. the 15th bit address line need be revised respective gut when the manufacturing PCB integrated circuit board;
5) five internal memory particles link to each other with the SAS-RAID card through the mode of golden finger slot; What adopt is five independently golden finger slots, respectively corresponding five internal memory particles, and one of them does the operation of ECC verification need do mark; If need the ECC verification, the internal memory particle must be inserted in this groove position;
6) on five groove positions, insert corresponding internal memory particle, the internal memory particle is welded on the PCB by single internal memory particle, and golden finger interface is provided.
Embodiment:
Carry out more detailed elaboration in the face of content of the present invention down shown in the by specification accompanying drawing:
A) the research and development slip-stick artist at first will link 15 address wires of DDR2 internal memory particle on the SAS-RAID master controller according to the memory size specification, promptly increases the highest addresses line, is the 15th bit address line also, need when the manufacturing PCB integrated circuit board, revise respective gut;
B) five internal memory particles link to each other with the SAS-RAID card through the mode of golden finger slot;
C) the internal memory particle of insertion respective volume on five groove positions; As insert single and be the internal memory particle of 256MB, if five are all inserted, realize that then overall buffer memory capacity is 1GB; If inserting two is internal memory particle and the access ECC particle of 256MB, realize that then overall buffer memory capacity is 512MB; According to The performance test results, adjustment internal memory particle is changed different internal memory particle configurations, makes the internal memory particle configuration of system reach optimum;
Through top detailed enforcement, we can carry out the updating operation of memory size under the system very easily, have not only reached the requirement to memory size, and have saved the cost of research and development neocaines, have improved work efficiency, have improved the dirigibility of system configuration.
Except that the described technical characterictic of instructions, be the known technology of those skilled in the art.
Claims (2)
1. the method for designing of a variable memory size SAS-RAID card is characterized in that adjusting DDR2 internal memory particle, changes different DDR2 internal memory particle configurations, makes the DDR2 internal memory particle configuration of system reach allocation optimum; Concrete steps are following
1) according to the memory size specification, 15 address wires of DDR2 internal memory particle to be linked on the SAS-RAID master controller, the memory size specification maximum that card is supported can reach 1GB;
2) total memory size of card is realized by five internal memory particles, and wherein a slice is as the ECC verification, and the mode that five internal memory particles pass through the golden finger slot links to each other with the SAS-RAID card;
3) according to the capacity specifications and the capacity requirement of user of single selected internal memory particle to SAS-RAID card metadata cache, the corresponding internal memory particle of insertion on the groove position of five golden finger slots;
4) 15 address wires of DDR2 internal memory particle are linked on the SAS-RAID master controller, increase be the highest addresses line, also i.e. the 15th bit address line need be revised respective gut when the manufacturing PCB integrated circuit board;
5) five internal memory particles link to each other with the SAS-RAID card through the mode of golden finger slot; Five golden finger slots independently, respectively corresponding five internal memory particles, one of them does the operation of ECC verification need do mark; If need the ECC verification, the internal memory particle must be inserted in this groove position.
2. method according to claim 1 is characterized in that, on the groove position of five golden finger slots, inserts corresponding internal memory particle, and five golden finger slots are welded on the PCB, and golden finger interface is provided.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103601891A CN102436853A (en) | 2011-11-15 | 2011-11-15 | Design method of memory capacity variable SAS-RAID (Serial Attached SCSI (Small Computer System Interface)-Redundant Array of Independent Disk) card |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103601891A CN102436853A (en) | 2011-11-15 | 2011-11-15 | Design method of memory capacity variable SAS-RAID (Serial Attached SCSI (Small Computer System Interface)-Redundant Array of Independent Disk) card |
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| CN102436853A true CN102436853A (en) | 2012-05-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106815161A (en) * | 2017-01-22 | 2017-06-09 | 郑州云海信息技术有限公司 | A kind of the HBA SAS cards methods for designing and structure of compatible difference buffer memory capacity |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1350216A (en) * | 2000-10-19 | 2002-05-22 | 周先谱 | Computer main board design and processing method |
| US20100274999A1 (en) * | 2009-04-25 | 2010-10-28 | Hon Hai Precision Industry Co., Ltd. | Control system and method for memory |
| CN202013742U (en) * | 2011-04-28 | 2011-10-19 | 浪潮电子信息产业股份有限公司 | Redundant array of independent disks (RAID) card with data caching protection |
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- 2011-11-15 CN CN2011103601891A patent/CN102436853A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1350216A (en) * | 2000-10-19 | 2002-05-22 | 周先谱 | Computer main board design and processing method |
| US20100274999A1 (en) * | 2009-04-25 | 2010-10-28 | Hon Hai Precision Industry Co., Ltd. | Control system and method for memory |
| CN202013742U (en) * | 2011-04-28 | 2011-10-19 | 浪潮电子信息产业股份有限公司 | Redundant array of independent disks (RAID) card with data caching protection |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106815161A (en) * | 2017-01-22 | 2017-06-09 | 郑州云海信息技术有限公司 | A kind of the HBA SAS cards methods for designing and structure of compatible difference buffer memory capacity |
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Application publication date: 20120502 |