CN102437090A - Copper back channel interconnecting process without metal blocking layer - Google Patents
Copper back channel interconnecting process without metal blocking layer Download PDFInfo
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- CN102437090A CN102437090A CN2011101942425A CN201110194242A CN102437090A CN 102437090 A CN102437090 A CN 102437090A CN 2011101942425 A CN2011101942425 A CN 2011101942425A CN 201110194242 A CN201110194242 A CN 201110194242A CN 102437090 A CN102437090 A CN 102437090A
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Abstract
The invention relates to a copper back channel interconnecting process without a metal blocking layer, which solves the problems that in the prior art, the residue of a metal layer etching blocking layer exists in the metal wire connecting process, so the integral capacitance is increased, and the long capacitance delay time is further caused. After the metal layer etching blocking layer is deposited, the excessive metal layer etching blocking layer in a non-metal conducting wire region is firstly removed through photoetching and etching, then, metal insulation media are deposited, a metal conducting wire groove is photoetched and etched again, in addition, the rest metal layer etching blocking layer at the lower part of the metal conducting wire groove is removed, and finally, the copper interconnecting process without the metal layer etching blocking layer is realized.
Description
Technical field
The present invention relates to a kind of metal interconnected technology, relate in particular to a kind of copper post-channel interconnection technology of not having metal barrier.
Background technology
Along with the continuous progress of integrated circuit fabrication process, it is more and more littler that the volume of semiconductor device is just becoming, and they coupled together also difficult more.In in the past 30 years, semi-conductor industry circle all is with the material of aluminium as interface unit, but along with the dwindling of chip, industrial quarters needs thinner, thinner connection, and also the high-ohmic of aluminium also more and more is difficult to meet demand.And under the situation of high density ULSI, high resistance causes electronics that " wire jumper " takes place easily, and near the device causing produces wrong on off state.That is to say, with aluminium as the chip of lead possibly produce can't with the function situation of prediction, stability is also relatively poor simultaneously.On so trickle circuit, the transmission signals speed of copper is faster and more stable than aluminium.
The metal connecting line of tradition integrated circuit is to make plain conductor with the etching mode of metal level, carries out the filling of dielectric layer, the chemico-mechanical polishing of dielectric layer then, repeats above-mentioned operation, and then successfully carries out the multiple layer metal stack.But when the material of plain conductor converts the lower copper of resistance aluminium to by aluminium since the dried quarter of copper difficulty comparatively, therefore new embedding technique is just very necessary concerning the processing procedure of copper.
Embedding technique is called Damascus technics again, and this technology is etching metallic channel on dielectric layer at first, and then fills metal, again metal is carried out metal mechanical polishing, repeats above-mentioned operation, and then successfully carries out the multiple layer metal stack.The main characteristics of embedding technique are the etching technics that need not carry out metal level, and these promotion and application to process for copper are very important.
Ic manufacturing technology has striden into the epoch of 130nm.Present most copper wirings are in 180 to the 130nm operation stage, and about 40% logical circuit production line can be used the copper Wiring technique.Arrived the 90nm operation stage, 90% semiconductor production line employing copper Wiring technique has then been arranged.Damascus mosaic technology that adopts Cu-CMP is present unique maturation and the graphical technology of copper in the IC manufacturing of successful Application.
Multilayer interconnection CALCULATION OF CAPACITANCE formula:
Wherein, k is a dielectric constant; L is that plain conductor is long; T is the plain conductor degree of depth; W is the plain conductor width;
is permittivity of vacuum; Visible by formula 1; Dielectric constant is low more, and electric capacity is more little.
Multilayer interconnection resistance-electric capacity time delay computing formula:
Wherein, (k is a dielectric constant; L is that plain conductor is long; T is the plain conductor degree of depth; W is the plain conductor width;
is permittivity of vacuum;
is the metallic resistance rate) visible by formula 2; Dielectric constant is low more; Resistivity is little, and multilayer interconnection resistance-electric capacity time delay is also short more.
Integral capacitor by the visible device of formula depends on metal level dielectric and metal level etching barrier layer.Usually the metal level etching barrier layer is materials such as silicon nitride or carborundum, and they can provide higher etching selection ratio to prevent to damage when plain conductor is groove etched layer device or metal down.But these materials are because its dielectric constant far above the metal level dielectric, and then causes whole capacitance values to rise.
Summary of the invention
The invention discloses a kind of copper post-channel interconnection technology of not having metal barrier, carry out in the prior art in the metal connecting line process owing to exist the residual integral capacitor that causes of metal level etching barrier layer to rise in order to solve, and then cause long problem of capacitance delays time.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of copper post-channel interconnection technology of not having metal barrier is formed with the source/leakage doped region of MOS memory in a substrate, on substrate, be formed with the grid of MOS memory; One contact hole etching barrier layer covers substrate and is arranged on the grid on the substrate; And the top on contact hole etching barrier layer also is coated with one deck contact hole insulating oxide layer film; And formation runs through a plurality of through holes on contact hole insulating oxide layer film and contact hole etching barrier layer; Partial through holes contact grid, partial through holes contact source/leakage doped region, and also be filled with metal material in the through hole; Deposit one metal level etching barrier layer on contact hole insulating oxide layer film wherein, may further comprise the steps:
Step a: the metal level etching barrier layer is carried out etching, only keep the residual region of the metal level etching barrier layer that is positioned at the through hole top and contacts with through hole, remaining metal level etching barrier layer etching is removed;
Step b: deposit one a metallic channel insulating barrier and a hard mask layer on contact hole insulating oxide layer film, the metallic channel insulating barrier covers the top of the residual region of metal level etching barrier layer simultaneously, and deposit one hard mask layer covers on the metallic channel insulating barrier more afterwards;
Step c: form the opening in the hard mask layer, and utilize the opening in the hard mask layer that the metallic channel insulating barrier is carried out etching, the metallic channel insulating barrier above the residual region of metal level etching barrier layer is etched away, in the metallic channel insulating barrier, to form metallic channel; Steps d: etching is removed metal remained layer etching barrier layer, is filled with the through hole of metal material with the bottom-exposed at metallic channel, afterwards depositing metal copper in metallic channel again;
Step e: carry out copper metal mechanical polishing process, the hard mask on the metallic channel insulating barrier is removed.
The copper post-channel interconnection technology of aforesaid no metal barrier wherein, also comprises before the step a: spin coating photoresist on the metal level etching barrier layer, and carry out photoetching.
The copper post-channel interconnection technology of aforesaid no metal barrier wherein, also comprises before the step c: spin coating photoresist on hard mask layer, photoetching forms the metallic channel figure.
The copper post-channel interconnection technology of aforesaid no metal barrier wherein, also is deposited with one deck contact hole etching barrier layer between contact hole insulating oxide layer film and substrate.
The copper post-channel interconnection technology of aforesaid no metal barrier, wherein, through passing the contact hole insulating oxide.
The copper post-channel interconnection technology of aforesaid no metal barrier wherein, is formed with the device side wall in the side of transistor gate.
In sum; Exist the residual integral capacitor that causes of metal level etching barrier layer to rise because the copper post-channel interconnection technology that adopted technique scheme, the present invention not to have metal barrier has solved in the prior art in the metal connecting line process, and then cause long problem of capacitance delays time; Behind the deposited metal etching barrier layer; Rely on photoetching, etching at first to remove the excess metal layer etching barrier layer of nonmetal conductor area, depositing metal dielectric subsequently, photoetching once more, etching metallic channel; And remove the residual metallic layer etching barrier layer that places the metallic channel bottom, finally realize the copper wiring technique of no metal level etching barrier layer.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.
Fig. 1 is the device cutaway view after the back road metal etch barrier deposit of the present invention's copper post-channel interconnection technology of not having metal barrier;
Fig. 2 is the photoetching of the completion metal etch barrier of the present invention's copper post-channel interconnection technology of not having metal barrier, the cutaway view after the etching;
Fig. 3 is the cutaway view after completion metallic channel insulating material and the hard mask deposition of the present invention's copper post-channel interconnection technology of not having metal barrier;
Fig. 4 is the cutaway view of the completion plain conductor of the present invention's copper post-channel interconnection technology of not having metal barrier after groove etched;
Fig. 5 is removing the metal level etching barrier layer and accomplishing the cutaway view that the metal level metallic copper is electroplated of the present invention's copper post-channel interconnection technology of not having metal barrier;
Fig. 6 is the cutaway view after surface hard mask is removed in the completion copper metal mechanical polishing of the present invention's copper post-channel interconnection technology of not having metal barrier.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Fig. 1 is the device cutaway view after the back road metal etch barrier deposit of the present invention's copper post-channel interconnection technology of not having metal barrier; See also Fig. 1; A kind of copper post-channel interconnection technology of not having metal barrier; In a substrate 10, be formed with the source/leakage doped region of MOS memory, on substrate 10, be formed with the grid 20 of MOS memory; One contact hole etching barrier layer 30 covers substrate 10 and is arranged on the grid 20 on the substrate 10; And the top on contact hole etching barrier layer 30 also is coated with one deck contact hole insulating oxide layer film 40; And formation runs through a plurality of through holes on contact hole insulating oxide layer film 40 and contact hole etching barrier layer 30; Partial through holes contact grid 20, partial through holes contact source/leakage doped region, and also be filled with metal material in the through hole 401; Deposit one metal level etching barrier layer 50 on contact hole insulating oxide layer film 40 wherein, may further comprise the steps:
Fig. 2 is the photoetching of the completion metal etch barrier of the present invention's copper post-channel interconnection technology of not having metal barrier, the cutaway view after the etching; See also Fig. 2; Step a: metal level etching barrier layer 50 is carried out etching; Only keep the residual region of the metal level etching barrier layer 50 that is positioned at through hole 401 tops and contacts with through hole 401, remaining metal level etching barrier layer 50 etching is removed, and the metal level etching barrier layer 50 that it kept blocks the open upper end of through hole 401 fully;
Further, also comprise before the step a: spin coating photoresist on metal level etching barrier layer 50, and carry out photoetching, form the etching figure, and, after step a, need photoresist be removed.
Fig. 3 is the cutaway view after completion metallic channel insulating material and the hard mask deposition of the present invention's copper post-channel interconnection technology of not having metal barrier; See also Fig. 3; Step b: deposit one a metallic channel insulating barrier 60 and a hard mask layer 70 successively from down to up on contact hole insulating oxide layer film 40; Metallic channel insulating barrier 60 covers metal remained layer etching barrier layer 50 with hard mask layer 70 simultaneously; That is to say that metallic channel insulating barrier 60 covers the top of the residual region of metal level etching barrier layer 50 simultaneously, deposit one hard mask layer 70 covers on the metallic channel insulating barrier 60 more afterwards;
Fig. 4 is the cutaway view of the completion plain conductor of the present invention's copper post-channel interconnection technology of not having metal barrier after groove etched; See also Fig. 4; Step c: form the opening in the hard mask layer 70; And utilize the opening in the hard mask layer 70 that metallic channel insulating barrier 60 is carried out etching, the metallic channel insulating barrier 60 above the residual region of metal level etching barrier layer 50 is etched away, in metallic channel insulating barrier 60, to form metallic channel;
Further, also comprise before the step c: spin coating photoresist on hard mask layer 70, photoetching forms the metallic channel figure.
Fig. 5 is removing the metal level etching barrier layer and accomplishing the cutaway view that the metal level metallic copper is electroplated of the present invention's copper post-channel interconnection technology of not having metal barrier; See also Fig. 5; Steps d: etching is removed metal remained layer etching barrier layer 50; Be filled with the through hole 401 of metal material with the bottom-exposed of metallic channel, afterwards depositing metal copper 80 in metallic channel again; Etching after removing metal remained layer etching barrier layer 50 is removed the photoresist of spin coating before the step c, and through behind the above-mentioned processing step, metal level etching barrier layer 50 is removed fully, thereby has realized the copper post-channel interconnection technology of no metal level etching barrier layer 50.
Fig. 6 is the cutaway view after surface hard mask is removed in the completion copper metal mechanical polishing of the present invention's copper post-channel interconnection technology of not having metal barrier; See also Fig. 6; After steps d, also comprise step e: carry out copper metal mechanical polishing process, the hard mask on the metallic channel insulating barrier 60 is removed.
Between contact hole insulating oxide layer film 40 and substrate 10, also be deposited with one deck contact hole etching barrier layer 30 among the present invention, through passing the contact hole insulating oxide.
Be formed with device side wall 201 in the side of transistor gate 20 among the present invention.
In sum; Exist the residual integral capacitor that causes of metal level etching barrier layer to rise because the copper post-channel interconnection technology that adopted technique scheme, the present invention not to have metal barrier has solved in the prior art in the metal connecting line process, and then cause long problem of capacitance delays time; Behind the deposited metal etching barrier layer; Rely on photoetching, etching at first to remove the excess metal layer etching barrier layer of nonmetal conductor area, depositing metal dielectric subsequently, photoetching once more, etching metallic channel; And remove the residual metallic layer etching barrier layer that places the metallic channel bottom, finally realize the copper wiring technique of no metal level etching barrier layer.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and the foregoing description can realize said variant, do not repeat them here.Such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that; The present invention is not limited to above-mentioned specific implementations; Any those of ordinary skill in the art are not breaking away under the technical scheme scope situation of the present invention, and all the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (6)
1. copper post-channel interconnection technology of not having metal barrier is formed with the source/leakage doped region of MOS memory in a substrate, on substrate, be formed with the grid of MOS memory; One contact hole etching barrier layer covers substrate and is arranged on the grid on the substrate; And the top on contact hole etching barrier layer also is coated with one deck contact hole insulating oxide layer film; And formation runs through a plurality of through holes on contact hole insulating oxide layer film and contact hole etching barrier layer; Partial through holes contact grid, partial through holes contact source/leakage doped region, and also be filled with metal material in the through hole; Deposit one metal level etching barrier layer is characterized in that on contact hole insulating oxide layer film, may further comprise the steps:
Step a: the metal level etching barrier layer is carried out etching, only keep the residual region of the metal level etching barrier layer that is positioned at the through hole top and contacts with through hole, remaining metal level etching barrier layer etching is removed;
Step b: deposit one a metallic channel insulating barrier and a hard mask layer on contact hole insulating oxide layer film, the metallic channel insulating barrier covers the top of the residual region of metal level etching barrier layer simultaneously, and deposit one hard mask layer covers on the metallic channel insulating barrier more afterwards;
Step c: form the opening in the hard mask layer, and utilize the opening in the hard mask layer that the metallic channel insulating barrier is carried out etching, the metallic channel insulating barrier above the residual region of metal level etching barrier layer is etched away, in the metallic channel insulating barrier, to form metallic channel; Steps d: etching is removed metal remained layer etching barrier layer, is filled with the through hole of metal material with the bottom-exposed at metallic channel, afterwards depositing metal copper in metallic channel again;
Step e: carry out copper metal mechanical polishing process, the hard mask on the metallic channel insulating barrier is removed.
2. the copper post-channel interconnection technology of no metal barrier according to claim 1 is characterized in that, also comprises before the step a: spin coating photoresist on the metal level etching barrier layer, and carry out photoetching.
3. the copper post-channel interconnection technology of no metal barrier according to claim 1 is characterized in that, also comprises before the step c: spin coating photoresist on hard mask layer, photoetching forms the metallic channel figure.
4. the copper post-channel interconnection technology of no metal barrier according to claim 1 is characterized in that, between contact hole insulating oxide layer film and substrate, also is deposited with one deck contact hole etching barrier layer.
5. the copper post-channel interconnection technology of no metal barrier according to claim 4 is characterized in that, through passing the contact hole insulating oxide.
6. the copper post-channel interconnection technology of no metal barrier according to claim 1 is characterized in that, is formed with the device side wall in the side of transistor gate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110194242.5A CN102437090B (en) | 2011-07-12 | 2011-07-12 | Copper back channel interconnecting process without metal blocking layer |
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| CN201110194242.5A CN102437090B (en) | 2011-07-12 | 2011-07-12 | Copper back channel interconnecting process without metal blocking layer |
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| CN102437090A true CN102437090A (en) | 2012-05-02 |
| CN102437090B CN102437090B (en) | 2015-01-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425065A (en) * | 2012-09-19 | 2017-12-01 | 英特尔公司 | Gate contacts structure and its manufacture method on active gate |
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| US5854124A (en) * | 1997-02-04 | 1998-12-29 | Winbond Electronics Corp. | Method for opening contacts of different depths in a semiconductor wafer |
| US6380084B1 (en) * | 2000-10-02 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling |
| US20040097099A1 (en) * | 2002-11-15 | 2004-05-20 | Lih-Ping Li | Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer |
| CN1893020A (en) * | 2005-07-06 | 2007-01-10 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the same |
| CN101202244A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Method for removing photoresist graphical in forming process of dual embedded structure |
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2011
- 2011-07-12 CN CN201110194242.5A patent/CN102437090B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854124A (en) * | 1997-02-04 | 1998-12-29 | Winbond Electronics Corp. | Method for opening contacts of different depths in a semiconductor wafer |
| US6380084B1 (en) * | 2000-10-02 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling |
| US20040097099A1 (en) * | 2002-11-15 | 2004-05-20 | Lih-Ping Li | Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer |
| CN1893020A (en) * | 2005-07-06 | 2007-01-10 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the same |
| CN101202244A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Method for removing photoresist graphical in forming process of dual embedded structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425065A (en) * | 2012-09-19 | 2017-12-01 | 英特尔公司 | Gate contacts structure and its manufacture method on active gate |
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