CN102446862A - Novel double-bit line SONOS (silicon oxide nitride oxide silicon) unit structure and manufacturing method thereof - Google Patents
Novel double-bit line SONOS (silicon oxide nitride oxide silicon) unit structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a novel double-bit line SONOS (silicon oxide nitride oxide silicon) unit structure and a manufacturing method thereof. According to the invention, double-bit line data can be saved to an SONOS memory cell, and the storage capacity can be improved one time on premise of not changing device size. The structure adopts an STI (shallow trench isolation) idea, and two bit lines of the same unit are subjected to physical isolation, thus the charge transverse diffusion between bit lines is prevented, further the on-off state of each bit line is accurately determined, and the durability of each bit data and the retentivity of charge of the memory cell are improved.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor storage element, relate in particular to a kind of realize same storage element can preserve the SONOS memory cell of twin bit data, and preparation method thereof.
Background technology
The basic functional principle of non-volatile semiconductor memory is a stored charge in the gate medium of a MOSFET.Wherein the device that is stored in the trapping centre of separation of a suitable dielectric layer of electric charge is called as the electric charge capture device.The most frequently used in this type device is silicon-silica-silicon nitride-silica-silicon (SONOS) memory.Non-volatility memorizer is being played the part of important role in semiconductor storage unit.Along with constantly reducing of NVM device size, the leakage current of the non-volatile volatile storage of floating gate type constantly increases along with reducing of tunneling oxide thickness, make tunneling oxide thickness continue reduce to be restricted.Therefore, use the trap material to be paid close attention to by people as the SONOS memory of charge storage media, the trap material is iunjected charge fixedly, has stoped the leakage of stored charge to a certain extent.The SONOS memory except size is little, also have good tolerability, low operating voltage, low-power consumption, technology simple, with advantage such as standard CMOS process compatibility.
Traditional SONOS structure is as shown in Figure 1, and the bottom is a matrix 1, and both sides are respectively source electrode 11 and drain electrode 12, up are tunnel oxide 2, accumulation layer 3, barrier oxide layer 4 and polysilicon gate 5 successively.
Continuous development along with semiconductor technology; The memory device volume is more and more littler, but to the data memory space require increasingly high; How guarantee that the memory device volume reduces or constant and stable prerequisite under, the memory capacity that increases substantially memory device has become present memory technology development key.
Summary of the invention
The invention provides a kind of novel two bit lines (twin bit) SONOS cellular construction and preparation method thereof; The data that the SONOS memory cell can be preserved twin bit have been realized; Under the prerequisite that does not change device size, memory capacity is doubled like this.And the theory of this structure reference STI (shallow trench isolation); It is isolated that two bit lines of same unit are carried out physics; Thereby stoped electric charge horizontal proliferation between the bit line; Further realized accurately confirming the on off state of each bit line, each bit line data endurance and the electric charge retentivity of memory cell all improved.
First purpose of the present invention provides the manufacture method of a kind of pair of bit line SONOS cellular construction, and step comprises:
The cvd silicon oxide barrier layer is to remain the grid body upper surface parallel in the step 5, the polysilicon of removing deposition in the step 4 and step 3;
In the above-mentioned manufacture method of the present invention, said groove width is preferably 70 ~ 80nm.
In the above-mentioned manufacture method of the present invention, the barrier layer thickness of cvd silicon oxide described in the step 3 is preferably 80 ~ 200A.
In the above-mentioned manufacture method of the present invention, the deposition process of silica barrier layer described in the step 3 preferably adopts original position steam to generate technology (ISSG, In-situ Steam Generation), but also can be other prior art well known by persons skilled in the art.
In the above-mentioned manufacture method of the present invention, the method for polysilicon deposition described in the step 4 preferably adopts high depth ratio to fill out ditch technology (HARP, High Aspect Ratio Process), but also can be other prior art well known by persons skilled in the art.
In the above-mentioned manufacture method of the present invention, remove the polysilicon of deposition and the method employing CMP process (CMP, Chemical Mechanical Polishing) of silica barrier layer in the step 5.
The above-mentioned HARP of the present invention, ISSG, CMP technology are prior art.
Second purpose of the present invention provides two bit line SONOS cellular constructions that a kind of as above-mentioned method is made; Comprise silicon base and two grids that are positioned at said silicon base upper surface, said two grids are followed successively by oxide layer, reservoir, barrier layer and polysilicon layer from the bottom to top; Through trench isolations, be filled with polysilicon in the said groove between said two grids; Do not have ion implanted region between said two grids, said silicon base in two grid outsides partly is respectively the ion implanted region of source end and drain terminal.Wherein, the said outside refer to be the opposing side of said grid and groove.
Also contain one deck silicon oxide layer between polysilicon of filling in the SONOS cellular construction that the present invention is above-mentioned, said groove and the trench wall.Polysilicon of wherein, filling in the said groove and the silicon oxide layer thickness between the trench wall are preferably 80 ~ 200A.
The SONOS cellular construction that the present invention is above-mentioned, said groove width (i.e. distance between two grids) is preferably 70 ~ 80nm.
The SONOS cellular construction that the present invention is above-mentioned, said feature sizes of grids are 50 ~ 350nm.
Two bit line SONOS cellular constructions of the present invention's preparation are realized the data that the SONOS memory cell can be preserved twin bit, under the prerequisite that does not change device size, memory capacity are doubled like this.And the theory of this structure reference STI (shallow trench isolation); It is isolated that 2 bit lines of same unit are carried out physics; Thereby stoped electric charge horizontal proliferation between the bit line; Further realized accurately confirming the on off state of each bit, each bit data endurance and the electric charge retentivity of memory cell all improved.
Description of drawings
Fig. 1 is a SONOS cellular construction sketch map in the prior art;
Fig. 2 is the two bit line SONOS cellular construction manufacture method flow charts of the present invention, wherein:
Fig. 2 A is the preparation of SONOS grid matrix;
Fig. 2 B is for to carry out etching to SONOS grid matrix;
Fig. 2 C is the cvd silicon oxide barrier layer;
Fig. 2 D is a deposit spathic silicon;
Fig. 2 E is for removing silica barrier layer and polysilicon;
Fig. 3 is the two bit line SONOS cellular construction sketch mapes of the present invention, wherein:
Fig. 3 A is two two grids of bit line SONOS cellular construction of the present invention and groove structure sketch map;
Fig. 3 B is the two bit line SONOS cellular construction detailed structure sketch mapes of the present invention.
Embodiment
The invention provides the manufacture method of a kind of pair of bit line SONOS cellular construction, after the deposit of SONOS grid polycrystalline silicon is accomplished, light shield of extra increase; Etching polysilicon gate in the SONOS unit goes out a groove (70 ~ 80nm); (thickness is followed deposit silicon crystal silicon again 80 ~ 100A), and groove is filled to use the silicon oxide deposition barrier layer afterwards; Carry out the polysilicon gate planarization then, form novel SONOS memory cell grid.The characteristic line breadth of the polysilicon gate of made is about 50-350nm; The data that the SONOS memory cell can be preserved twin bit have been realized; And the theory of this structure reference STI (shallow trench isolation); It is isolated that 2 bit lines of same unit are carried out physics, stops electric charge horizontal proliferation between the bit line.
Through specific embodiment the present invention is made the method for two bit line SONOS cellular constructions below and two bit line SONOS cellular constructions of made carry out detailed introduction and description; So that better understand the present invention, but following embodiment does not limit the scope of the invention.
Shown in Fig. 2 A, silicon oxide layer deposited 2, reservoir (silicon nitride layer) 3, barrier layer (silicon oxide layer) 4 and gate polysilicon layer 5 successively above silicon base 1 are prepared SONOS grid matrix.
Shown in Fig. 2 B, on said SONOS grid matrix, carry out photoresist coating and development, expose grid matrix mid portion, part to silicon base 1 upper surface that etching grid matrix exposes forms the groove 23 that runs through grid matrix two ends, and groove width is 70nm.
Remove remaining photoresist then.
Shown in Fig. 2 C, adopt ISSG technology, be the silica barrier layer 6 of 80A at the inner surface and residue grid body upper surface uniform deposition one layer thickness of groove 23.
Wherein, ISSG technology is known in the art technology, can be implemented according to existing knowledge by those skilled in the art.
Shown in Fig. 2 D, adopt HARP process deposits polysilicon 7, groove 23 is filled.
Wherein, HARP technology is known in the art technology, can be implemented according to existing knowledge by those skilled in the art.
Shown in Fig. 2 E; CMP technology planarization polysilicon gate; Utilize CMP technology to remove unnecessary silica barrier layer 6 and polysilicon 7, be in same plane to silica barrier layer 6 and polysilicon 7 upper surfaces and remaining polysilicon gate upper surface (being polysilicon 5 upper surfaces).
Wherein, CMP technology is state of the art, and polishing fluid and polishing condition can be selected according to existing knowledge by those skilled in the art.
Adopt prior art, carry out the photoresist coating, develop, and etching forms the SONOS polysilicon gate.
Shown in Fig. 2 A, silicon oxide layer deposited 2, reservoir (silicon nitride layer) 3, barrier layer (silicon oxide layer) 4 and gate polysilicon layer 5 successively above silicon base 1 are prepared SONOS grid matrix.
Shown in Fig. 2 B, on said SONOS grid matrix, carry out photoresist coating and development, expose grid matrix mid portion, part to silicon base 1 upper surface that etching grid matrix exposes forms the groove 23 that runs through grid matrix two ends, and groove width is 75nm.
Remove remaining photoresist then.
Shown in Fig. 2 C, adopt ISSG technology, be the silica barrier layer 6 of 150A at the inner surface and residue grid body upper surface uniform deposition one layer thickness of groove 23.
Wherein, ISSG technology is known in the art technology, can be implemented according to existing knowledge by those skilled in the art.
Shown in Fig. 2 D, adopt HARP process deposits polysilicon 7, groove 23 is filled.
Wherein, HARP technology is known in the art technology, can be implemented according to existing knowledge by those skilled in the art.
Shown in Fig. 2 E; CMP technology planarization polysilicon gate; Utilize CMP technology to remove unnecessary silica barrier layer 6 and polysilicon 7, be in same plane to silica barrier layer 6 and polysilicon 7 upper surfaces and remaining polysilicon gate upper surface (being polysilicon 5 upper surfaces).
Wherein, CMP technology is state of the art, and polishing fluid and polishing condition can be selected according to existing knowledge by those skilled in the art.
Adopt prior art, carry out the photoresist coating, develop, and etching forms the SONOS polysilicon gate.
Shown in Fig. 2 A, silicon oxide layer deposited 2, reservoir (silicon nitride layer) 3, barrier layer (silicon oxide layer) 4 and gate polysilicon layer 5 successively above silicon base 1 are prepared SONOS grid matrix.
Shown in Fig. 2 B, on said SONOS grid matrix, carry out photoresist coating and development, expose grid matrix mid portion, part to silicon base 1 upper surface that etching grid matrix exposes forms the groove 23 that runs through grid matrix two ends, and groove width is 80nm.
Remove remaining photoresist then.
Shown in Fig. 2 C, adopt ISSG technology, be the silica barrier layer 6 of 200A at the inner surface and residue grid body upper surface uniform deposition one layer thickness of groove 23.
Wherein, ISSG technology is known in the art technology, can be implemented according to existing knowledge by those skilled in the art.
Shown in Fig. 2 D, adopt HARP process deposits polysilicon 7, groove 23 is filled.
Wherein, HARP technology is known in the art technology, can be implemented according to existing knowledge by those skilled in the art.
Shown in Fig. 2 E; CMP technology planarization polysilicon gate; Utilize CMP technology to remove unnecessary silica barrier layer 6 and polysilicon 7, be in same plane to silica barrier layer 6 and polysilicon 7 upper surfaces and remaining polysilicon gate upper surface (being polysilicon 5 upper surfaces).
Wherein, CMP technology is state of the art, and polishing fluid and polishing condition can be selected according to existing knowledge by those skilled in the art.
Adopt prior art, carry out the photoresist coating, develop, and etching forms the SONOS polysilicon gate.
With reference to Fig. 3, two bit line SONOS unit of the above embodiment of the present invention preparation comprises silicon base 1, and left grid 22 and 21, two grids of right grid are positioned at the upper surface of silicon base 1, and is isolated through grooves 23 in the middle of two grids.Silicon base 1 is provided with source end ion implanted region 11 and 12, two ion implanted regions of drain terminal ion implanted region and lays respectively at the opposing side of two grids and groove 23.
Be filled with polysilicon 7 in the groove 23.
On the basis of embodiment 4, in the groove of the two bit line SONOS unit of the present invention, also be filled with silica barrier layer 6, silica barrier layer 6 between polysilicon 7 grooves 23 inwalls, in other words conj.or perhaps polysilicon 7 and two grids and and silicon base 1 between.
According to the description of the foregoing description, those skilled in the art can know that the width of the groove 23 of the two bit line SONOS unit of the present invention is 70 ~ 80nm, and the thickness of silica barrier layer 6 is 80 ~ 200A.
Two bit line SONOS unit of the present invention's preparation, the characteristic line breadth of polysilicon gate is 50 ~ 350nm.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (10)
1. the manufacture method of novel two bit line SONOS cellular constructions is characterized in that step comprises:
Step 1, silicon oxide layer deposited, reservoir, barrier layer and gate polysilicon layer successively above silicon base are prepared SONOS grid matrix;
Step 2 is carried out photoresist coating and development on said SONOS grid matrix, expose grid matrix mid portion, and the part that etching grid matrix exposes forms the groove that runs through grid matrix two ends to silicon base, removes remaining photoresist;
Step 3 is on said grooved inner surface and residue grid body upper surface cvd silicon oxide barrier layer;
Step 4, deposit spathic silicon is filled groove;
Step 5; In the polysilicon of removing deposition in the step 4 and the step 3 the cvd silicon oxide barrier layer to residue grid body upper surface, cvd silicon oxide barrier layer upper surface and remain the grid body upper surface and be in the same plane in the polysilicon that makes deposition in the step 4 and the step 3;
Step 6 is carried out photoresist coating, development and etching at residue grid body upper surface and is formed the SONOS polysilicon gate.
2. method according to claim 1 is characterized in that, said groove width is 70 ~ 80nm.
3. method according to claim 1 is characterized in that, the barrier layer thickness of cvd silicon oxide described in the step 3 is 80 ~ 200A.
4. method according to claim 1 is characterized in that, the deposition process of silica barrier layer described in the step 3 adopts original position steam to generate technology.
5. method according to claim 1 is characterized in that, the method for polysilicon deposition described in the step 4 adopts high depth ratio to fill out ditch technology.
6. two bit line SONOS cellular constructions of making of the method for claim 1; It is characterized in that; Comprise silicon base and two grids that are positioned at said silicon base upper surface, said two grids are followed successively by oxide layer, reservoir, barrier layer and polysilicon layer from the bottom to top; Through trench isolations, be filled with polysilicon in the said groove between said two grids; Do not have ion implanted region between said two grids, said silicon base in two grid outsides partly is respectively the ion implanted region of source end and drain terminal.
7. SONOS cellular construction according to claim 6 is characterized in that, contains one deck silicon oxide layer between polysilicon of filling in the said groove and the said trench wall.
8. SONOS cellular construction according to claim 7 is characterized in that, the polysilicon and the silicon oxide layer thickness between the trench wall of filling in the said groove are 80 ~ 200A.
9. SONOS cellular construction according to claim 6 is characterized in that, said groove width is 70 ~ 80nm.
10. SONOS cellular construction according to claim 6 is characterized in that, said feature sizes of grids is 50 ~ 350nm.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7511334B2 (en) * | 2003-04-01 | 2009-03-31 | Samsung Electronics Co., Ltd. | Twin-ONO-type SONOS memory |
| US20090166716A1 (en) * | 2007-12-27 | 2009-07-02 | Cheol-Soo Jo | Semiconductor device and method for manufacturing the same |
| CN101872767A (en) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | Silicon nitride trap layer olive-shaped energy band gap structure and manufacturing method thereof of SONOS (Silicon Oxide Nitride Oxide Semiconductor) component |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7511334B2 (en) * | 2003-04-01 | 2009-03-31 | Samsung Electronics Co., Ltd. | Twin-ONO-type SONOS memory |
| US20090166716A1 (en) * | 2007-12-27 | 2009-07-02 | Cheol-Soo Jo | Semiconductor device and method for manufacturing the same |
| CN101872767A (en) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | Silicon nitride trap layer olive-shaped energy band gap structure and manufacturing method thereof of SONOS (Silicon Oxide Nitride Oxide Semiconductor) component |
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