CN102468127A - Method for cleaning wafer in double polycrystalline capacitance process - Google Patents
Method for cleaning wafer in double polycrystalline capacitance process Download PDFInfo
- Publication number
- CN102468127A CN102468127A CN2010105346648A CN201010534664A CN102468127A CN 102468127 A CN102468127 A CN 102468127A CN 2010105346648 A CN2010105346648 A CN 2010105346648A CN 201010534664 A CN201010534664 A CN 201010534664A CN 102468127 A CN102468127 A CN 102468127A
- Authority
- CN
- China
- Prior art keywords
- wafer
- hydrofluoric acid
- polysilicon
- electric capacity
- ground floor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The embodiment of the invention discloses a method for cleaning a wafer in a double polycrystalline capacitance process, which is used for solving the problems of big difference among capacitance values at different positions of the wafer and low capacitance uniformity in the conventional double polycrystalline capacitance process. The method comprises the step of cleaning the wafer by using sulfuric acid hydrogen peroxide, ammonia hydrogen peroxide and hydrofluoric acid respectively after growing a first layer of polycrystalline silicon on the wafer and before growing an insulating dielectric layer on the first layer of polycrystalline silicon. By the method provided by the embodiment of the invention, silicon oxide on the surface of the first layer of polycrystalline silicon can be cleaned; the contacting property of the first layer of polycrystalline silicon and the insulating dielectric layer is improved; difference among the capacitance values at different positions of the wafer is reduced; and the capacitance uniformity is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly the method for cleaning wafer in a kind of pair of polycrystalline electric capacity technology.
Background technology
In technical field of semiconductors, two polycrystalline electric capacity are meant the use pair electric capacity that the polycrystalline technology is produced, and it is owing to the precision height and be easy to manufacturing, uses more and more widely.
Referring to Fig. 1, make in the technical process of two polycrystalline electric capacity at present, comprise the following step:
Referring to Fig. 2, in the structural representation of two polycrystalline electric capacity, length has insulating medium layer 203 between ground floor polysilicon 201 and the second layer polysilicon 202.
Using two polycrystalline technology to produce in the technology of electric capacity, the electric capacity uniformity is an important parameter, and it plays a part very crucial to the application of product.Specifically, the electric capacity uniformity just is meant the difference of the capacitance of diverse location on the wafer.Difference is more little, explains that uniformity is good more.Therefore, after all technologies of two polycrystalline electric capacity are accomplished, the electric capacity uniformity on the meeting test wafer.But present the differing greatly of diverse location capacitance on the wafer of two polycrystalline electric capacity, the electric capacity uniformity is relatively poor, and restriction has been played in the application of two polycrystalline electric capacity products.
In sum, the differing greatly of diverse location capacitance on the wafer of existing two polycrystalline electric capacity, the electric capacity uniformity is relatively poor.
Summary of the invention
The embodiment of the invention provide a kind of in two polycrystalline electric capacity technologies the method for cleaning wafer, differ greatly the problem that the electric capacity uniformity is relatively poor in order to diverse location capacitance on the wafer that solves existing two polycrystalline electric capacity.
Provided by the invention a kind of in two polycrystalline electric capacity technologies the method for cleaning wafer, comprising:
On wafer after growth regulation one deck polysilicon, and before growth insulating medium layer on the ground floor polysilicon, use dioxysulfate water, ammoniacal liquor hydrogen peroxide solution and hydrofluoric acid clean wafer respectively.
Said silica with ground floor polysilicon surface on the hydrofluoric acid clean wafer.
The reaction equation of said use hydrofluoric acid clean wafer is:
4HF+SiO
2＝SiF
4+2H
2O；
Wherein, HF representes hydrofluoric acid, SiO
2The expression silica, H
2O representes water.
Said hydrofluoric acid is the hydrofluoric acid after diluting.
The thinner ratio of the hydrofluoric acid after the said dilution is 1: 40～1: 60.
The time of said use hydrofluoric acid clean wafer is 10 seconds～30 seconds.
Saidly carrying out after two ammoniacal liquor cleaning wafers with dioxysulfate water and ammoniacal liquor with the hydrofluoric acid clean wafer.
Saidly comprise with the hydrofluoric acid clean wafer:
Wafer is put into the groove that fills hydrofluoric acid to be soaked.
The polysilicon of said ground floor polysilicon for mixing.
Said ground floor polysilicon is the bottom crown of two polycrystalline electric capacity;
The second layer polysilicon of growth is the top crown of two polycrystalline electric capacity after insulating medium layer.
Because before growth insulating medium layer on the ground floor polysilicon; With hydrofluoric acid (HF) cleaning wafer; Can wash the silica of ground floor polysilicon surface off; Improve the contact performance of ground floor polysilicon and insulating medium layer, reduced the difference of diverse location capacitance on the wafer, improved the electric capacity uniformity.
Description of drawings
Fig. 1 is the method sketch map of two polycrystalline electric capacity technologies in the background technology;
Fig. 2 is the structural representation of two polycrystalline electric capacity in the background technology;
Fig. 3 is a method sketch map of producing two polycrystalline electric capacity in the embodiment of the invention.
Embodiment
The inventor through analyzing, thought before growth insulating medium layer on the ground floor polysilicon of wafer in the invention process; The ground floor polysilicon maybe be oxidized in air on the wafer, formed silica, and traditional cleaning step; Use dioxysulfate water and ammoniacal liquor hydrogen peroxide solution to clean; Mainly be acidity and the alkaline organic on the cleaning wafer, can not remove the silica on polysilicon handle wafer surface, thereby influenced the contact performance of ground floor polysilicon and insulating medium layer.Simultaneously, because the silica that the ground floor polysilicon surface forms and inhomogeneous also will have influence on the electric capacity uniformity.Therefore, the inventor considers before growth insulating medium layer on the ground floor polysilicon, to use the HF cleaning wafer, to wash the silica of ground floor polysilicon surface on the wafer off.Experimental result shows that after two polycrystalline electric capacity technologies were accomplished, the difference that records diverse location capacitance on the wafer diminished, and the electric capacity uniformity is obviously improved.
Below in conjunction with Figure of description the embodiment of the invention is described in further detail.
Referring to Fig. 3, the embodiment of the invention provides a kind of process of producing two polycrystalline electric capacity, comprises the steps:
Step 301, on wafer, form the ground floor polysilicon.
Wherein, the ground floor polysilicon is as the bottom crown of electric capacity.The ground floor polysilicon can be the DOPOS doped polycrystalline silicon of P type or N type.
General, the thickness of ground floor polysilicon is at 1800A.
Step 302, with dioxysulfate water cleaning wafer.
Wherein, dioxysulfate water mainly is the alkaline organic that washes ground floor polysilicon surface on the wafer.
In the enforcement, can wafer be put into the groove that fills dioxysulfate water and soak certain hour.
Preferable, each components in proportions is following in the dioxysulfate water of use:
Sulfuric acid (H
2SO
4): hydrogen peroxide solution (H
2O
2): water (H
2O)=1: 1: 5, wafer was soaked 180 seconds, can effectively remove the alkaline organic of polysilicon surface.
Step 303, with ammoniacal liquor hydrogen peroxide solution cleaning wafer.
Wherein, the ammoniacal liquor hydrogen peroxide solution mainly is the acid organic substance that washes ground floor polysilicon surface on the wafer.
In the enforcement, can wafer be put into the groove that fills the ammoniacal liquor hydrogen peroxide solution and soak certain hour.
Preferable, each components in proportions is following in the ammoniacal liquor hydrogen peroxide solution of use:
Ammoniacal liquor hydrogen peroxide solution (NH
4OH): hydrogen peroxide solution (H
2O
2): water (H
2O)=1: 2: 10, wafer was soaked 180 seconds, can effectively remove the acid organic substance of polysilicon surface.
Step 304, use the hydrofluoric acid clean wafer.
Wherein, hydrofluoric acid (HF) is with the silica (SiO of ground floor polysilicon surface on the wafer
2) react, therefore can wash the silica of polysilicon surface off.Reaction equation is following:
4HF+SiO
2=SiF4+2H
2O........... reaction equation 1.
In the enforcement, can wafer be put into the groove that fills hydrofluoric acid and soak certain hour.
Because hydrofluoric acid that pure hydrofluoric acid or concentration are big and silica reaction are too fast, are unfavorable for controlling course of reaction, the hydrofluoric acid clean wafer after the therefore general use dilution.
Preferable, the thinner ratio of hydrofluoric acid (hydrofluoric acid: water) be 1: 40～1: 60, wafer is immersed in the hydrofluoric acid 10～30 seconds, can effectively remove the silica of polysilicon surface.
The time that wafer soaks in hydrofluoric acid is also unsuitable long, otherwise meeting excessive corrosion wafer, the properties of product of the two polycrystalline electric capacity of influence.
Step 305, growth insulating medium layer.
Wherein, insulating medium layer mainly plays between ground floor polysilicon and second layer polysilicon and plays the dielectric effect.Insulating medium layer can be siliceous oxide-based, the general tetraethoxysilane that under low pressure forms that adopts.
Step 306, formation second layer polysilicon.
Wherein, second layer polysilicon is as the top crown of electric capacity.Second layer polysilicon can be the DOPOS doped polycrystalline silicon of P type or N type.
General, the thickness of second layer polysilicon is at 2200A.
In the present embodiment; Step 302～step 304 is the corresponding step of method of cleaning wafer; But step 302, step 303, step 304 are not limited to above-mentioned execution sequence; The order of these three steps can be arranged arbitrarily, such as: can carry out according to the order of step 303 → step 302 → step 304, also can carry out according to step 304 → step 302 → step 303 order.
Preferable, carry out according to the order of step 302 → step 303 → step 304, it is less to the change of background technology to compare other orders, implements to be easier to.
The method that adopts present embodiment to provide; Can effectively improve the electric capacity uniformity; Such as: adopt in the prior art only with dioxysulfate water and ammoniacal liquor hydrogen peroxide solution cleaning wafer, the electric capacity uniformity is 1.9%, provide in the employing embodiment of the invention with behind dioxysulfate water, ammoniacal liquor hydrogen peroxide solution, the hydrofluoric acid clean wafer; The uniformity of electric capacity is improved to 0.5%, improvement rate about 75%.
Although described the preferred embodiments of the present invention, in a single day those skilled in the art get the basic inventive concept could of cicada, then can make other change and modification to these embodiment.So accompanying claims is intended to be interpreted as all changes and the modification that comprises preferred embodiment and fall into the scope of the invention.
Because the embodiment of the invention is on wafer after growth regulation one deck polysilicon; And before growth insulating medium layer on the ground floor polysilicon,, also use the hydrofluoric acid clean wafer except using dioxysulfate water, ammoniacal liquor hydrogen peroxide solution cleaning wafer respectively; Therefore can wash the silica of ground floor polysilicon surface off; Improve the contact performance of ground floor polysilicon and insulating medium layer, reduced the difference of diverse location capacitance on the wafer, improved the electric capacity uniformity.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the method for cleaning wafer in two polycrystalline electric capacity technologies is characterized in that this method comprises:
On wafer after growth regulation one deck polysilicon, and before growth insulating medium layer on the ground floor polysilicon, use dioxysulfate water, ammoniacal liquor hydrogen peroxide solution and hydrofluoric acid clean wafer respectively.
2. the method for claim 1 is characterized in that, said silica with ground floor polysilicon surface on the hydrofluoric acid clean wafer.
3. method as claimed in claim 2 is characterized in that, the reaction equation of said use hydrofluoric acid clean wafer is:
4HF+SiO
2＝SiF
4+2H
2O；
Wherein, HF representes hydrofluoric acid, SiO
2The expression silica, H
2O representes water.
4. the method for claim 1 is characterized in that, said hydrofluoric acid is the hydrofluoric acid after diluting.
5. method as claimed in claim 4 is characterized in that, the thinner ratio of the hydrofluoric acid after the said dilution is 1: 40～1: 60.
6. method as claimed in claim 5 is characterized in that, the time of said use hydrofluoric acid clean wafer is 10 seconds～30 seconds.
7. like the arbitrary described method of claim 1-5, it is characterized in that, saidly carrying out after two ammoniacal liquor cleaning wafers with dioxysulfate water and ammoniacal liquor with the hydrofluoric acid clean wafer.
8. like the arbitrary described method of claim 1-5, it is characterized in that, saidly comprise with the hydrofluoric acid clean wafer:
Wafer is put into the groove that fills hydrofluoric acid to be soaked.
9. like the arbitrary described method of claim 1-5, it is characterized in that the polysilicon of said ground floor polysilicon for mixing.
10. like the arbitrary described method of claim 1-5, it is characterized in that said ground floor polysilicon is the bottom crown of two polycrystalline electric capacity;
The second layer polysilicon of growth is the top crown of two polycrystalline electric capacity after insulating medium layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105346648A CN102468127A (en) | 2010-11-03 | 2010-11-03 | Method for cleaning wafer in double polycrystalline capacitance process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105346648A CN102468127A (en) | 2010-11-03 | 2010-11-03 | Method for cleaning wafer in double polycrystalline capacitance process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102468127A true CN102468127A (en) | 2012-05-23 |
Family
ID=46071617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105346648A Pending CN102468127A (en) | 2010-11-03 | 2010-11-03 | Method for cleaning wafer in double polycrystalline capacitance process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102468127A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103480598A (en) * | 2012-06-15 | 2014-01-01 | 无锡尚德太阳能电力有限公司 | Silicon wafer cleaning method for preparing high-efficiency solar cell and cleaning equipment |
| CN104253016A (en) * | 2013-06-26 | 2014-12-31 | 北大方正集团有限公司 | Method for improving productive capacity of high-ohmic resistor |
| CN106373874A (en) * | 2015-07-21 | 2017-02-01 | 北大方正集团有限公司 | Manufacturing method of ohmic contact electrode based on AlGaN/GaN HEMT |
| CN111584342A (en) * | 2020-05-07 | 2020-08-25 | 如皋市协创能源科技有限公司 | Method for cleaning element in double-polycrystal capacitor process |
| CN112103179A (en) * | 2020-11-03 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Manufacturing method of MIM capacitor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
| US20030040162A1 (en) * | 2001-08-24 | 2003-02-27 | Hynix Semiconductor Inc. | Method for fabricating a capacitor |
| US20070072431A1 (en) * | 2005-09-28 | 2007-03-29 | Chang-Sup Mun | Method for cleaning substrate having exposed silicon and silicon germanium layers and related method for fabricating semiconductor device |
| CN101017772A (en) * | 2007-02-27 | 2007-08-15 | 江苏佳讯电子有限公司 | The cleaning method for removing the impure ion from the semiconductor pipe core assembly |
| CN101339900A (en) * | 2007-07-02 | 2009-01-07 | 旺宏电子股份有限公司 | Method for surface modification of semiconductor layer and method of manufacturing semiconductor device |
-
2010
- 2010-11-03 CN CN2010105346648A patent/CN102468127A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
| US20030040162A1 (en) * | 2001-08-24 | 2003-02-27 | Hynix Semiconductor Inc. | Method for fabricating a capacitor |
| US20070072431A1 (en) * | 2005-09-28 | 2007-03-29 | Chang-Sup Mun | Method for cleaning substrate having exposed silicon and silicon germanium layers and related method for fabricating semiconductor device |
| CN101017772A (en) * | 2007-02-27 | 2007-08-15 | 江苏佳讯电子有限公司 | The cleaning method for removing the impure ion from the semiconductor pipe core assembly |
| CN101339900A (en) * | 2007-07-02 | 2009-01-07 | 旺宏电子股份有限公司 | Method for surface modification of semiconductor layer and method of manufacturing semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103480598A (en) * | 2012-06-15 | 2014-01-01 | 无锡尚德太阳能电力有限公司 | Silicon wafer cleaning method for preparing high-efficiency solar cell and cleaning equipment |
| CN104253016A (en) * | 2013-06-26 | 2014-12-31 | 北大方正集团有限公司 | Method for improving productive capacity of high-ohmic resistor |
| CN104253016B (en) * | 2013-06-26 | 2017-04-05 | 北大方正集团有限公司 | The method for improving high resistant production capacity |
| CN106373874A (en) * | 2015-07-21 | 2017-02-01 | 北大方正集团有限公司 | Manufacturing method of ohmic contact electrode based on AlGaN/GaN HEMT |
| CN111584342A (en) * | 2020-05-07 | 2020-08-25 | 如皋市协创能源科技有限公司 | Method for cleaning element in double-polycrystal capacitor process |
| CN112103179A (en) * | 2020-11-03 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Manufacturing method of MIM capacitor |
| CN112103179B (en) * | 2020-11-03 | 2021-03-02 | 晶芯成(北京)科技有限公司 | Manufacturing method of MIM capacitor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9117759B2 (en) | Methods of forming bulb-shaped trenches in silicon | |
| CN102468127A (en) | Method for cleaning wafer in double polycrystalline capacitance process | |
| CN102117761B (en) | Wet process method for improving chamfer smoothness on top of shallow trench isolation | |
| CN104505437A (en) | Texturing preprocessing solution and method of diamond wire cutting polycrystalline silicon wafer, texturing preprocessing silicon wafer and application of texturing preprocessing silicon wafer | |
| CN102468176B (en) | Method for making longitudinal region of super junction device | |
| CN105140114A (en) | Method for preparing substrate | |
| CN103208421B (en) | A kind of method improving silicon nitride layer and oxide layer etching selection ratio | |
| CN103681245A (en) | Method for cleaning germanium sheet and passivating surface of germanium sheet | |
| CN108091574A (en) | Mos field effect transistor and preparation method thereof | |
| CN102969232A (en) | Manufacture method of false gate of back gate process | |
| KR102049125B1 (en) | Method, apparatus, and composition for wet etching | |
| CN101252083B (en) | Method for cleaning polycrystalline silicon gate surface | |
| WO2014161463A1 (en) | Method for forming gate oxide layer of semiconductor device | |
| CN101847655B (en) | Trench grate capable of improving trench grate MOS device performance and manufacture method thereof | |
| CN102361007A (en) | Method for etching groove and semiconductor device | |
| CN105719972A (en) | Formation method of semiconductor structure | |
| CN104465367A (en) | Method and application for processing field oxide layer | |
| CN101800172B (en) | A kind of manufacture method of self-aligned polysilicon floating gate | |
| CN105702724B (en) | Semiconductor devices and forming method thereof | |
| CN102956456B (en) | A kind of manufacture method of semiconductor device | |
| CN102637586B (en) | Forming method of metal grid electrode | |
| TW200421491A (en) | Bottom oxide formation process for preventing formation of voids in the trench | |
| CN103117220B (en) | The minimizing technology of super junction sacrificial oxide layer | |
| US8524093B2 (en) | Method for forming a deep trench | |
| CN104392919B (en) | The processing method of the surface of silicon of nmos device and the preparation method of nmos device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120523 |