CN102468271A - Test structure of semiconductor technology and manufacture method thereof - Google Patents
Test structure of semiconductor technology and manufacture method thereof Download PDFInfo
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- CN102468271A CN102468271A CN2010105334392A CN201010533439A CN102468271A CN 102468271 A CN102468271 A CN 102468271A CN 2010105334392 A CN2010105334392 A CN 2010105334392A CN 201010533439 A CN201010533439 A CN 201010533439A CN 102468271 A CN102468271 A CN 102468271A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The invention discloses a test structure of semiconductor technology and a formation method thereof. The method comprises the following steps: providing a semiconductor substrate with a first area and a second area, wherein, the first area and the second area are separated by an isolation region; forming a first device on the first area and a second device on the second area respectively, wherein, the first device comprises a first metal gate and a first source-drain area, the second device comprises a second metal gate and a second source-drain area, and the first metal gate crosses the first area and partial isolation region and is connected with the second metal gate which crosses the second area and partial isolation region on the isolation region; carrying out a heat treatment on the structure so that a mutual diffusion or alloy reaction is generated at a connection part of the first metal gate and the second metal gate to form a composite region. Through testing the formed structure and detecting a transport factor, threshold voltage, reliability and the like of the structure, influence of the metal gates in a CMOS device caused by problems such as diffusion or interreaction in heat treatment technology on performance of the devices is detected.
Description
Technical field
The present invention relates generally to a kind of semiconductor structure and manufacturing approach thereof, specifically, relate to a kind of test structure and manufacturing approach thereof of semiconductor technology of high-k/metal gate.
Background technology
Reach with lower node along with integrated circuit fabrication process enters into 45nm, the application of high-k gate dielectric (high-k) material and metal gate electrode material has become inevitable.The introducing of high-k gate dielectric material can guarantee under the situation of equal EOT (Equivalent Oxide Thickness, equivalent oxide thickness), to increase the physical thickness of gate medium effectively, and this can make that tunnelling current is effectively suppressed.The introducing of metal gate electrode material can be avoided the problems such as boron atom diffusion, depletion of polysilicon and high resistance in traditional polygate electrodes.Yet, along with the introducing of high-k gate dielectric and metal gate electrode material, some challenging problems have also appearred, like the issue of inter-diffusion of metal gate electrode material.In cmos device with high-k gate dielectric and metal gate electrode material; In order to control the threshold voltage of nMOS device and pMOS device; Usually need to adopt the metal gate material of different materials; As adopting material TaC in the nMOS device, and adopt material MoAlN with high work function etc. in the pMOS device with low work function.In addition, can operate as normal in order to ensure MOS transistor at the active area edge, metal gate is beyond active area; Like STI (Shallow Trench Isolation; Shallow trench isolation leaves), an extension area must be arranged, and for some MOS device; Like the CMOS inverter, the extension of metal gate on STI of nMOS and pMOS device possibly directly contact.In certain Technology for Heating Processing; The situation that the last directly metal gate material of contact of STI counterdiffusion possibly take place or directly reacts; For large-size device, intermetallic counterdiffusion or reaction maybe be little to the electric property influence of device, but concerning small size device; Because reducing and the shortening of device pitch of cmos device size, diffusion between this metal gate material or reaction meeting exert an influence to the performance of adjacent devices.
Therefore, be necessary to design a kind of test structure and check the influence that metal gate material diffusion or reaction etc. cause device performance in the MOS device.
Summary of the invention
In view of the above problems, the invention provides a kind of formation method of test structure of semiconductor technology, said method comprises: A, the Semiconductor substrate with first area and second area is provided, said first area and second area are separated by isolated area; B, form second device on first device, the second area forming on the first area respectively; Said first device comprises first metal gate and source-drain area; Said second device comprises second metal gate and source-drain area, and wherein said first metal gate is connected on isolated area across first area and part isolated area and with second metal gate across second area and part isolated area; C, said structure is heat-treated, make said first metal gate and second metal gate contact part generation counterdiffusion or alloy reaction, to form the recombination region.
The present invention also provides a kind of test structure through said method formation semiconductor technology, and said structure comprises: have the Semiconductor substrate of first area and second area, said first area and second area are separated by isolated area; Be formed at first device on the said first area and be formed at second device on the said second area, said first device comprises first metal gate, and said second device comprises second metal gate; Wherein said first metal gate is positioned on first area and the part isolated area; Said second metal gate is positioned on second area and the part isolated area or said second metal gate is positioned on second area, part isolated area and part first metal gate; Said first metal gate is connected on isolated area with second metal gate, and comprises the recombination region of said first metal gate and second metal gate in the junction.
The present invention also provides the formation method of the test structure of another kind of semiconductor technology, and said method comprises: A, the Semiconductor substrate with isolated area is provided; B, on said substrate and isolated area, form insulating medium layer; And on said insulating medium layer, form the first metal gate material layer, and on the insulating medium layer of said isolated area or the second metal gate material layer that formation is connected with the said first metal gate material layer on the insulating medium layer of said isolated area and the part first metal gate material layer across said substrate and part isolated area; C, said structure is heat-treated, make the said first metal gate material layer be connected with the second metal gate material layer part generation counterdiffusion or alloy reaction, to form the recombination region.
The present invention also provides a kind of test structure through said method formation semiconductor technology, and said structure comprises: the Semiconductor substrate with isolated area; Be formed at the insulating medium layer on isolated area and the substrate; Be formed at the first metal gate material layer on the said insulating medium layer across said substrate and part isolated area; And be formed on the insulating medium layer of said isolated area or be formed at the second metal gate material layer on insulating medium layer and the part first metal gate material layer of said isolated area, that be connected with the said first metal gate material layer, and comprise the recombination region of the said first metal gate material layer and second metal gate material in the junction.
Through adopting manufacturing approach of the present invention; N type metal gates material is directly contacted with the extension of p type metal gates material on isolated area; And heat-treat; Structure through to such formation is tested, and detects mobility, threshold voltage and the reliability etc. of this structure, thus detect metal gate in the cmos device in Technology for Heating Processing owing to diffusion takes place or problem such as reacts to each other and influence that the performance of device is produced.
Description of drawings
Fig. 1-5 shows the structural representation according to the test structure of the semiconductor technology of the first embodiment of the present invention;
Fig. 6-9 shows the sketch map according to the structure of the test structure of the semiconductor technology of second embodiment of the invention.
Embodiment
The present invention relates generally to a kind of semiconductor device and manufacturing approach thereof.Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
The invention provides a plurality of embodiment, below will introduce semiconductor device and manufacturing approach thereof in detail according to the implementation method of different embodiment.
First embodiment
The formation method that below will introduce test structure in detail with NMOS and PMOS device with and structure.
At step S101, the Semiconductor substrate 200 with first area 200-1 and second area 200-2 is provided, said first area 200-1 and second area 200-2 are separated by isolated area 202, with reference to figure 1, Fig. 2 (AA ' of Fig. 1 is to view).In the present embodiment; Said substrate 200 has been carried out and has been handled operation early stage, and said processing is operated and comprised prerinse, forms well region and form isolated area 202, in the present embodiment; Said substrate 200 is a silicon substrate; In other embodiments, said substrate 200 can also comprise other compound semiconductors, like carborundum, GaAs, indium arsenide or indium phosphide.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 200 can comprise various doping configurations.In addition, preferably, said substrate 200 comprises epitaxial loayer, and said substrate 200 also can comprise silicon-on-insulator (SOI) structure.Said isolated area 202 can comprise that silicon dioxide or other can separate the material of the active area of semiconductor device.
At step S102; Forming formation second device on first device, the second area 200-2 on the 200-1 of first area respectively; Said first device comprises first metal gate 204 and first source-drain area 205; Said second device comprises second metal gate 206 and second source-drain area 207; Wherein said first metal gate 204 is connected on isolated area 202 across first area 200-1 and part isolated area 202 and with second metal gate 206 across second area 200-2 and part isolated area 202, with reference to figure 1, Fig. 2 (AA ' of Fig. 1 is to view) and Fig. 3, Fig. 4 (AA ' of Fig. 3 is to view).Said first device can be NMOS or PMOS, and then second device is the device of opposite types, i.e. PMOS or NMOS.
Specifically, at first, form gate dielectric layer 203, said gate dielectric layer can comprise SiO
2, SiON or high K medium material (for example, compare, have high dielectric constant materials) or other suitable dielectric materials with silica.Then; Form first metal gate 204 and second metal gate 206; In one embodiment; Form said first metal gate 204 and second metal gate, 206 concrete steps can comprise: on said device architecture, form first metal gate 204 earlier, graphical first metal gate 204 and remove second area 200-2 and part isolated area 202 on first metal gate 204, thereby formed first metal gate 204 across first area 200-1 and part isolated area 202; Then; On said device architecture, form second metal gate 206, graphical said second metal gate 206 is also removed second metal gate 206 on said first metal gate 204, is connected with second metal gate 206 through being in contact with one another on isolated area 202 with part isolated area 202 and with first metal gate 204 thereby formed across second area 200-2; With reference to figure 1, Fig. 2 (AA ' of Fig. 1 is to view), the scope of the length D of wherein said first metal gate or the part of second metal gate on said isolated area is 30nm-500nm.In another embodiment; Form said first metal gate 204 and second metal gate, 206 concrete steps can comprise: on said device architecture, form first metal gate 204 earlier; Graphical first metal gate 204 and remove second area 200-2 and part isolated area 202 on first metal gate 204; Thereby formed first metal gate 204, then, on said device architecture, formed second metal gate 206 across first area 200-1 and part isolated area 202; Graphical said second metal gate 206 is also removed part second metal gate 206 on said first metal gate 204; Thereby be formed on the isolated area 202 second metal gate 206 that the overlay region is arranged with first metal gate 204, said first metal gate 204 is connected on isolated area 202 through the overlay region with second metal gate 206, with reference to figure 3, Fig. 4 (AA ' of Fig. 3 is to view); The scope of the length D of wherein said first metal gate or the part of second metal gate on said isolated area is 30nm-500nm; The length L of said overlay region is not more than the length of the part of first metal gate on isolated area, can form the overlay region of different length as required, like Fig. 4, shown in Figure 5.The metal that said first metal gate and second metal gate have opposite types, said metal comprise N type or P type metal, and the example of wherein said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination, the example of said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination.Then; Can be through transistor arrangement according to expectation; 200-1 forms first source-drain area 205 and second area 200-2 forms second source-drain area 207 to the first area to inject p type or n type alloy or impurity, can by comprise that photoetching, ion inject, the method for diffusion and/or other appropriate process form, and at the sidewall formation side wall 210 of said first metal gate 204 and second metal gate 206; Said side wall 208 can have one or more layers structure; Side wall 210 is a three-decker in the present embodiment, can be by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low K dielectrics material and combination thereof, and/or other suitable materials form; This only is an example, and the present invention is not limited thereto this.
S103; Said structure is heat-treated; Make said first metal gate 204 be connected with second metal gate 206 part generation counterdiffusion or alloy reaction, to form recombination region 214, with reference to figure 1, Fig. 2 (AA ' of Fig. 1 is to view) and Fig. 3, Fig. 4 (AA ' of Fig. 3 is to view).Can or utilize the annealing when forming source-drain area after source-drain area forms, said structure is carried out quick thermal annealing process, wherein said heat treated atmosphere comprises: N
2, H
2And mist, said heat treated temperature range is 400-1100 ℃, said heat treatment period scope is 1s-50min; In the embodiment of L=(1/2) * D, as shown in Figure 4, annealing temperature can be about 950 ℃; Annealing time is about 10s, and is in first metal gate and embodiment that second metal gate only contacts, as shown in Figure 2; Annealing temperature can be about 1050 ℃, and annealing time is about 10s, and this only is an example; The present invention is not limited to this, can select corresponding annealing conditions according to the length and the testing requirement of different overlay regions.
Then, can further process said device as required.For example, on said first metal gate and/or second metal gate, form contact 212, and on said source-drain area, form contact 212, this only is an example, and the present invention is not limited thereto this.
More than the formation method of test structure with NMOS and PMOS device has been carried out detailed description; Further; The present invention also provides the semi-conductor test structure that forms according to said method; With reference to figure 1, Fig. 2 (AA ' of Fig. 1 is to view) and Fig. 3, Fig. 4 (AA ' of Fig. 3 is to view), said structure comprises: have the Semiconductor substrate of first area 200-1 and second area 200-2, said first area 200-1 and second area 200-2 are separated by isolated area 202; Be formed at first device on the said first area 200-1 and be formed at second device on the said second area 200-2, said first device comprises first metal gate 204, and said second device comprises second metal gate 206; Wherein said first metal gate 204 is positioned on first area 200-1 and the part isolated area 202; Said second metal gate 206 is positioned on second area 200-2 and the part isolated area 202 or said second metal gate 206 is positioned on second area 200-2, part isolated area 202 and part first metal gate 204; Said first metal gate 204 is connected on isolated area 202 with second metal gate 206, and comprises the recombination region 214 of said first metal gate 204 and second metal gate 206 in the junction.Wherein alternatively, the metal that said first metal gate and second metal gate have opposite types, said metal comprise N type or P type metal, and the example of wherein said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination, the example of said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination.Said recombination region forms through the counterdiffusion or the alloy reaction of said first metal gate and second metal gate; The length range of said first metal gate or the part of second metal gate on said isolated area is 30nm-500nm, and wherein the length of second metal gate on said first metal gate is not more than the length of the part of first metal gate on isolated area.
More than the formation method and the structure thereof of test structure with NMOS and PMOS device have been carried out detailed description; Through metal gate with NMOS and PMOS device; Extension on STI directly contacts; And heat-treat; Structure through to such formation is tested, and detects mobility, threshold voltage and the reliability etc. of this structure, thus detect metal gate in the cmos device in Technology for Heating Processing owing to diffusion takes place or problem such as reacts to each other and influence that the performance of device is produced.
Second embodiment
Below will introduce second embodiment that the present invention has the semi-conductor test structure of MOSCAP structure in detail.
The aspect that below will be only be different from first embodiment with regard to second embodiment is set forth.The part of not describing will be understood that with first embodiment and has adopted identical step, method or technology to carry out, and therefore repeats no more at this.
At step S201, the Semiconductor substrate with isolated area is provided.With the first embodiment S101, repeat no more.
At step S202; On said substrate 200 and isolated area 202, form insulating medium layer 203, and on said insulating medium layer 203, form the first metal gate material layer 204 and the coupled second metal gate material layer 206 that connects across said substrate 200 and part isolated area 202.
Specifically, at first, form insulating medium layer 203, said insulating medium layer can comprise SiO
2, SiON or high K medium material (for example, compare, have high dielectric constant materials) or other suitable dielectric materials with silica.Then, be formed on the first and second metal gate material layers that join on the isolated area 202.In one embodiment; Form the said first metal gate material layer 204 and the second metal gate material layer, 206 concrete steps can comprise: on said structure, form the first metal gate material layer 204; Remove the part first metal gate material layer 204; Only on said substrate 200 and part isolated area 202, form the first metal gate material layer 204; Then, on isolated area 202, form the second metal gate material layer 206, first metal material layer 204 is connected on said isolated area 202 with second metal material layer 206; With reference to figure 6, Fig. 7 (AA ' of Fig. 6 is to view), the scope of the length D of wherein said first metal gate material layer or the part of the second metal gate material layer on said isolated area is 30nm-500nm.In another embodiment; Form the said first metal gate material layer 204 and the second metal gate material layer, 206 concrete steps can comprise: on said structure, form the first metal gate material layer 204; Remove the part first metal gate material layer 204; Only on said substrate 200 and part isolated area 202, form the first metal gate material layer 204; Then; On the insulating medium layer 203 of said isolated area 202 and the part first metal gate material layer 204, form second metal material layer 206, thereby be formed on the isolated area 202 the second metal gate material layer 206 that the overlay region is arranged with the first metal gate material layer 204, the said first metal gate material layer 204 is connected on isolated area through the overlay region with the second metal gate material layer 206; With reference to figure 8, Fig. 9 (AA ' of Fig. 8 is to view); The scope of the length D of wherein said first metal gate material layer or the part of the second metal gate material layer on said isolated area is 30nm-500nm, and the length L of said overlay region is not more than the length of the part of the first metal gate material layer on isolated area, can form the overlay region of different length as required.The metal that the said first metal gate material layer and the second metal gate material layer have opposite types, said metal comprise N type or P type metal, and the example of wherein said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination, the example of said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination, when the said first metal gate material layer is N type metal, form n type capacitive region, when the said first metal gate material layer is P type metal, form P type capacitive region.
S203 heat-treats said structure, makes the said first metal gate material layer 204 be connected with the second metal gate material layer 206 part generation counterdiffusion or alloy reaction, to form recombination region 214, with reference to figure 6-Fig. 9.Said step repeats no more with the first embodiment S103.
Then, can further process said device as required.For example, on said insulation material layer 203, form the liner 216 that is connected with the said first metal gate material layer 204.
More than the formation method of test structure with N type or P type MOSCAP structure has been carried out detailed description; Further; The present invention also provides the semi-conductor test structure that forms according to said method, comprises with reference to figure 6, Fig. 7 (AA ' of Fig. 6 is to view) with reference to figure 8, the said structure of Fig. 9 (AA ' of Fig. 8 is to view): the Semiconductor substrate 200 with isolated area 202; Be formed at the insulating medium layer 203 on isolated area 202 and the substrate 200; Be formed at the first metal gate material layer 204 on the said insulating medium layer 203 across said substrate and part isolated area; And be formed on the insulating medium layer of said isolated area or be formed at the second metal gate material layer 206 on insulating medium layer 203 and the part first metal gate material layer 204 of said isolated area 202, that be connected with the said first metal gate material layer 204, and comprise the recombination region of the said first and second metal gate material layers in the junction.Wherein alternatively, the metal that the said first metal gate material layer and the second metal gate material layer have opposite types, said metal comprise N type or P type metal, and the example of said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination, the example of said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination.Said recombination region forms through the counterdiffusion or the alloy reaction of the said first metal gate material layer and the second metal gate material layer.The length range of the part of the said first metal gate material layer on said isolated area is 30nm-500nm, and the length of the second metal gate material layer on the said first metal gate material layer is not more than the length of the part of the first metal gate material layer on isolated area.
Through adopting manufacturing approach of the present invention; N type metal gates material is directly contacted with the extension of p type metal gates material on isolated area; And heat-treat; Structure through to such formation is tested, and detects mobility, threshold voltage and the reliability etc. of this structure, thus detect metal gate in the cmos device in Technology for Heating Processing owing to diffusion takes place or problem such as reacts to each other and influence that the performance of device is produced.
Though specify about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and accompanying claims, can carry out various variations, replacement and modification to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (32)
1. the formation method of the test structure of a semiconductor technology, said method comprises:
A, the Semiconductor substrate with first area and second area is provided, said first area and second area are separated by isolated area;
B, form second device on first device, the second area forming on the first area respectively; Said first device comprises first metal gate and first source-drain area; Said second device comprises second metal gate and second source-drain area, and wherein said first metal gate is connected on isolated area across first area and part isolated area and with second metal gate across second area and part isolated area;
C, said structure is heat-treated, make said first metal gate be connected with second metal gate part generation counterdiffusion or alloy reaction, to form the recombination region.
2. method according to claim 1, wherein said step B comprises: on said device, form first metal gate, graphical said first metal gate and remove second area and the part isolated area on first metal gate; On said device, form second metal gate, graphical said second metal gate is also removed second metal gate on said first metal gate.
3. method according to claim 1, wherein said step B comprises: on said device, form first metal gate, graphical said first metal gate and remove second area and the part isolated area on first metal gate; On said device, form second metal gate, graphical said second metal gate is also removed part second metal gate on said first metal gate, to be formed on the isolated area second metal gate that the overlay region is arranged with first metal gate.
4. method according to claim 3, the length of wherein said overlay region is not more than the length of the part of first metal gate on isolated area.
5. method according to claim 1, the metal that wherein said first metal gate and second metal gate have opposite types, said metal comprise N type or P type metal.
6. method according to claim 5, wherein said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination.
7. method according to claim 5, wherein said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination.
8. method according to claim 1, wherein said heat treated temperature range is 400-1100 ℃, and said heat treatment period scope is 1s-50min, and said heat treated atmosphere comprises: N
2, H
2And mist.
9. method according to claim 1, the length range of wherein said first metal gate or the part of second metal gate on said isolated area is 30nm-500nm.
10. method according to claim 1 is also comprising behind the said step C: on said first metal gate and/or second metal gate, form contact, and on said source-drain area, form contact.
11. the test structure of a semiconductor technology, said structure comprises:
Semiconductor substrate with first area and second area, said first area and second area are separated by isolated area;
Be formed at first device on the said first area and be formed at second device on the said second area, said first device comprises first metal gate, and said second device comprises second metal gate;
Wherein said first metal gate is positioned on first area and the part isolated area; Said second metal gate is positioned on second area and the part isolated area or said second metal gate is positioned on second area, part isolated area and part first metal gate; Said first metal gate is connected on isolated area with second metal gate, and comprises the recombination region of said first metal gate and second metal gate in the junction.
12. structure according to claim 11, the metal that wherein said first metal gate and second metal gate have opposite types, said metal comprise N type or P type metal.
13. structure according to claim 12, wherein said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination.
14. structure according to claim 12, wherein said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination.
15. structure according to claim 11, wherein said recombination region forms through the counterdiffusion or the alloy reaction of said first metal gate and second metal gate.
16. structure according to claim 11, the length range of wherein said first metal gate or the part of second metal gate on said isolated area is 30nm-500nm.
17. structure according to claim 11, wherein the length of second metal gate on said first metal gate is not more than the length of the part of first metal gate on isolated area.
18. the formation method of the test structure of a semiconductor technology, said method comprises:
A, the Semiconductor substrate with isolated area is provided;
B, on said substrate and isolated area, form insulating medium layer; And on said insulating medium layer, form the first metal gate material layer, and on the insulating medium layer of said isolated area or the second metal gate material layer that formation is connected with the said first metal gate material layer on the insulating medium layer of said isolated area and the part first metal gate material layer across said substrate and part isolated area;
C, said structure is heat-treated, make the said first metal gate material layer be connected with the second metal gate material layer part generation counterdiffusion or alloy reaction, to form the recombination region.
19. method according to claim 18, the metal that the wherein said first metal gate material layer and the second metal gate material layer have opposite types, said metal comprise N type or P type metal.
20. method according to claim 19, wherein said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination.
21. method according to claim 19, wherein said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination.
22. method according to claim 18, wherein said heat treated temperature range is 400-1100 ℃, and said heat treatment period scope is 1s-50min, and said heat treated atmosphere comprises: N
2, H
2And mist.
23. method according to claim 18, the length range of the part of the wherein said first metal gate material layer on said isolated area is 30nm-500nm.
24. according to right 18 described methods, wherein the length of the second metal gate material layer on the said first metal gate material layer is not more than the length of the part of the first metal gate material layer on isolated area.
25. method according to claim 18 is also comprising behind the said step C: on said insulation material layer, form the liner that is connected with the said first metal gate material layer.
26. the test structure of a semiconductor technology, said structure comprises:
Semiconductor substrate with isolated area;
Be formed at the insulating medium layer on isolated area and the substrate;
Be formed at the first metal gate material layer on the said insulating medium layer across said substrate and part isolated area; And be formed on the insulating medium layer of said isolated area or be formed at the second metal gate material layer on insulating medium layer and the part first metal gate material layer of said isolated area, that be connected with the said first metal gate material layer, and comprise the recombination region of the said first and second metal gate material layers in the junction.
27. structure according to claim 26, the metal that the wherein said first metal gate material layer and the second metal gate material layer have opposite types, said metal comprise N type or P type metal.
28. structure according to claim 27, wherein said N type metal comprises: Hf, Zr, Ti, Ta, Al, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
xOr its combination.
29. structure according to claim 27, wherein said P type metal comprises: Ru, Pd, Pt, Ir, TaN
x, TiAlN, WCN, MoAlN, RuO
xOr its combination.
30. structure according to claim 26, wherein said recombination region forms through the counterdiffusion or the alloy reaction of the said first metal gate material layer and the second metal gate material layer.
31. structure according to claim 26, the length range of the part of the wherein said first metal gate material layer on said isolated area is 30nm-500nm.
32. according to right 26 described methods, wherein the length of the second metal gate material layer on the said first metal gate material layer is not more than the length of the part of the first metal gate material layer on isolated area.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425271A (en) * | 2013-08-27 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
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| CN1941376A (en) * | 2005-09-26 | 2007-04-04 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN101159269A (en) * | 2006-10-05 | 2008-04-09 | 国际商业机器公司 | Structure and method for creation of a transistor |
| US20080157215A1 (en) * | 2006-12-28 | 2008-07-03 | Toshiba America Electronic Components, Inc. | Inter-Diffusion Barrier Structures for Dopants in Gate Electrodes, and Method for Manufacturing |
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| US20040256679A1 (en) * | 2003-06-17 | 2004-12-23 | Hu Yongjun J. | Dual work function metal gates and method of forming |
| CN1941376A (en) * | 2005-09-26 | 2007-04-04 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN101159269A (en) * | 2006-10-05 | 2008-04-09 | 国际商业机器公司 | Structure and method for creation of a transistor |
| US20080157215A1 (en) * | 2006-12-28 | 2008-07-03 | Toshiba America Electronic Components, Inc. | Inter-Diffusion Barrier Structures for Dopants in Gate Electrodes, and Method for Manufacturing |
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