CN102468305A - Non-volatile memory and method for manufacturing same - Google Patents
Non-volatile memory and method for manufacturing same Download PDFInfo
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- CN102468305A CN102468305A CN2010105553436A CN201010555343A CN102468305A CN 102468305 A CN102468305 A CN 102468305A CN 2010105553436 A CN2010105553436 A CN 2010105553436A CN 201010555343 A CN201010555343 A CN 201010555343A CN 102468305 A CN102468305 A CN 102468305A
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Abstract
The invention relates to a non-volatile memory and a method for manufacturing the same. The non-volatile memory comprises a substrate, a grid structure, a first doped region, a second doped region and a pair of isolation structures, wherein the grid structure is configured on the substrate and comprises a charge storage structure, a grid and gap walls, the charge storage structure is configured on the substrate, the grid is configured on the charge storage structure, the gap walls are configured on the lateral walls of the grid and the charge storage structure, the first doped region and the second doped region are respectively configured in the substrate at the two sides of the charge storage structure and at least are positioned below the gas walls, the pair of isolation structures are respectively configured in the substrate at the two sides of the grid structure. The invention also provides a method for manufacturing the non-volatile memory. With the adoption of the non-volatile memory and the method for manufacturing the same, a second bit effect and programmed interference during operation of the non-volatile memory can be avoided.
Description
Technical field
The present invention relates to a kind of non-volatility memory (non-volatile memory) and manufacturing approach thereof, particularly relate to a kind of non-volatility memory and the manufacturing approach thereof that can avoid second bit effect (second bit effect) and sequencing to disturb (program disturbance).
Background technology
Therefore the advantage that the data that non-volatility memory owing to have deposits in also can not disappear after outage must possess this type of memory body in many electric equipment products, the normal running when keeping the electric equipment products start.Particularly, fast flash memory bank (flash memory) is owing to have and can repeatedly carry out the operations such as depositing in, read, wipe of data, so become a kind of memory cell of the extensive employing of PC and electronic equipment institute.
Nitride fast flash memory bank (nitride-based flash memory) is present common a kind of non-volatility memory.In the nitride fast flash memory bank, utilize the data that can store two bits by the charge-trapping structure (the ONO layer of promptly knowing) that oxide skin(coating)-nitride layer-oxide skin(coating) constituted.In general, the data of two bits can be stored in left side (being left bit) or right side (being right bit) of the nitride layer in the charge-trapping structure respectively
Yet, in the nitride fast flash memory bank, exist the second bit effect, promptly when left bit is carried out read operation, can receive the influence of right bit, maybe when right bit is carried out read operation, can receive the influence of left bit.In addition, along with the memory body size is dwindled gradually, the length of passage (channel) also shortens thereupon, causes the second bit effect more remarkable, thereby has influenced the operation window (operation window) and the element efficiency of memory body.In addition, because the memory body size is dwindled gradually, the spacing between each element also shortens thereupon, and therefore adjacent memory body also is easy to generate the problem that sequencing is disturbed when carrying out programming operations.
This shows that above-mentioned existing non-volatility memory obviously still has inconvenience and defective, and demands urgently further improving in product structure and use.In order to solve the problem of above-mentioned existence; Relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; But do not see always that for a long time suitable design is developed completion; And common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new non-volatility memory and manufacturing approach thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The objective of the invention is to; Overcome the defective that existing non-volatility memory exists; And a kind of new non-volatility memory, technical problem to be solved are provided is to make it can avoid when operation, producing the second bit effect and sequencing interference, is very suitable for practicality.
Another object of the present invention is to, a kind of manufacture method of new non-volatility memory is provided, technical problem to be solved is to make it can make the non-volatility memory with big operation window, thereby is suitable for practicality more.
The object of the invention and solve its technical problem and adopt following technical scheme to realize.According to a kind of non-volatility memory that the present invention proposes, it comprises substrate, grid structure, first doped region, second doped region and a pair of isolation structure.Grid structure is disposed in the substrate.Grid structure comprises charge storing structure, grid and clearance wall.Charge storing structure is disposed in the substrate.Gate configuration is on charge storing structure.Clearance wall is disposed on the sidewall of grid and charge storing structure.First doped region and second doped region are disposed at respectively in the substrate of charge storing structure two sides, and are positioned at the below of clearance wall at least.This is disposed at respectively in the substrate of grid structure two sides isolation structure.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid non-volatility memory, wherein said first doped region and second doped region are for example between this is to isolation structure, and this is to the degree of depth of the isolation structure degree of depth greater than first doped region and second doped region.
Aforesaid non-volatility memory, wherein said first doped region and second doped region for example center on this respectively to one in the isolation structure, and the degree of depth of first doped region and second doped region is greater than this degree of depth to isolation structure.
Aforesaid non-volatility memory, wherein said charge storing structure comprise first dielectric layer, electric charge storage layer and second dielectric layer.First dielectric layer is disposed in the substrate.Electric charge storage layer is disposed on first dielectric layer.Second dielectric layer is disposed on the electric charge storage layer.
Aforesaid non-volatility memory, the material of wherein said electric charge storage layer for example are nitride or high dielectric constant material.
Aforesaid non-volatility memory, wherein said grid structure comprise dielectric layer and control grid between tunneling dielectric layer, floating grid, grid.Tunneling dielectric layer is disposed in the substrate.Floating grid is disposed on the tunneling dielectric layer.Dielectric layer is disposed on the floating grid between grid.The control grid is disposed between grid on the dielectric layer.Clearance wall is disposed on the sidewall of dielectric layer between tunneling dielectric layer, floating grid, grid and control grid.
Aforesaid non-volatility memory, dielectric layer for example is the composite construction by oxide layer/nitration case/oxide layer constituted between wherein said grid.
The object of the invention and solve its technical problem and also adopt following technical scheme to realize.The manufacturing approach of a kind of non-volatility memory that proposes according to the present invention, the method is that substrate is provided earlier.Then, in substrate, form charge storing structure and grid.Then, on the sidewall of charge storing structure and grid, form clearance wall.Then, in the substrate of charge storing structure two sides, form doped region.In the substrate of grid and clearance wall two sides, form irrigation canals and ditches.Afterwards, in irrigation canals and ditches, form isolation structure.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
The manufacturing approach of aforesaid non-volatility memory, the degree of depth of wherein said irrigation canals and ditches are for example greater than the degree of depth of doped region.
The manufacturing approach of aforesaid non-volatility memory, wherein said doped region are for example around irrigation canals and ditches, and the degree of depth of doped region is greater than the degree of depth of irrigation canals and ditches.
The manufacturing approach of aforesaid non-volatility memory, the formation method of wherein said doped region for example is to carry out doping process.
The manufacturing approach of aforesaid non-volatility memory, the formation method of wherein said isolation structure for example are in substrate, to form insulation material layer earlier, and insulation material layer cover gate and clearance wall, and fill up irrigation canals and ditches.Then, carry out flatening process, remove the SI semi-insulation material layer, up to exposing grid.
The object of the invention and solve its technical problem and adopt following technical scheme to realize in addition again.According to a kind of non-volatility memory that the present invention proposes, it comprises substrate, two grid structures, doped region and isolation structures.Grid structure is disposed in the substrate.Each grid structure comprises charge storing structure and grid.Charge storing structure is disposed in the substrate.Gate configuration is on charge storing structure.Doped region is disposed in the substrate and between two grid structures.In the isolation structure configuration doped region.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid non-volatility memory, the degree of depth of wherein said isolation structure are for example greater than the degree of depth of doped region.
Aforesaid non-volatility memory, the degree of depth of wherein said doped region are for example greater than the degree of depth of isolation structure.
Aforesaid non-volatility memory, wherein said grid structure comprise dielectric layer and control grid between tunneling dielectric layer, floating grid, grid.Tunneling dielectric layer is disposed in the substrate.Floating grid is disposed on the tunneling dielectric layer.Dielectric layer is disposed on the floating grid between grid.The control grid is disposed between grid on the dielectric layer.
Aforesaid non-volatility memory, wherein said each grid structure also comprise the clearance wall on the sidewall that is disposed at dielectric layer between tunneling dielectric layer, floating grid, grid and control grid.
Aforesaid non-volatility memory, wherein said each grid structure also comprises the clearance wall on the sidewall that is disposed at grid and charge storing structure.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, non-volatility memory of the present invention and manufacturing approach thereof have advantage and beneficial effect at least:
The present invention serve as cover act with grid and clearance wall, so after admixture was implanted in the substrate, clearance wall can be used as the buffering area of dopant diffusion when the doped region that forms as source area and drain region.Some dopant diffusion to clearance wall below; And can only not diffuse to the below of charge storing structure; Therefore can avoid the length (being the passage length of memory body) between source area and the drain region to shorten effectively, and then avoid the second bit effect that produced when memory body operated.
In addition, therefore the present invention when non-volatility memory is carried out programming operations, can avoid the problem of sequencing interference effectively because isolation structure is disposed in the substrate of grid structure two sides.
In sum, the invention relates to a kind of non-volatility memory and manufacturing approach thereof.This non-volatility memory comprises substrate, grid structure, first doped region, second doped region and a pair of isolation structure.Grid structure is disposed in the substrate.Grid structure comprises charge storing structure, grid and clearance wall.Charge storing structure is disposed in the substrate.Gate configuration is on charge storing structure.Clearance wall is disposed on the sidewall of grid and charge storing structure.First doped region and second doped region are disposed at respectively in the substrate of charge storing structure two sides, and are positioned at the below of clearance wall at least.This is disposed at respectively in the substrate of grid structure two sides isolation structure.The present invention also provides a kind of manufacturing approach of non-volatility memory.The present invention can avoid non-volatility memory when operation, to produce the second bit effect and sequencing interference by this.The present invention has obvious improvement technically, and has tangible good effect, really is the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of specification, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process profile according to the non-volatility memory that one embodiment of the invention illustrated.
Fig. 2 A to Fig. 2 D is the manufacturing process profile according to the non-volatility memory that another embodiment of the present invention illustrated.
Fig. 3 is the generalized section according to the non-volatility memory that another embodiment of the present invention illustrated.
Fig. 4 is the generalized section according to the non-volatility memory that further embodiment of this invention illustrated.
10,20: non-volatility memory 100: substrate
102: grid structure 104: charge storing structure
104a, 104c: dielectric layer 104b: electric charge storage layer
106: grid 108: clearance wall
110,112,110a, 110b, 112a, 112b: doped region
114,200: irrigation canals and ditches 116,202: isolation structure
300: tunneling dielectric layer 302: floating grid
304: dielectric layer 306 between grid: the control grid
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To non-volatility memory and its embodiment of manufacturing approach, structure, method, step, characteristic and the effect thereof that proposes according to the present invention, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to appear in the following detailed description that cooperates with reference to graphic preferred embodiment.Through the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to obtain one more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.
Figure 1A to Fig. 1 D is the manufacturing process profile according to the non-volatility memory that one embodiment of the invention illustrated.At first, see also shown in Figure 1A, substrate 100 is provided.Substrate 100 is for example for having silicon (silicon on insulator, SOI) substrate on silicon base or the insulating barrier.Then, in substrate 100, form charge storing structure 104 and grid 106 in regular turn.Charge storing structure 104 is the composite constructions that are made up of dielectric layer 104a, electric charge storage layer 104b and dielectric layer 104c.The material of dielectric layer 104a, 104c for example is an oxide, and the material of electric charge storage layer 104b for example is nitride or high dielectric constant material (HfO for example
2, TiO
2, ZrO
2, Ta
2O
5Or Al
2O
3).Dielectric layer 104a is as tunneling dielectric layer, and dielectric layer 104c is as electric charge barrier layer.The material of grid 106 for example is a DOPOS doped polycrystalline silicon.Charge storing structure 104 for example is in substrate 100, to deposit earlier ground floor dielectric materials layer, charge storage material layer, second layer dielectric materials layer and gate material layers in regular turn with the formation method of grid 106.Then, carry out Patternized technique, with gate material layers, second layer dielectric materials layer, charge storage material layer and ground floor dielectric material patterned.
Then, see also shown in Figure 1B, on the sidewall of charge storing structure 104 and grid 106, form clearance wall 108.The formation method of clearance wall 108 for example be earlier in substrate 100 conformally (conformally) form the spacer material layer.Then, carry out anisotropic etch process, remove part spacer material layer.The material of clearance wall 108 for example is oxide, nitride or its combination.Charge storing structure 104, grid 106 constitute grid structure 102 with clearance wall 108.Afterwards, in the substrate 100 of charge storing structure 104 2 sides, form doped region 110,112.The formation method of doped region 110,112 for example is serve as the cover curtain with grid 106 and clearance wall 108, carries out doping process, with in required admixture (dopant) the implantation substrate 100., admixture can produce diffusion phenomena after being implanted in the substrate 100.In the present embodiment, owing to be formed with clearance wall 108 on the sidewall of charge storing structure 104 and grid 106, serve as after the cover curtain implantation admixture therefore with grid 106 and clearance wall 108, clearance wall 108 can be used as the buffering area of dopant diffusion.Admixture in the substrate 100 can't diffuse to the below of charge storing structure 104 in large quantities, but diffuses to the below of clearance wall 108, or seldom partly diffuses to the below of charge storing structure 104.That is to say that formed doped region 110, the distance between 112 (being the passage length of memory body) can't therefore and significantly shorten, and then produce the second bit effect can avoid memory body operated the time.
Then, see also shown in Fig. 1 C, in the substrate 100 of grid 106 and clearance wall 108 2 sides, form irrigation canals and ditches 114.The formation method of irrigation canals and ditches 114 for example is serve as cover act with grid 106 and clearance wall 108, carries out anisotropic etch process, to remove part substrate 100.The degree of depth of irrigation canals and ditches 114 is greater than the degree of depth of doped region 110,112.In the process that removes part substrate 100, the doped region 110,112 of part also can be removed simultaneously, and retains doped region 110a, the 112a that is positioned at clearance wall 108 belows.
Afterwards, see also shown in Fig. 1 D, in irrigation canals and ditches 114, form isolation structure 116, to process non-volatility memory 10.The formation method of isolation structure 116 for example is in substrate 100, to form insulation material layer earlier, and insulation material layer cover gate 106 and clearance wall 108, and fills up irrigation canals and ditches 114.Then, carry out flatening process, remove the SI semi-insulation material layer, up to exposing grid 106.
In the present embodiment, because isolation structure 116 is formed at respectively in the substrate of grid structure 102 2 sides, therefore when non-volatility memory 10 is carried out programming operations, can avoid the problem of sequencing interference effectively.
To be example below, the non-volatility memory of present embodiment will be explained with Fig. 1 D.
See also shown in Fig. 1 D, non-volatility memory 10 comprises substrate 100, grid structure 102, doped region 110a, doped region 112a and a pair of isolation structure 116.Grid structure 102 is disposed in the substrate 100.Grid structure 102 comprises charge storing structure 104, grid 106 and clearance wall 108.Charge storing structure 104 is disposed in the substrate 100.Charge storing structure 104 comprises dielectric layer 104a, electric charge storage layer 104b and dielectric layer 104c.Dielectric layer 104a is disposed in the substrate 100, as tunneling dielectric layer.Electric charge storage layer 104b is disposed on the dielectric layer 104a, in order to store charge.Dielectric layer 104c is disposed on the electric charge storage layer 104b, as electric charge barrier layer.Grid 106 is disposed on the charge storing structure 104.Clearance wall 108 is disposed on the sidewall of grid 106 and charge storing structure 104.Doped region 110a and doped region 112a are disposed at respectively in the substrate 100 of charge storing structure 104 2 sides, and be positioned at clearance wall 108 under, and partly extend to the below of charge storing structure 104.Doped region 110a and doped region 112a are respectively as source area and drain region.Look actual conditions, doped region 110a and doped region 112a also can be respectively as drain region and source areas.Isolation structure 116 is disposed at respectively in the substrate 100 of grid structure 102 2 sides.Doped region 110a and doped region 112a are between isolation structure 116, and the degree of depth of isolation structure 116 is greater than the degree of depth of doped region 110a and doped region 112a.
In addition, in another embodiment, doped region 110a and doped region 112a also can only be positioned at the below of clearance wall 108.
Fig. 2 A to Fig. 2 D is the manufacturing process profile according to the non-volatility memory that another embodiment of the present invention illustrated.In the present embodiment, will represent with identical label, not describe separately at this with components identical among Figure 1A to Fig. 1 D.At first, see also shown in Fig. 2 A, in substrate 100, form charge storing structure 104 and grid 106 in regular turn.Charge storing structure 104 is the composite constructions that are made up of dielectric layer 104a, electric charge storage layer 104b and dielectric layer 104c.
Then, see also shown in Fig. 2 B, on the sidewall of charge storing structure 104 and grid 106, form clearance wall 108.Charge storing structure 104, grid 106 constitute grid structure 102 with clearance wall 108.Afterwards, in the substrate 100 of grid structure 102 2 sides, form irrigation canals and ditches 200.
Then, see also shown in Fig. 2 C, in the substrate 100 of charge storing structure 104 2 sides, form doped region 110b, 112b.The formation method of doped region 110b, 112b for example is serve as the cover curtain with grid 106 and clearance wall 108, carries out doping process, with sidewall and the bottom with required admixture implantation irrigation canals and ditches 200.Likewise, after admixture was implanted, clearance wall 108 can be used as the buffering area of dopant diffusion.The below of some dopant diffusion to the clearance wall 108 in the substrate 100, perhaps the admixture of few part also can diffuse to the below of charge storing structure 104.Therefore, the distance between formed doped region 110b, the 112b (being the passage length of memory body) can't therefore and significantly shorten, and then produces the second bit effect can avoid memory body operated the time.
Afterwards, see also shown in Fig. 2 D, in irrigation canals and ditches 200, form isolation structure 202, to process non-volatility memory 20.The formation method of isolation structure 200 for example is in substrate 100, to form insulation material layer earlier, and insulation material layer cover gate 106 and clearance wall 108, and fills up irrigation canals and ditches 200.Then, carry out flatening process, remove the SI semi-insulation material layer, up to exposing grid 106.
Likewise, in the present embodiment,, therefore when non-volatility memory 20 is carried out programming operations, can avoid the problem of sequencing interference effectively because isolation structure 202 is formed at respectively in the substrate of grid structure 102 2 sides.
To be example below, the non-volatility memory of present embodiment will be explained with Fig. 2 D.
See also shown in Fig. 2 D; Non-volatility memory 20 is with the difference of non-volatility memory 10: in non-volatility memory 10; Doped region 110a and doped region 112a are between isolation structure 116; And the degree of depth of isolation structure 116 is greater than the degree of depth of doped region 110a and doped region 112a; And in non-volatility memory 20, doped region 110b and doped region 112b center on an isolation structure 202 respectively, and the degree of depth of doped region 110b and doped region 112b is greater than the degree of depth of isolation structure 202.
Likewise, in another embodiment, doped region 110b and doped region 112b also can only be positioned at the below of clearance wall 108.
Special one what carry is that in above-mentioned each embodiment, charge storing structure 104 is the composite constructions that are made up of dielectric layer 104a, electric charge storage layer 104b and dielectric layer 104c.In other embodiments, also can look actual demand and change the structure of charge storing structure 104.
In addition, in another embodiment, above-mentioned grid structure also can be by dielectric layer between tunneling dielectric layer, floating grid, grid and the control structure that grid constituted.Like Fig. 3 and shown in Figure 4, Fig. 3 is the generalized section according to the non-volatility memory that another embodiment of the present invention illustrated.Fig. 4 is the generalized section according to the non-volatility memory that further embodiment of this invention illustrated.Tunneling dielectric layer 300 is disposed in the substrate 100, and floating grid 302 is disposed on the tunneling dielectric layer 300, and dielectric layer 304 is disposed on the floating grid 302 between grid.Control grid 306 is disposed between grid on the dielectric layer 304.Clearance wall 108 is disposed on the sidewall of dielectric layer between tunneling dielectric layer 300, floating grid 302, grid 304 and control grid 306.Dielectric layer 304 for example is the composite construction by oxide layer/nitration case/oxide layer constituted between grid.Floating grid 302 is as charge storing structure.
In sum, in an embodiment of the present invention, when forming doped region, serve as that the cover curtain mixes with grid and clearance wall, therefore after admixture was implanted in the substrate, clearance wall can be used as the buffering area of dopant diffusion.Some dopant diffusion to clearance wall below; And can only not diffuse to the below of charge storing structure; Therefore can avoid the passage length of memory body to shorten effectively, and then produce the second bit effect can avoid memory body operated the time, and increase operation window.
In addition, in the non-volatility memory of the embodiment of the invention, isolation structure is disposed in the substrate of grid structure two sides, therefore when non-volatility memory is carried out programming operations, can avoid the problem of sequencing interference effectively.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the method for above-mentioned announcement capable of using and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations; In every case be the content that does not break away from technical scheme of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. non-volatility memory is characterized in that it comprises:
One substrate;
One grid structure is disposed in this substrate, and this grid structure comprises:
One charge storing structure is disposed in this substrate;
One grid is disposed on this charge storing structure; And
One clearance wall is disposed on the sidewall of this grid and this charge storing structure;
One first doped region and one second doped region are disposed at respectively in this substrate of these charge storing structure two sides, and are positioned at the below of this clearance wall at least; And
A pair of isolation structure is disposed at respectively in this substrate of these grid structure two sides.
2. non-volatility memory according to claim 1 is characterized in that wherein said first doped region and this second doped region between this is to isolation structure, and this is to the degree of depth of the isolation structure degree of depth greater than this first doped region and this second doped region.
3. non-volatility memory according to claim 1; It is characterized in that wherein said first doped region and this second doped region center on this respectively to one in the isolation structure, and the degree of depth of this first doped region and this second doped region is greater than this degree of depth to isolation structure.
4. the manufacturing approach of a non-volatility memory is characterized in that it may further comprise the steps:
One substrate is provided;
In this substrate, form a charge storing structure and a grid;
On the sidewall of this charge storing structure and this grid, form a clearance wall;
In this substrate of these charge storing structure two sides, form a doped region;
In this substrate of this grid and this clearance wall two sides, form irrigation canals and ditches; And
In these irrigation canals and ditches, form an isolation structure.
5. the manufacturing approach of non-volatility memory according to claim 4 is characterized in that the degree of depth of the degree of depth of wherein said irrigation canals and ditches greater than this doped region.
6. the manufacturing approach of non-volatility memory according to claim 4 it is characterized in that wherein said doped region around these irrigation canals and ditches, and the degree of depth of this doped region is greater than the degree of depth of these irrigation canals and ditches.
7. the manufacturing approach of non-volatility memory according to claim 4 is characterized in that the formation method of wherein said isolation structure comprises:
In this substrate, form an insulation material layer, and this insulation material layer this grid of covering and this clearance wall, and fill up this irrigation canals and ditches; And
Carry out flatening process, remove this insulation material layer of part, up to exposing this grid.
8. non-volatility memory is characterized in that it comprises:
One substrate;
Two grid structures are disposed in this substrate, and each grid structure comprises:
One charge storing structure is disposed in this substrate; And
One grid is disposed on this charge storing structure;
One doped region is disposed in this substrate and between those grid structures; And
One isolation structure is disposed in this doped region.
9. non-volatility memory according to claim 8 is characterized in that the degree of depth of the degree of depth of wherein said isolation structure greater than this doped region.
10. non-volatility memory according to claim 8 is characterized in that the degree of depth of the degree of depth of wherein said doped region greater than this isolation structure.
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| CN104022064A (en) * | 2013-03-01 | 2014-09-03 | 格罗方德半导体公司 | Method of forming asymmetric spacers on various structures on integrated circuit product |
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| US20100155816A1 (en) * | 2008-12-22 | 2010-06-24 | Spansion Llc | Hto offset and bl trench process for memory device to improve device performance |
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| US6177317B1 (en) * | 1999-04-14 | 2001-01-23 | Macronix International Co., Ltd. | Method of making nonvolatile memory devices having reduced resistance diffusion regions |
| CN101335306A (en) * | 2007-06-27 | 2008-12-31 | 旺宏电子股份有限公司 | Silicone oxide non-volatile memory unit ultra-high in silicone and manufacturing method therefor |
| US20090039405A1 (en) * | 2007-08-08 | 2009-02-12 | Spansion Llc | Oro and orpro with bit line trench to suppress transport program disturb |
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| CN104022064A (en) * | 2013-03-01 | 2014-09-03 | 格罗方德半导体公司 | Method of forming asymmetric spacers on various structures on integrated circuit product |
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| CN102468305B (en) | 2015-04-01 |
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