CN102544139A - Photodiode device and manufacturing method thereof - Google Patents
Photodiode device and manufacturing method thereof Download PDFInfo
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- CN102544139A CN102544139A CN2010106031984A CN201010603198A CN102544139A CN 102544139 A CN102544139 A CN 102544139A CN 2010106031984 A CN2010106031984 A CN 2010106031984A CN 201010603198 A CN201010603198 A CN 201010603198A CN 102544139 A CN102544139 A CN 102544139A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The invention provides a photodiode device and a manufacturing method thereof. The photodiode device comprises a substrate, wherein an epitaxial layer is positioned on the substrate and comprises a window layer and a covering layer positioned on the window layer; the covering layer covers part of the window layer; and a patterned conductive layer is positioned on the covering layer and has a shape that a bottom area is larger than a top area.
Description
Technical field
The present invention relates to a kind of photoelectric diode device and manufacturing approach thereof, particularly relate to photoelectric diode device and manufacturing approach thereof with surface conductance layer.
Background technology
Along with the energy starved problem is serious day by day, the exploitation of energy savings and new forms of energy, for example wind-force, waterpower, solar energy etc. are paid attention to by people all gradually.Solar cell extensively is used on each item product owing to have long or the like advantage of pollution-free, easy to use, life-span now.Solar cell is to utilize the photovoltaic special efficacy should be with the photodiode of transform light energy for electric energy, is to use without the formed P-N knot of semi-conducting material face as the one of which to absorb sunlight.
Figure 1A and 1B are for making the flow process profile of known photodiode.With reference to Figure 1A, the wafer 100 that comprises substrate 110 and epitaxial loayer 120 at first is provided, at least one P-N ties the Window layer 123 and the cover layer 125 of face 121 and top thereof to epitaxial loayer 120 for sandwich construction comprises.Then form back of the body conductive layer 130, supply the usefulness of follow-up electrical connection at the back of wafer 100.Then; Use photomask; With known metal deposition, photoetching, and technology such as etching form first patterned conductive layer 140 on epitaxial loayer 120, its thickness is about
Then, with reference to Figure 1B, be mask with first patterned conductive layer 140, the cover layer 125 of etching epitaxial loayer 120 is to expose Window layer 123.Then, use another photomask, form second patterned conductive layer 150 on first patterned conductive layer 140, to increase the thickness of monolithic conductive layer with the mode of electroplating.In general, the thickness of second patterned conductive layer 150 is about 5-6 μ m.At last, can on wafer 100, cover the conformal anti-reflecting layer of one deck (figure does not show).
The method of Figure 1A and 1B has a lot of shortcomings.For example, first patterned conductive layer 140 and second patterned conductive layer 150 are to use the twice photomask to make respectively, and not only cost is high, also is easy to generate the difficulty of aligning, and then causes the bad structure shown in Figure 1B.Therefore, be necessary to provide a kind of structure of novelty and method to improve known problem.
Summary of the invention
In view of the existing problem of known technology, the invention provides a kind of photodiode and manufacturing approach thereof that improves photoelectric conversion efficiency, lifting technology reliability, reaches the reduction cost of manufacture.
One side of the present invention is to provide a kind of photoelectric diode device to comprise substrate; Epitaxial loayer is on this substrate, and this epitaxial loayer comprises Window layer and cover layer is positioned on this Window layer, and this cover layer covers the part of this Window layer; Reach patterned conductive layer on this cover layer, this patterned conductive layer has the shape of bottom area greater than its topside area.
Another aspect of the present invention is to provide a kind of photoelectric diode device as above-mentioned, and wherein this patterned conductive layer does not have 1/15th the foot structure of extending along this level of base plate direction that is equal to or less than this pattern conductive layer thickness.
Another aspect of the present invention is to provide a kind of manufacturing approach of photoelectric diode device, and comprising provides wafer, comprises substrate and epitaxial loayer, and this epitaxial loayer comprises Window layer and cover layer is positioned on this Window layer; The deposit patterned conductive layer is on this epitaxial loayer, and this patterned conductive layer has the foot structure that along continuous straight runs extends from the bottom of this patterned conductive layer, and the thickness of this foot structure is equal to or less than 1/15th of this pattern conductive layer thickness; Remove the part of this foot structure; And this tectal part of etching so that this Window layer expose.
Another aspect of the present invention is to provide the manufacturing approach like above-mentioned photoelectric diode device, and the step that wherein deposits this patterned conductive layer also comprises uses evaporation process so that this patterned conductive layer has the shape of bottom area greater than its topside area.
Other aspects of the present invention, part will be stated in follow-up explanation, and part can be learnt in explaining easily, or can be learnt by enforcement of the present invention.Each side of the present invention is with the element that is particularly pointed out in the claim capable of using and combination and understand and reach.Need to understand, usefulness is for example all only made in general remark of stating earlier and following detailed description, is not in order to restriction the present invention.
Description of drawings
Figure 1A and 1B are for making the flow process profile of known photoelectric diode device;
Fig. 2 A to Fig. 2 F and Fig. 2 B ' are according to the embodiment of the invention, and illustrate the flow process profile of making photoelectric diode device;
Fig. 3 A to Fig. 3 E is according to another embodiment of the present invention, and illustrates the flow process profile of making photoelectric diode device;
Fig. 4 is another embodiment again according to the present invention, and the photoelectric diode device profile that illustrates;
Fig. 5 A and 5B are the embodiment of the invention forms the tool foot structure in manufacture process the half-finished sweep electron microscope of photodiode (SEM) diagram; And
Fig. 6 is the embodiment of the invention is removed foot structure in manufacture process the half-finished sweep electron microscope of photodiode (SEM) diagram.
Description of reference numerals
100: wafer 110: substrate
120: epitaxial loayer 121:P-N ties surface layer
123: Window layer 125: cover layer
130: 140: the first patterned conductive layers of back of the body conductive layer
Patterned conductive layer 300 in 150: the second: wafer
310: substrate 312: first surface
314: second surface 320: epitaxial loayer
321: sandwich construction 322: Window layer
323: cover layer 330: back of the body conductive layer
340: patterned conductive layer 340a: sidewall
340 ': electric conducting material 340 ": electric conducting material
350: foot structure 360: anti-reflecting layer
380: patterning photoresist layer 380a: edge
390: opening 400: wafer
410: substrate 412: first surface
414: second surface 420: epitaxial loayer
421:P-N ties surface layer 422: Window layer
423: cover layer 430: back of the body conductive layer
440: patterning photoresist layer 450: patterned conductive layer
460: foot structure 470: anti-reflecting layer
510: substrate 520: epitaxial loayer
522: Window layer 523: cover layer
530: back of the body conductive layer 550: patterned conductive layer
570: anti-reflecting layer 571: opening
Embodiment
The present invention discloses a kind of photoelectric diode device and manufacturing approach thereof, can improve the conversion efficiency of photoelectric diode device, and can reduce required photomask quantity, and then reduces cost of manufacture.In order to make narration of the present invention more detailed and complete, can be with reference to the accompanying drawing of following description and cooperation Fig. 2 A to Fig. 6.Device, element and method step described in right following examples in order to explanation the present invention, is not in order to limit scope of the present invention only.It should be noted that to clear to present the present invention, each element in the accompanying drawing is not the scale according to material object, and for avoiding fuzzy content of the present invention, below known secondary structure, associated materials and correlation processing technique thereof are also omitted in explanation.
In method of the present invention, be based upon each layer material on the epitaxial loayer; Can carry out via the method that persons skilled in the art are known; Sedimentation (deposition) for example, chemical vapour deposition technique (chemical vapor deposition), plasma enhanced chemical vapor deposition method (plasma enhancedchemical vapor deposition (PECVD)), vapour deposition method (evaporation), galvanoplastic (plating) or atomic layer deposition method (atomic layer deposition (ALD)) etc.
Fig. 2 A to Fig. 2 F is according to the embodiment of the invention, and illustrates the flow process profile of making photoelectric diode device.With reference to figure 2A, in an embodiment of the present invention, wafer 300 is provided, it comprises substrate 310 and is formed at the epitaxial loayer 320 on the first surface 312 of substrate 310.Substrate 310 can be any suitable semiconductor substrate, for example silicon substrate, germanium substrate, GaAs substrate etc.Epitaxial loayer 320 is for comprising the sandwich construction of at least one P-N knot face, and its material can be the combination of the various semi-conducting materials that meet lattice match and ability rank demand.Epitaxial loayer 320 can for example use Metalorganic chemical vapor deposition method (MOCVD) or molecular beam epitaxy sedimentation technology such as (MBE) known film and form.In this embodiment, epitaxial loayer 320 comprises a plurality of P-N knot faces and the sandwich construction 321 of the tunnel type conductive layer between each P-N knot face respectively.Epitaxial loayer 320 also comprises Window layer 322 and cover layer 323 in the top of sandwich construction 321.
In general, a plurality of P-N knot faces that epitaxial loayer 320 is comprised are to use different semi-conducting materials made, and it has different energy gaps, in order to absorb the sunlight of different wave length.For instance, epitaxial loayer 320 can comprise GaInP layer, GaAs layer, reach the GaInAs layer.In an embodiment, the P-N knot mask near substrate has more little energy gap more, in order to the long more sunlight of absorbing wavelength.Utilize the P-N knot face of the different energy gaps of a plurality of tools, can improve the absorption region of optical wavelength, and then promote photoelectric conversion efficiency.
Then, at the second surface 314 formation back of the body conductive layers 330 of substrate 310, its material can be any suitable conducting metal, the alloy that for example titanium, silver, platinum, gold, tin, nickel, copper or its constituted etc. or other suitable electric conducting materials.The method that forms back of the body conductive layer 330 can for example be printing or various vacuum coating technology.
With reference to figure 2B, form patterned conductive layer 340 on epitaxial loayer 320.The material of patterned conductive layer 340 can be various suitable electric conducting materials, and like metal or metal alloy, its thickness preferably is about 4 μ m to about 8 μ m, and is so not subject to the limits.Patterned conductive layer can be sandwich construction.In this embodiment, patterned conductive layer 340 comprises that end contact layer directly contacts with epitaxial loayer, intermediate conductive layer on the end contact layer, go up conductive layer on the intermediate conductive layer, and the top barrier layer on last conductive layer.In other embodiment, patterned conductive layer 340 can have only the two-layer arbitrarily of above-mentioned each layer.More in other embodiment, patterned conductive layer 340 can also can comprise the layer of other functions of tool except that comprising above-mentioned each layer.
Form patterned conductive layer 340 and can use known metal deposition process.This embodiment uses evaporation process.Shown in Fig. 2 B ', be that it exposes the opening 390 of desiring deposit patterned conductive layer 340 prior to formation patterning photoresist layer 380 on the epitaxial loayer 320.This embodiment uses negative type photoresist to make patterning photoresist layer 380, and its thickness preferably can be between 9 μ m to 12 μ m.The top of negative type photoresist is connected to suitable with the top of the patterned conductive layer 340 that do not form with desire.Patterning photoresist layer 380 is owing to form the incision shape shown in Fig. 2 B ' through irradiation and development effect meeting.Then, with the mode deposits conductive material of vapor deposition in opening 390 to form patterned conductive layer 340 on epitaxial loayer 320.And then utilize peel off (lift-off) technology remove patterning photoresist layer 380 with and the unnecessary electric conducting material 340 ' and 340 of top ", form the structure shown in Fig. 2 B.Should note at each layer that this embodiment patterned conductive layer 340 is comprised it being to deposit formation in regular turn for adopting material different under the mask at same patterning photoresist layer (promptly 380).For example, end contact layer can be Ge or Ni or Pd or its alloy, intermediate conductive layer and can be Ag, goes up conductive layer and can be various oxides or its various combinations etc. that Au or Mo or its alloy, top barrier layer can be Ni, W, Mo, Ti, Ta or above-mentioned material.
Can be through the time of control vapor deposition and the thickness and the shape of determining positions patterned conductive layer 340.Shown in Fig. 2 B ', when carrying out vapor deposition, make patterning photoresist layer 380 deposit some conductive layers 340 gradually near the edge 380a of opening 390 ", to let the size of opening 390 along with the vapor deposition time is little more for a long time and more.The area that so is its accumulation of electric conducting material of may command institute vapor deposition dwindles gradually, forms thus to have the trapezoidal cross-section structure that is similar to shown in Fig. 2 B and 2B '.Patterned conductive layer 340 is bigger near the bottom area of epitaxial loayer 320, and patterned conductive layer 340 is less away from the topside area of epitaxial loayer 320.
With reference to figure 2B and 2B ', the two bottom sides of patterned conductive layer 340 possibly form foot structure (footing) 350 because of vapor deposition or other technology.Foot structure is that the electric conducting material that extend along the horizontal direction of substrate 301 bottom of this patterned conductive layer 340 is piled up.In this embodiment, sidewall 340a backwash to beneath epitaxial loayer 320 surfaces thereby the accumulation of electric conducting material bump patterned conductive layer 340 formed when the main formation reason of foot structure 350 possibly be vapor deposition.Long more with the process time, the thick more foot structure 350 of vapor deposition patterned conductive layer 340 can be thick more and sturdy more.In this embodiment, intermediate conductive layer is the thickest, so foot structure 350 Main Ingredients and Appearances are the material of intermediate conductive layer, for example is silver.Generally speaking, the thickness d of foot structure 350 be about patterned conductive layer 340 thickness D 1/15th or lower.Thickness D is at the patterned conductive layer 340 of 4 μ m to about 8 μ m, and its thickness d that can form foot structure 350 is that about 1 μ m is to about 2 μ m for about
to about
width w.This embodiment is because vapor deposition produces foot structure 350.Use different depositing operations also possibly produce foot structure in other embodiment.
Then,, wafer 300 is carried out etching, to remove foot structure 350 with reference to figure 2C.Can use any suitable etching method such as the ion(ic) etching of dry ecthing, wet etching, physical property ion(ic) etching or chemical ion(ic) etching or the bond rational faculty and chemical.Using dry ecthing to be example, etching condition can the pressure of 10-30mTorr, 100-500Watt, and the Dc bias of 300-600V under, use the inert gas of 15-25sccm flow, inert gas can be selected from He, Ne, Ar, Kr, Xe, arbitrary or each combination of Rn.At this embodiment is to select Ar for use, foot structure 350 is bombed after making it form plasma.In other embodiment, can use argon (Ar) or helium (He) or combine argon (Ar) and helium (He).Some embodiment also uses wet etching, when especially foot structure 350 has a long way to go on the overall structure size of patterned conductive layer 340, can adopt the wet etching process of short time to remove foot structure 350.In some embodiment, foot structure 350 can be removed as much as possible; In some embodiment, foot structure 350 can only be removed a part.
Note in this embodiment; Use the etchant of removing foot step structure 350 material for the top barrier layer of patterned conductive layer 340 (being various oxides or its various combinations etc. of Ni, W, Mo, Ti, Ta or above-mentioned material) is had very low rate of etch, therefore in the dry-etching process, patterned conductive layer 340 is had protective effect at this embodiment top barrier layer.In addition, about foot structure, can make the sweep electron microscope photo of the generation of process in fact with reference to the present invention.Fig. 5 A and 5B are the half-finished sweep electron microscope of photodiode (SEM) figure that forms the tool foot structure in the manufacture process; Fig. 6 is the half-finished sweep electron microscope figure of photodiode that in manufacture process, removes foot structure.
Then, with reference to figure 2D, be mask with patterned conductive layer 340, the Window layer 322 under etching epitaxial loayer 320 exposes with a part of removing cover layer 323.The method of etching epitaxial loayer 320 can be dry ecthing or wet etching process.With the wet etching is example, can use NH
4OH solution or by H
3PO
4, H
2O
2, H
2O mixes according to special ratios or use contains the formed solution of citric acid as etching solution.Wet etching process can make residual cover layer 323 have the undercut structures (figure does not show) with respect to the patterned conductive layer 340 of top.
With reference to figure 2E, be conformally formed anti-reflecting layer 360 and be positioned on the patterned conductive layer 340.Anti-reflecting layer 360 can reduce the chance of incident light reflection, improves the efficient of opto-electronic conversion.The material of anti-reflecting layer 360 can be the various transparent materials that refractive index is lower than substrate 310, for example silica (SiO
x), silicon nitride (SiN
x), titanium oxide (TiO
x), aluminium oxide (AlO
x) or comprising formed individual layer of one or more above-mentioned material or double-decker, its thickness can or be used required and adjusts according to the different of material refractive index.The formation method of anti-reflecting layer 360 can for example be known various deposition techniques, like vapor deposition, sputter, chemical vapour deposition (CVD) etc.
Then,, use known exposure photoetching technology, remove the anti-reflecting layer 360 of part, with the patterned conductive layer 340 under exposing, as the usefulness of follow-up electrical connection with reference to figure 2F.This step is applicable to the bus structures on the surface that forms photoelectric diode device.The step that part anti-reflecting layer 360 is removed can for example be that first painting photoresist layer (figure does not show) is on anti-reflecting layer 360; Utilize design transfer technology such as exposure imaging the photoresist patterned to be defined the position of the patterned conductive layer 340 that institute's desire exposes again; Again with this patterning photoresist layer as mask, etching anti-reflecting layer 360 and obtain structure shown in Fig. 2 F.
Photodiode shown in Fig. 2 A to 2F embodiment has the following advantages at least.At first its not tool photoelectric conversion efficiency is had dysgenic foot structure; Secondly for patterned conductive layer 340 does not need via forming like the described twice photo-marsk process of Figure 1B, it is only formed so manufacture process is known relatively more simple by one photomask, can reduce cost of manufacture effectively; Moreover it is the roomy relatively class trapezium structure in narrow relatively bottom, top that patterned conductive layer 340 has, and known relatively, it is reduced by the probability that the light of top incident is stopped, can so increase photoelectric conversion efficiency.
Fig. 3 A to Fig. 3 E is according to another embodiment of the present invention, and illustrates the flow process profile of making photodiode.The embodiment of Fig. 3 A to Fig. 3 E and the difference of aforesaid embodiment are that aforesaid embodiment forms patterned conductive layer earlier, are the extension cover layer under the mask etching with the patterning conductor layer; The embodiment of Fig. 3 A to Fig. 3 E then is first with the extension cover layer under another photomask etching, forms patterned conductive layer again.
With reference to figure 3A, in embodiments of the present invention, wafer 400 is provided, it comprises substrate 410 and is formed at the epitaxial loayer 420 on the first surface 412 of substrate 410.The structure of substrate 410 and epitaxial loayer 420 and material can be with reference to above stated specification.Then, form back of the body conductive layer 430 with for example methods such as printing or vacuum coating technology at the second surface 414 of substrate 410.Then, form patterning photoresist layer 440 on epitaxial loayer 420, the etched position of desire to define.The formation method of patterning photoresist layer 440 can for example be that elder generation's comprehensive ground painting photoresist layer (figure does not show) is on epitaxial loayer 420; Utilize design transfer technology patterning photoresist layers such as exposure imaging again, and form the patterning photoresist layer 440 shown in Fig. 3 A.
With reference to figure 3B, be mask with patterning photoresist layer 440, the cover layer 423 of etching epitaxial loayer 420 is with the Window layer 422 under exposing.The method of etching epitaxial loayer 420 can be with reference to aforementioned related description.Then, with reference to figure 3C, remove patterning photoresist layer 440 after, form patterned conductive layer 450 to cover a plurality of cover layers 423 at least.The method that forms patterned conductive layer 450 can comprise: with rotary coating, exposure, and photoetching technique such as developments forms patterning photoresist layer (scheming not show), and on substrate 410, wherein patterning photoresist layer does not cover cover layer 423; Then form conductive layer with overlay pattern photoresist layer and cover layer 423 with known metal deposition process such as for example vapor depositions; Remove patterning photoresist layer and be arranged in the unnecessary conductive layer of part on the patterning photoresist layer and obtain the patterned conductive layer 450 of Fig. 3 C to peel off (lift-off) technology again.The structure that should note patterned conductive layer 450 has and is similar to trapezoidal section, and is less away from its area of top of epitaxial loayer 420, bigger near its area of bottom of epitaxial loayer 420.As aforementioned, when forming patterned conductive layer 450, may can't form foot structure 460 because of the restriction of technology with avoiding.Generally speaking, the thickness d of foot structure 460 be about patterned conductive layer 450 thickness D 1/15th or lower.At this embodiment, foot structure 460 thickness d are that about 1 μ m is to about 2 μ m for about
to about
width w.The material of patterned conductive layer 450 can be various suitable electric conducting materials, and thickness is about 4 μ m to about 8 μ m, and is so not subject to the limits.
Then, with reference to figure 3D, the etching method that uses previous embodiment to say carries out etching to wafer 400, to remove foot structure 450.Then, with reference to figure 3E, form patterning anti-reflecting layer 470 on substrate 410.Patterning anti-reflecting layer 470 optionally the patterned conductive layer 450 of expose portion with useful as the electrical connection of follow-up making bus structures institute.The formation method of pattern reflecting layer 470 can for example comprise following steps: form conformal anti-reflecting layer (figure does not show) with known depositing operation, its material and other details can be with reference to above stated specification comprehensively; Then, form patterning photoresist layer on conformal anti-reflecting layer, the position of the patterned conductive layer 450 that desire exposes to define; Be mask with this patterning photoresist layer more at last, the conformal anti-reflecting layer of etching, and obtain the patterning anti-reflecting layer 470 shown in Fig. 3 E.
Embodiment shown in Fig. 3 A to Fig. 3 E has a shortcoming to be, the Window layer of exposing under the process of manufacturing patterned conductive layer 450 possibly injure 422.Therefore, at another embodiment, can after exposing Window layer, form anti-reflecting layer covering Window layer and cover layer partly earlier to protect, and then make patterned conductive layer at the etching cover layer.Structure as shown in Figure 4, it comprises substrate 510, the epitaxial loayer 520 of substrate 510 tops.Epitaxial loayer 520 comprises cover layer 523 and Window layer 522.Structure shown in Figure 4 also comprises anti-reflecting layer and covers Window layer 522 for 570 layers; The cover layer 523 of part; Reach patterned conductive layer 550 in cover layer 523 tops, wherein patterned conductive layer 550 can link to each other through the opening 571 and cover layer 523 electricity of anti-reflecting layer 570.The manufacturing process of patterned conductive layer 550 can be with reference to previous embodiment.
The above is merely the preferred embodiments of the present invention, is not in order to limit claim of the present invention; All other do not break away from being equal to of being accomplished under the disclosed spirit and changes or modify, and all should be included in the scope of claim.
Claims (14)
1. the manufacturing approach of a photoelectric diode device comprises:
Wafer is provided, comprises substrate and epitaxial loayer, this epitaxial loayer comprises Window layer and cover layer is positioned on this Window layer;
The deposit patterned conductive layer is on this epitaxial loayer, and this patterned conductive layer has the foot structure that along continuous straight runs extends from the bottom of this patterned conductive layer, and the thickness of this foot structure is equal to or less than 1/15th of this pattern conductive layer thickness; And
Remove the part of this foot structure; And
This tectal part of etching so that this Window layer expose.
2. manufacturing approach as claimed in claim 1, wherein this patterned conductive layer comprises sandwich construction, and this sandwich construction is through same mask, adopts material different to deposit in regular turn and forms.
3. manufacturing approach as claimed in claim 2, wherein this mask is a negative type photoresist, after this manufacturing approach also is included in this patterned conductive layer of deposition, removes the electric conducting material of this mask and this mask top with stripping technology.
4. manufacturing approach as claimed in claim 3, wherein this negative type photoresist thickness is between 9 μ m to 12 μ m, and the thickness of this patterned conductive layer is between 4 μ m to 8 μ m.
5. manufacturing approach as claimed in claim 1, wherein the step of this this patterned conductive layer of deposition also comprises the use evaporation process so that this patterned conductive layer has the shape of bottom area greater than its topside area.
6. manufacturing approach as claimed in claim 2, wherein the step of this this patterned conductive layer of deposition also comprises:
Make this mask have opening and expose this beneath epitaxial loayer;
The material of this patterned conductive layer is deposited on this epitaxial loayer that this opening exposes; And
Make the material of this patterned conductive layer of a part be deposited on this mask edge gradually, so that this opening diminishes gradually near this opening.
7. manufacturing approach as claimed in claim 1, wherein this patterned conductive layer also comprises the top barrier layer, is used to carry out protect this patterned conductive layer when dry-etching is removed this foot structure a part of.
8. manufacturing approach as claimed in claim 1 is wherein removed this foot structure and is to use dry-etching, and condition is under 10 to 30mTorr the pressure limit, and use traffic is at 15 to 25sccm inert gas.
9. manufacturing approach as claimed in claim 8, wherein this dry-etching is to be that 100 to 500 watts, Dc bias are to carry out under 300 to 600 volts at power.
10. manufacturing approach as claimed in claim 1, wherein this tectal step of this etching is before the step of this this patterned conductive layer of deposition, to implement.
11. a photoelectric diode device, it is to process with the arbitrary described method of claim 1 to 10.
12. a photoelectric diode device comprises:
Substrate;
Epitaxial loayer on this substrate, this epitaxial loayer comprise Window layer and cover layer is positioned on this Window layer, and this cover layer covers the part of this Window layer; And
In this supratectal patterned conductive layer, this patterned conductive layer has the shape of bottom area greater than its topside area.
13. photoelectric diode device as claimed in claim 12, wherein this patterned conductive layer does not have 1/15th the foot structure of extending along this level of base plate direction that is equal to or less than this pattern conductive layer thickness.
14. photoelectric diode device as claimed in claim 12, wherein this patterned conductive layer is a sandwich construction, and this sandwich construction is to be that mask deposition forms through same patterning photoresist layer.
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|---|---|---|---|
| CN2010106031984A CN102544139A (en) | 2010-12-23 | 2010-12-23 | Photodiode device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106031984A CN102544139A (en) | 2010-12-23 | 2010-12-23 | Photodiode device and manufacturing method thereof |
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| CN102544139A true CN102544139A (en) | 2012-07-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117135994A (en) * | 2023-10-25 | 2023-11-28 | 致真存储(北京)科技有限公司 | Method for manufacturing semiconductor device and semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5604073A (en) * | 1994-01-12 | 1997-02-18 | International Business Machines Corporation | Azo dyes as adhesion promotion additive in polydimethylglutarimide |
| US20040069746A1 (en) * | 2002-10-15 | 2004-04-15 | Richard Hsiao | Method of removing magnetoresistive sensor cap by reactive ion etching |
| TW200428529A (en) * | 2003-06-11 | 2004-12-16 | Ind Tech Res Inst | Method for forming a conductive layer |
| US7126052B2 (en) * | 2002-10-02 | 2006-10-24 | The Boeing Company | Isoelectronic surfactant induced sublattice disordering in optoelectronic devices |
-
2010
- 2010-12-23 CN CN2010106031984A patent/CN102544139A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5604073A (en) * | 1994-01-12 | 1997-02-18 | International Business Machines Corporation | Azo dyes as adhesion promotion additive in polydimethylglutarimide |
| US7126052B2 (en) * | 2002-10-02 | 2006-10-24 | The Boeing Company | Isoelectronic surfactant induced sublattice disordering in optoelectronic devices |
| US20040069746A1 (en) * | 2002-10-15 | 2004-04-15 | Richard Hsiao | Method of removing magnetoresistive sensor cap by reactive ion etching |
| TW200428529A (en) * | 2003-06-11 | 2004-12-16 | Ind Tech Res Inst | Method for forming a conductive layer |
Non-Patent Citations (1)
| Title |
|---|
| IBM, ET AL.: "Skirt Removal Process for Metal Lift-Off", 《IBM TECHNICAL DISCLOSURE BULLETIN》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117135994A (en) * | 2023-10-25 | 2023-11-28 | 致真存储(北京)科技有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN117135994B (en) * | 2023-10-25 | 2023-12-29 | 致真存储(北京)科技有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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Application publication date: 20120704 |