CN102569136A - 清洁基板表面的方法和设备 - Google Patents

清洁基板表面的方法和设备 Download PDF

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CN102569136A
CN102569136A CN201210032669XA CN201210032669A CN102569136A CN 102569136 A CN102569136 A CN 102569136A CN 201210032669X A CN201210032669X A CN 201210032669XA CN 201210032669 A CN201210032669 A CN 201210032669A CN 102569136 A CN102569136 A CN 102569136A
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埃罗尔·安东尼奥·C·桑切斯
乔黑尼斯·斯温伯格
戴维·K·卡尔森
罗伊辛·L·多尔蒂
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Abstract

本发明大体提供用于在半导体基板上形成干净且无伤害的表面的设备及方法。本发明的一个实施例提供一系统，该系统含有一清洁腔室，该清洁腔室适于在基板表面上形成外延层之前，将基板表面暴露于等离子体清洁处理。在一实施例中，采用一方法以减少在清洁腔室中处理的基板的污染，该方法藉由在基板上进行清洁处理之前，于清洁腔室的内表面上沉积集除物质。在一实施例中，于清洁腔室的基板上重复进行氧化及蚀刻步骤，以在基板上暴露出或产生一干净表面，而可以在干净表面上沉积外延层。在一实施例中，于清洁步骤中使用低能量等离子体。

Description

清洁基板表面的方法和设备
本申请是2008年7月8日申请的申请号为200880100583.8的发明专利申请的分案申请。
技术领域
本发明的实施例大体涉及用于处理半导体基板的方法和设备，特别是用于清洁硅基板表面的方法和设备。
相关技术说明
集成电路形成在硅及其它半导体基板内及上方。在单晶硅的实例中，通过从熔融硅浴生长硅晶锭(ingot)，并接着将固化的晶锭锯开成为多个晶圆而制成基板。可接着在单晶硅晶圆上形成外延硅层，以形成掺杂或未掺杂的无缺陷硅层。半导体装置(例如晶体管)由外延硅层制造。所形成的外延硅层的电学特性通常比单晶硅基板的特性要好。
单晶硅及外延硅层的表面当暴露于一般周围条件时容易受到污染。因此，在执行多种半导体工艺(例如形成外延层)之前，需要清洁基板以移除硅晶圆表面上的杂质及微粒。
常规地，利用湿式清洁处理或常规等离子体清洁处理来清洁半导体基板。然而，湿式清洁处理具有“排队时间”的问题，由于一批中的晶圆具有不同的闲置时间，故会造成一批晶圆中的晶圆与晶圆之间产生差异。常规的远程或原位(in situ)等离子体清洁处理极具挑战性，因为以气相形成的或在清洁处理过程中所产生的不期望存在的物种而造成腔室及腔室中待处理基板的污染。该些不期望存在的物种会限制期望物种的清洁作用，或是将其它的困难引入清洁处理中。
因此，需要清洁基板表面的方法及设备，特别是在执行外延沉积处理之前用于清洁基板表面的方法及设备。
发明内容
本发明一般提供一种处理基板的设备，该设备包括低能量清洁腔室、外延层沉积腔室以及传输室，该低能量清洁腔室包括：形成一处理区域的一或多个壁；适于传送电磁能至处理区域的等离子体产生源；适于传送含硅气体至处理区域的第一气源；适于传送氧化气体至处理区域的第二气源，该传输室具有围出一传输区域的一或多个壁，以及适于将基板在低能量清洁腔室中的第一位置以及外延层沉积腔室中的第一位置之间传输的机械手。
本发明的实施例还提供用于执行低能量清洁处理的设备，该设备包括：形成一处理区域的一或多个壁；适于传送电磁能至处理区域的等离子体产生源；设置在处理区域中的屏蔽，其中制成该屏蔽的材料选自由硅、钇、氧化钇、锗、硼、磷及硅锗化合物所组成的组；具有基板支撑表面以及适于被RF功率源所偏压的偏压电极的基板支撑件；适于传送氧化气体至处理区域的第一气源；适于传送惰性气体至处理区域的第二气源；以及适于传送含硅气体至处理区域的第三气源。
本发明的实施例还提供一种形成外延层的方法，该方法包括：在一腔室部件的一表面上沉积一集除层(gettering layer)，而该腔室部件设置于一清洁腔室中的处理区域内；将基板放置在清洁腔室的处理区域中的基板支撑件上；将放置在基板支撑件上的基板表面进行氧化；自放置在该基板支撑件上的该基板移除至少一部分的氧化表面；在移除至少一部分的氧化表面之后，藉由将基板表面暴露于含氢气体而钝化该基板表面；将基板由清洁腔室传输至外延层沉积腔室；以及在至少一部分的钝化表面上沉积一外延层。
本发明的实施例还提供一种执行低能量清洁处理的设备，该设备包括：形成处理区域的一或多个壁，其中该一或多个壁的至少其中之一含有热交换装置以控制该一或多个壁的至少其中之一的温度；适于传送电磁能至处理区域的等离子体产生源；设置在处理区域中的屏蔽；具有基板支撑表面和适于被RF功率源所偏压的偏压电极的基板支撑件，以及用于控制基板支撑表面温度的基板支撑件热交换装置；适于传送氧化气体至处理区域的第一气源；以及适于传送蚀刻气体至处理区域的第二气源。
附图简要说明
为了使本发明的上述特征更明显易懂，可配合参考实施例说明，实施例部分绘示如附图。需注意的是，虽然附图公开本发明特定实施例，但附图并非用以限定本发明的精神与范围，任何本领域技术人员，可作各种修改与修饰而得到等效实施例。
图1概要绘示根据本发明一个实施例的清洁腔室的截面侧视图。
图2A概要绘示根据本发明另一实施例的清洁腔室的截面侧视图。
图2B概要绘示根据本发明一个实施例的清洁腔室的截面侧视图。
图3绘示根据本发明一个实施例的用于清洁半导体基板的方法的流程图。
图4概要绘示清洁腔室的一部分截面侧视图。
图5概要绘示根据本发明一个实施例的群集式工具的平面视图。
为了便于了解，附图中相同的组件符号表示相同的组件。某一实施例采用的组件不需特别详述而可应用到其它实施例。
详细说明
本发明一般提供用于在半导体基板(或晶圆)上形成干净且无损害的表面的设备及方法。本发明的一个实施例提供一种系统，所述系统含有一清洁腔室，该清洁腔室适以在基板表面上形成外延层之前，将该基板表面暴露于等离子体清洁处理。在一个实施例中，使用一种方法以减少在清洁腔室中进行处理的基板的污染，该方法藉由在基板上执行清洁处理之前，于清洁腔室的内表面上沉积集除物质(gettering material)。集除物质会倾向捕捉在清洁腔室中的污染物，因而确保所处理的基板为干净的，且即将在清洁腔室中进行处理的基板也具有相同的期望的干净结果。在一个实施例中，于清洁腔室中的基板上重复执行氧化及蚀刻步骤，以在基板上暴露或产生干净表面，而接着可在此表面上设置外延薄膜。在一个实施例中，在蚀刻步骤过程中使用低能量等离子体。等离子体低能量可通过下列方式实现：降低基板RF偏压功率、调整跨越基板施加的偏压电位、将用于在处理腔室中产生等离子体的RF功率进行脉冲、脉冲基板RF偏压功率、形成含有轻(light)原子物种的等离子体、使用等离子体屏蔽以限制等离子体、调整基板相对于等离子体的处理位置和/或所述方式的组合。
清洁腔室
图1概要绘示了根据本发明的一个实施例的清洁腔室100的横截面侧视图。清洁腔室100为感应耦合等离子体处理腔室，所述清洁腔室100能够在处理区域122中清洁基板102。在一个实施例中，清洁腔室100为改良的去耦等离子体氮化(DPN)腔室，该改良的去耦等离子体氮化腔室可购自加州圣克拉拉的应用材料公司(Applied Material)，该腔室利用感应耦合射频(RF)源。适以执行此处所述的一或多种处理的DPN腔室的详细描述可参见：美国专利No.6,660,659，专利名称为“Plasma Method and Apparatus for Processing aSubstrate”；以及美国专利No.7,122,454，专利名称为“Method for improvingnitrogen profile in plasma nitrided gate dielectric layers”，在此将所述专利的全文并入以做为参考。
清洁腔室100一般包括RF源组件191、处理腔室组件193及基板支撑组件194。处理腔室组件193通常包括多个用于在处理区域122中形成真空的部件，藉此可在该真空中执行等离子体处理。一般来说，处理腔室组件193包括密封地围绕处理区域122的腔室基座127、腔室壁128及腔室盖129。处理区域122可利用真空泵110抽气至期望的真空压力，而真空泵110穿过腔室基座127和/或腔室壁128而连接至处理区域122。一般来说，腔室壁128及腔室基座127可以由金属形成，例如铝或其它适合金属。
在一个实施例中，腔室壁128及腔室盖129可以为温控的。可使用常规方法和/或热交换装置来加热及冷却各个腔室部件。举例来说，可以藉由设置在处理腔室组件193外的加热器(未示出，例如为灯组)来加热腔室壁128及腔室盖129。在另一实施例中，可将冷却气体循环于处理腔室组件193外侧，藉以冷却腔室壁128及腔室盖129。在另一实施例中，嵌设在腔室壁128及腔室盖129中的加热和/或冷却导管可连接至流体加热器/冷却器装置以控制温度。可用于控制处理腔室组件193的方法及设备可参见美国专利NO.6,083,323，专利名称为“Method for Controlling the Temperature ofthe Walls of aReaction Chamber During Processing”，在此将所述专利并入以做为参考。
在一个实施例中，RF源组件191为感应型(inductive)RF源，该RF源组件191通常包含RF产生器108及RF匹配电路108A，而RF匹配电路108A连接至线圈109。线圈109邻近腔室盖129。在个一实施例中，RF产生器108可以在约400kHz～约60MHz的频率下以约0～约3000W操作。在一个实例中，RF产生器108以13.56MHz的频率操作。在一个实施例中，RF产生器108可以提供RF能量脉冲至线圈109，以产生具有降低的能量层级和/或等离子体密度的等离子体。
腔室盖129通常为介电部件(例如：石英、陶瓷物质(如：氧化铝))，该腔室盖129适以允许来自感应型RF源组件191的RF能量在处理区域122中形成等离子体。
在一个实施例中，处理腔室组件193也含有气体输送系统150，而该气体输送系统150适于将一或多种处理气体输送至处理区域122内，处理区域122由腔室基座127、腔室壁128及腔室盖129所界定。在一个实施例中，处理区域122的周围围绕有一或多个屏蔽130，而该些屏蔽130用于保护腔室壁128和/或腔室盖129免受所产生的等离子体以及在腔室中进行的准备处理的损害。在一个实施例中，气体输送系统150包括臭氧产生器，该臭氧产生器配置以产生含有高浓度臭氧(O3)的气流。在一个实施例中，气体输送系统适于输送反应性气体，例如含硅气体(例如硅烷)、含氢气体(例如H2)、含锗气体、含氯气体、含氧气体(例如O2)、三氟化氮(NF3)、含硼气体(例如二硼烷)和/或含磷气体(例如磷化氢)(仅列出少数)。在一个实施例中，气体输送系统适于输送惰性气体，例如氩气(Ar)、氦气(He)、氪气(Kr)和/或氮气(N2)。可通过调整由气体输送系统150输送的气体的流速以及真空泵110的抽气速率来控制处理区域122中的压力。节流阀111可用于调整真空泵110的抽气速率。
基板支撑组件194一般包括基板支撑件162，该基板支撑件162含有基板支撑构件162A。基板支撑构件162A可以为用于在处理过程中主动支托基板的常规静电吸座，或者是包括简单的基板支撑件。温度控制器161通常适于利用温度控制器161及热交换装置来加热和/或冷却基板支撑构件162A至一期望温度，热交换装置例如为嵌设的电阻加热组件或耦接至常规的热交换器的流体冷却通道(未示出)。在一个实施例中，温度控制器161适以操作并加热设置在基板支撑构件162A上的基板102至介于约20℃～约800℃的温度。
在处理过程中，基板支撑件162可以连接至RF产生器123，以便可以将RF偏压施加至设置在基板支撑件162的一部分中的导电组件，以将处理区域122中所形成的等离子体吸引至基板102的表面。在一个实施例中，RF产生器123适以在基板清洁处理过程的一或多个部分中于基板上产生阴极或阳极偏压以调整基板上所保有的电荷，和/或控制基板表面的离子及等离子体轰击量。在一个实施例中，基板支撑构件162A接地或者为DC(直流)偏压。在另一实施例中，基板支撑构件162A以及基板在等离子体处理过程中为电性浮置，以使得基板102的离子轰击损害降到最低。
参照图1，将来自RF产生器108的RF能量传送至处理区域122会导致处理区域122中的气体原子产生离子化。在清洁处理过程中，当基板暴露于处理区域122中所产生的等离子体时，基板102表面的污染会被击出，或是自表面解吸附(desorb)，这是由等离子体中的离子化原子所传输的能量撞击基板102表面所致。在一个实施例中，由于透过基板支撑构件162A而施加至基板102的偏压，可以将等离子体中的离子化气体原子吸引至基板102的表面。
在一个实施例中，藉由RF产生器108而传送至线圈109的RF功率经脉冲以形成低能量等离子体。在一个实施例中，脉冲等离子体处理通常为藉由RF产生器108所作用的线圈109而以时间为函数的一系列传送至处理区域122的连续能量脉冲。将感应RF源进行脉冲，以激发处理区域122中的等离子体，这样会使得通常形成在常规等离子体处理腔室中的等离子体电位(plasma potential)对于基板表面所造成的损害量降至最低。使得对基板表面所造成的任何损害通过清洁处理而最小化或消除的需求，对于制备用于在其上形成外延层单晶基板来说是关键的。需要使对于基板表面的损害最小化，以减少在所形成的外延层中的缺陷数量及应力。因此，对感应RF源功率进行脉冲允许产生并维持低电子温度及低离子能量等离子体。一般来说，由脉冲RF感应等离子体所产生的离子，其所产生的离子具有低离子能量(例如＜10eV)，而不会对于设置在等离子体中的基板造成损害。可以适用并受益于本发明一或多个实施例的脉冲RF功率的方法的实例进一步讨论于共同受让的美国专利6,831,021(2003年6月12日申请)，在此将该专利并入以做为参考。
图2A概要绘示了根据本发明另一实施例的清洁腔室100a的横截面侧视图。清洁腔室100a为电容耦合等离子体腔室。清洁腔室100a包括腔室盖129，该腔室盖129密封地耦接至处理腔室组件196并界定一处理区域133。在此配置中，腔室盖组件139包括气体分配板(也称作喷头)132及基座板131，该基座板131具有一基本平行于气体分配板132的阻隔板134。气体分配板132利用电绝缘体135而与腔室壁128隔离。腔室盖组件139连接至气体输送系统150。来自气体输送系统150的反应物和/或清洁气体可以通过气体信道136流入处理区域133。RF源组件191耦接至基座板131以提供用于等离子体产生的RF功率源。用于电容式(capacitive)等离子体产生的RF源通常包括一射频(RF)功率源，例如13.56MHz的RF产生器。在处理过程中，基板支撑构件162A可以接地。在基板支撑构件162A与基座板131之间的偏压电位可以点燃处理区域133中的等离子体。在等离子体中经激发的物种可以用于处理基板102。在处理过程中，基板支撑构件162A可以连接至RF产生器123，藉此，RF偏压可以施加至设置在部分基板支撑构件162A中的导电组件，以将已在处理区域122中产生的等离子体中存在的离子吸引至基板102表面。针对电容耦合等离子体反应器的更详细描述可以参见美国专利No.6,495,233，专利名称为“Apparatus for distributing gases in a chemical vapordeposition system”，在此将该专利并入以做为参考。
上述清洁腔室100和100a(图1和2)可以用于清洁半导体基板。更特定的说，本发明的清洁腔室100和100a可以用于对硅表面执行无损害的清洁。
在另一实施例中，清洁腔室可以使用微波能量源(未示出)来产生等离子体，而该等离子体可用于执行本发明所述的清洁处理。
清洁基板表面的方法
图3绘示了根据本发明一个实施例而用于清洁半导体基板的方法200的流程图。在一个实施例中，可以在上述清洁腔室100或100a中执行方法200。在一个实施例中，清洁处理通常提供一种使用等离子体清洁处理而形成干净且无损害的半导体基板表面的方法。
在步骤212，可再生(regenerate)清洁腔室(例如清洁腔室100或100a)的内表面。在一个实施例中，步骤212包括执行一蚀刻处理以移除清洁腔室的多个内表面上不期望存在的残留物质和/或污染。可执行常规溅射蚀刻和/或化学辅助蚀刻处理以再生清洁腔室的内表面，例如腔室壁或屏蔽130。
在一个实施例中，反应性气体的远程或原位等离子体可以用于移除清洁腔室的内表面上的污染。反应性气体可以选自广范围的气体，包括普遍使用的卤素及卤素化合物。举例来说，根据待移除的沉积物质，反应性气体可以为氯、氟或它们的化合物，例如三氟化氮(NF3)、四氟化碳(CF4)、六氟化硫(SF6)、六氟乙烷(C2F6)、四氯化碳(CCl4)、六氯乙烷(C2Cl6)或它们的组合。
在一个实施例中，可将诸如氩气、氮气、氦气、氢气或氧气等的载气系传送至清洁腔室的处理区域中，以帮助移除不期望存在的物种和/或协助蚀刻处理，或帮助起始及/或稳定清洁腔室中的等离子体。
在一个实施例中，可以将清洁气体传送至清洁腔室中，以蚀刻包括集除物质(将于下面讨论)的涂层，例如在清洁腔室的内表面上的硅(Si)。清洁气体可以包括加热的三氟化氮(NF3)、氯化氢(HCl)或它们的组合。在一个实施例中，常规的远程等离子体源(RPS)可以耦接至处理腔室的处理区域。RPS通常提供具有反应性的清洁剂，例如解离氟，所述反应性的清洁剂将沉积及其它处理的副产物自腔室部件移除，并利用真空泵110排出。
在步骤214，可使用遮盘或仿真基板(dummy substrate)覆盖住基板支撑构件(例如图1和2A的基板支撑构件162A)的顶表面。遮盘或仿真基板可以用于预防后续的沉积过程中(例如步骤216)在基板支撑构件上的任何沉积，藉此，待处理的基板不会与任何形成在清洁腔室内的涂层接触。覆盖住基板支撑构件也可防止当基板支撑构件为配置成在处理过程中支托基板的静电吸座时会产生的卡紧问题。
在步骤216，一个实施例中，可通过在一或多个清洁腔室部件，例如腔室壁128、屏蔽130、遮蔽环138、腔室盖129上沉积集除涂层而调理(condition)该部件。集除涂层可包括一或多种集除物质。术语“集除物质”通常是指在清洁处理之前或是清洁处理过程中用于固定和/或吸附(即，物理性吸附或化学性吸附)在清洁腔室中的任何杂质的任何物质。集除物质经选择以移除在清洁腔室中不期望存在的副产物，且不会衍生其它问题，例如新副产物的生成、产生微粒、RF功率的不期望损耗或是处理区域122中期望存在的物种的移除。在步骤216所形成的沉积集除涂层的厚度介于约
Figure BSA00000670146600091
～约1μm之间。在内表面上的涂层可用于减少或预防后续处理的基板的污染。涂层可包括纯硅物质(例如外延Si层、多晶Si层、非晶Si层)、含硅层、含锗层、和/或含有期望水平的一或多种常见掺质物质(例如硼(B)、磷(P))的硅或锗层，或它们的组合。相信由纯硅所形成的涂层对于硅基板上常见的多数污染具有强力的集除效应，而此硅基板上即将形成有外延层。硅的使用也可有利于使得微粒污染对于装置产量的效应最小化，而此微粒污染是由在经过清洁的基板表面上后续形成的外延层的金属污染所造成。在一个实例中，利用含硅烷(SiH4)的气体沉积集除涂层，将含硅烷的气体传送至处理腔室的处理区域，该处理区域的压力为约0.1～约5.0托(Torr)，RF功率介于约200瓦～约2千瓦之间，而腔室部件温度维持在约200℃～约500℃。
在一个实施例中，可将配置为集除氧气的集除物质层沉积在清洁腔室的内表面上。在一个实施例中，涂层包括厚度为约
Figure BSA00000670146600092
～约1μm的硅(Si)层。可以使用典型的CVD或ALD型处理而沉积硅涂层，该些处理将含硅前驱物传送至设置在腔室的处理区域中的加热部件。用于接收集除物质的部件可以使用外部灯、嵌设的电阻加热组件来进行加热，和/或使用RF等离子体来进行加热。
于步骤216中所沉积的集除物质的涂层能够将清洁处理中产生的不期望存在物种固定、吸收或吸附。最终，随着活性表面被覆盖或是变得反应性较差，涂层的集除能力会降低。为了补偿此问题，可以藉由重复进行步骤212、214、216而在处理区域122的部件上形成集除物质的新涂层。在一个实施例中，可于清洁腔室中处理各个基板之前，重复进行步骤212、214、216。在另一实施例中，可于清洁腔室中处理多个基板之后，重复进行步骤212、214、216。
在沉积集除物质层之后，自清洁腔室中移除遮盘、仿真盘或仿真基板。接着，将待清洁的基板放置在清洁腔室中。由于清洁腔室一般保持在真空状态下，可使基板表面上存在的污染及微粒物质(例如，氧、碳、氟、硅和氯)解吸附或是移开，以便可以利用在清洁腔室的内表面上形成的涂层而集除它们。
接着，执行一或多个氧化及蚀刻步骤(于下面讨论)来清洁基板。氧化处理用于消耗掉基板表面上已污染或已损害的硅。接着移除所形成的氧化层以暴露出新鲜且干净的硅表面。氧化处理描述于步骤220，而蚀刻步骤则描述于步骤222。
在步骤220，将氧化剂传送至清洁腔室，以在被清洁的基板的顶部层上产生氧化物。在一个实施例中，氧化剂包括臭氧(O3)，臭氧使得硅的氧化在相对低的温度下进行。在一个实施例中，将氧暴露于等离子体、紫外光(UV)能量或是等离子体与UV能量的组合，而在臭氧产生器中产生臭氧。在一个实施例中，设置UV灯145以在处理过程中，将能量传送至基板表面。在一个实施例中(未示出)，设置UV灯以通过形成在腔室壁128其中之一的通口传送UV光。针对氧化方法的详细描述可以参见美国专利申请No.2006/0223315，专利名称为“Thermally Oxidizing Silicon Using Ozone”，以及美国专利申请No.2002/0115266，专利名称为“Method and a System For SealingAn Epitaxial Silicon Layer On A Substrate”，在此将两者并入以做为参考。
在一个实施例中，利用高温氧化处理而氧化基板表面。在此实例中，在基板支撑构件(例如图1的基板支撑构件162A)上加热基板至介于约400℃～约700℃之间。在氧化过程中，清洁腔室维持在低于基板的温度。举例来说，包括有气体输送路径的清洁腔室部件(例如壁、屏蔽)维持在小于400℃，或是基本上低于400℃。在一个实施例中，基板支撑构件/加热器维持在约700℃，而清洁腔室维持在约350℃。在一个实施例中，利用流经处理腔室壁中的通道的流体而对壁进行温度控制。
在步骤222，接着进行蚀刻处理以移除在步骤220所形成的氧化物。可以使用物理、化学或物理及化学蚀刻技术的组合而进行该蚀刻处理。
在化学蚀刻的实例中，可将蚀刻气体传送至清洁腔室，并点燃等离子体以产生会与基板上的物质发生化学反应的反应性物种。反应的挥发性副产物可以藉由连接至清洁腔室的真空系统移除，和/或利用在步骤216中形成在腔室部件表面上的涂层集除。蚀刻气体可包括氯、氟或是其它适于在步骤220中将形成在基板表面的氧化物移除的其它化合物。在一个实施例中，蚀刻气体包括三氟化氮(NF3)、氯离子(Cl-)以及载气(例如氩气)。
物理蚀刻的进行藉由产生用于提供激发物种的等离子体而执行，该激发物种用于轰击基板表面，以自基板表面物理性地移除物质。在部分实例中，期望向基板支撑件提供一偏压，以加速在等离子体中形成的离子朝向基板表面移动。轰击离子藉由溅射蚀刻作用而物理性地移除基板表面上的物质。一般期望基板表面的低能量物理性轰击以减少对于基板表面的硅晶格的损害量。低功率偏压可用于移除氧化层，并且使对于基板表面的损害最小化。常规干式蚀刻处理通常用于快速移除物质，而并不需考虑到等离子体辅助物质移除处理所产生的基板物质晶格损害。因为轰击离子的高能量和/或副产物的存在，所以并不期望在执行外延沉积步骤之前用常规溅射蚀刻技术来清洁基板。更特定的说，本发明的蚀刻处理包括调整在蚀刻处理过程中形成的离子的能量，以使得在步骤222中于基板表面暴露出的结晶物质的损害最小化。在一个实施例中，藉由在具有集除物质的腔室中使用低RF功率物质移除处理，步骤222所进行的物质移除处理会在基板上形成无损害且干净的表面，而这对于在后续的沉积处理步骤中确保形成高质量外延层是十分重要的。在一个实施例中，RF产生器123适于向设置在基板支撑件162中的导电组件传送约25瓦～约500瓦的平均RF偏压功率，以执行蚀刻处理。
在方法200的替代的实施例中，步骤216是在步骤220之后且在步骤222之前进行。在此替代的实施例的一方面中，步骤220及222在不同的腔室中进行，故在执行步骤222之前，不会在氧化基板的表面上沉积集除层(步骤216)。在使用单一腔室的该替代的实施例的另一方面中，步骤220在基板上执行，接着将基板自清洁腔室中移除，以便可以置入仿真基板以允许进行步骤216而不会将集除物质涂覆在氧化基板的表面上，接着将仿真基板移除，并将氧化基板重新置入而可进行步骤222。
图4概要绘示了清洁腔室300的部分截面侧视图，该侧视图大体绘示了用于进行物理蚀刻处理的机构。清洁腔室300具有界定出处理区域302的腔室主体301。可在基板支撑件304上而位于处理区域302中设置待清洁的基板303。线圈305设置在腔室主体301的上方部分的外侧，藉以在处理区域302的上方部分中产生等离子体308。可将RF源306连接至线圈305，以提供用于产生等离子体的RF能量。偏压源307可耦接至基板支撑件304，以向基板303和/或基板支撑件304提供偏压电位。可将在等离子体308中产生的活化物种309或离子310吸引至基板303的顶表面303A，以移除在顶表面303A上的物质。
在一个实施例中，可调整活化物种309和/或离子310的能量，藉此在物质移除的过程中，不会对顶表面303A造成物理性的损害。上述调整可藉由下列方式实现：降低基板RF偏压功率；调整跨越基板施加的偏压电位；将传送至等离子体产生部件(例如感应耦合装置(例如线圈)、电容耦合装置(例如喷头、微波源))的RF功率进行脉冲；脉冲基板RF偏压功率；形成在蚀刻气体中含有轻原子物种的等离子体；使用等离子体屏蔽以限制等离子体；调整基板相对于等离子体的处理位置；和/或上述的组合。
在一个实施例中，可以藉由使用传送至基板支撑件的较低的RF偏压功率来降低活化物种的能量。在一个实施例中，可将偏压源(例如图4中的偏压源307)的功率设定为约50瓦，以将基板顶表面上的二氧化硅移除。
在一个实施例中，可将偏压源(例如图4中的偏压源307)的电位调整为较少阴极性(less cathodic)，以降低基板上的偏压。在一个实施例中，可省略偏压源，且基板设置在接地的基板支撑件上。在另一实施例中，可施加逆向偏压(reversed bias)，藉以对等离子体中的离子及反应性离子物种施加排斥力。举例来说，当清洁绝缘层上覆硅(silicon-on-insulator)基板时，可以使用逆向偏压。
在一个实施例中，可藉由脉冲RF源和/或基板偏压源来降低等离子体能量。可以藉由调整传送至等离子体产生部件(例如，线圈、喷头、微波源)的RF脉冲的占空比(duty cycle)来控制能量降低的程度。脉冲该RF源会降低由RF源产生的等离子体中的活化物种的密度。在一个实施例中，RF源经脉冲以在清洁处理过程中维持清洁腔室中的低能量等离子体。脉冲该RF源会降低在等离子体处理区域中的总等离子体及活化物种密度，因而降低轰击物种的能量及数量，以避免对基板造成损害。针对脉冲等离子体处理的详细讨论可参照美国专利申请序号NO.11/614,019(代理人案号No.APPM10983)，于2007年12月20日申请，专利名称为“Method and Apparatus forFabricating a High Dielectric Constant Transistor Gate Using a Low EnergyPlasma Apparatus”，在此将所述专利申请并入以做为参考。
在一个实施例中，蚀刻气体包括一或多种较轻的物种，所述较轻的物种用于产生低能量等离子体，以使得由物理蚀刻处理而在基板表面上产生的任何损害降低或最小化。在一个实施例中，较轻的气体物种，例如氦气(He)、氖气(Ne)、氢气(H2)或它们的组合，可以添加至包含有其它处理气体(例如氩气(Ar))的蚀刻气体中。在一个实施例中，蚀刻气体包括氩气和氦气。在另一实施例中，蚀刻气体实质包括氩气、氦气和氢气。在另一实施例中，蚀刻气体包括氩气和氢气。在另一实施例中，蚀刻气体包括氩气和氮气。在又另一实施例中，蚀刻气体实质包括氦气(He)、氖气(Ne)或氢气(H2)。
在另一实施例中，等离子体屏蔽140(图2B)在处理过程中设置在基板表面附近。图2B概要绘示了清洁腔室100的一个实施例的横截面侧视图，而该清洁腔室100包含一等离子体屏蔽140。等离子体屏蔽用于使得基板表面附近的轰击物种的数量和/或能量降低或最小化。等离子体屏蔽140为经穿孔的或是多孔的物质，所述等离子体屏蔽140允许部分的等离子体和/或处理气体在处理过程中通过。在一个实施例中，穿孔为穿过等离子体屏蔽的多个孔洞141。在一个实施例中，等离子体屏蔽由介电材料制成，或是涂覆有介电材料，而所述介电材料与等离子体及处理气体兼容(例如，石英、SiO2)。在一个实施例中，等离子体屏蔽由与腔室其它部件相同的材料制成，例如制成腔室盖129或腔室壁128的材料。在一个实施例中，等离子体屏蔽由选自由硅、钇、氧化钇、锗、硼、磷及硅锗化合物所组成组的材料制成。
在另一实施例中，可调整被处理的基板与清洁腔室中所产生的等离子体的相对位置，以调整等离子体中的离子或活化物种对基板表面轰击的量。相似的调整方式描述于共同受让的美国专利申请No.2006/0105114，专利名称为“Multi-Layer High Quality Gate Dielectric for Low-Temperature Poly-SiliconTFTs”，在此将该专利申请并入以做为参考。
回到图3，步骤222的示范性蚀刻处理可以在类似于图1的清洁腔室100的清洁腔室中进行，以移除在基板的顶表面上形成的氧化硅。在处理过程中，腔室压力维持在约1mTorr～约1Torr。在一个实施例中，腔室压力维持在约20mTorr～约800mTorr。可向处理区域提供包括氦气及氩气的蚀刻气体。在一个实施例中，腔室压力为约5mTorr～约20mTorr，且蚀刻气体主要包括氦气。也可将被处理的基板加热至高达约700℃。清洁腔室可以维持在约20℃～约400℃。在一个实施例中，腔室维持在约30℃的温度。相信将腔室壁维持在较低温度下可以协助减少腔室壁的腐蚀。
回到图3，可以重复步骤220、222一或多次直到基板干净为止。一旦清洁完基板表面，则接着在经过清洁的基板表面上进行步骤224和/或步骤226。
在步骤224，在经过清洁的基板上执行钝化处理，以便在后续外延沉积处理前基板会保持干净。在一个实施例中，钝化处理包括流入钝化气体并产生钝化气体的等离子体。在一个实施例中，钝化气体包括具有稀释浓度的氢气(H2)，所述钝化气体利用氢来终结(terminate)经过清洁的硅表面。在一个实施例中，钝化处理包括传送包含约1％氢气的含氢气体，且同时基板维持在约50～500℃的温度。
在步骤226，于外延腔室中，在经过清洁的基板上生长外延硅层。为了使用CVD工艺生长硅外延层，基板放置在设定于升高温度(例如约500℃～800℃)以及降低压力状态或大气压力下的外延腔室中。在维持于升高温度及降低压力状态下的同时，将含硅气体(例如单硅烷气体或二氯硅烷气体)供应至外延腔室中，并利用气相生长以生长硅外延层，而形成具有与基板(半导体层生长在该基板上)相同的结晶取向的半导体层。该工艺可以在压力介于约0.1Torr～约760Torr之间操作。用于沉积含硅薄膜的硬件包括购自加州圣克拉拉的应用材料公司(Applied Materials，Inc.)的Epi Centura RTM系统以及Poly Gen RTM系统。针对外延腔室的详细描述可参照美国专利申请序号No.11/767,619，专利名称为“Modular CVD EPI 300mm Reactor”，于2007年6月25日申请，在此将所述专利申请并入以做为参考。
方法200可以在包括有清洁腔室及外延腔室的群集式工具(cluster tool)中进行。在常规配置中，基板在进行常规的清洁处理(例如湿式清洁处理)之后，必须等待一段时间，然后才可进入外延沉积腔室以形成外延层。等待的过程会影响基板表面的洁净度，因而对晶圆与晶圆之间的处理结果造成影响。在一个实施例中，安排完成步骤224以及后续外延层沉积处理(即，步骤226)之间的时间，以便基板可以在完成钝化处理之后立即转移至外延腔室。使用控制处理时间或时间安排的控制器147可以增进处理的可重复性及装置产量。在一个实施例中，可以于步骤224之前加入排队步骤(queuingstep)，以排除钝化之后的等待。在另一实施例中，直到控制器147确认外延沉积室已准备好在步骤222和/或步骤224完成时接收基板之后，才会开始步骤222和/或步骤224。
在一个实施例中，步骤220在第一清洁腔室100中进行，而步骤222在第二清洁腔室100中进行，以减少步骤220与步骤222对彼此之间的影响。在一个实施例中，第一清洁腔室100可进行步骤212～220，而第二清洁腔室100可进行步骤212～216及步骤222～224。
控制器147一般设计成促进第一清洁腔室100及系统400(图5)的控制及自动化操作，并典型地包括中央处理单元(CPU)(未示出)、内存(未示出)及支持电路(或I/O)(未示出)。CPU可以为任一形式的计算机处理器，并可用于控制各腔室工艺及硬件(例如：监测器、马达、流体输送硬件等)的工业设定，并监控系统及腔室工艺(例如：基板位置、处理时间、监测器信号等)。内存连接至CPU，并可以为一或多种易于存取的内存，例如随机存取内存(RAM)、只读存储器(ROM)、软盘、硬盘或是其它任何形式的数字存储器，且可为本地的或是远程的。软件指令及数据可经过编码并储存在内存中，以提供CPU指令。支持电路也以常规方式连接至CPU以支持处理器。支持电路可以包括高速缓冲存储器(cache)、电源供应、时钟电路、输入/输出电路、子系统(subsystem)等。可以由控制器147所读取的程序(或计算机指令)决定可在基板上执行何种任务。优选地，程序为可以由控制器147读取的软件，所述程序包括用于产生及储存至少有工艺配方顺序、基板位置信息、多个受控部件的移动顺序、工艺控制、工艺时间、时间安排、排队步骤及它们的任何组合的编码。
群集式工具
图5绘示了根据本发明一个实施例的用于半导体处理的群集式工具400的平面视图。群集式工具为一模块式的系统，所述系统包括多个腔室，以在半导体制造过程中执行多项功能。群集式工具400包括中央传输室401，该中央传输室401透过一对加载锁定真空室405(load-lock chamber)而连接至前端环境404。工厂界面机械手408A、408B设置在前端环境404中，并配置以将基板传送于加载锁定真空室405及多个装设在前端环境404的舱(pod)403之间。
多个腔室407、408、409及410装设至中央传输室401以执行期望的工艺。中央机械手406设置在中央传输室401中，并配置以将基板传送于加载锁定真空室405及腔室407、408、409、410之间，或是腔室407、408、409、410之间。
在一个实施例中，群集式工具400包括清洁腔室(例如图1的清洁腔室100)以及二个外延腔室407、408。腔室410可以为清洁腔室，例如图1所述的清洁腔室100。腔室410配置以在外延生长工艺之前用于清洁基板。腔室407、408为能够进行外延生长工艺的外延腔室。示范性的外延腔室描述于美国专利申请序号NO.11/767,619(代理人案号No.10394)，专利名称为“Modular CVD EPI 300mm Reactor”，于2007年6月25日申请，在此将所述专利申请并入以做为参考。
群集式工具400可以用于执行上述方法200。在处理过程中，待处理的基板到达群集式工具400的舱403。接着利用工厂界面机械手408A或408B而将基板由舱403传送至真空兼容的加载锁定真空室405。接着传输室401中的中央机械手406拾取基板，而传输室401一般保持在真空状态下。中央机械手406将基板装载至清洁腔室410中，而清洁腔室410的内表面已按方法200的步骤212、214、216所述进行再生并涂覆。可以在清洁腔室410中对基板进行包括方法200的步骤220、222、224的清洁处理。中央机械手406接着自清洁腔室410拾取基板，并将该基板装载至外延腔室407或408(视可利用的腔室而定)。在外延腔室407或408中于已经过清洁的基板上生长外延层。
在一个实施例中，配置群集式工具400而包含有位于腔室409及腔室410的位置(图5)的二个清洁腔室100(或100a)，和位于腔室407或腔室408的位置的二个外延腔室。如上所提及，在此配置中，于外延腔室407或408中进行外延层沉积步骤226之前，期望在一个清洁腔室(例如腔室410)中执行步骤220，并且在另一个清洁腔室(例如腔室409)中执行步骤222及224。
在另一实施例中，群集式工具包括等离子体浸没离子注入(P3I)腔室。举例来说，腔室409为P3I腔室，该P3I腔室配置以将一或多种掺质注入基板上的外延层中。示范性的P3I腔室描述于美国专利NO.6,939,434，专利名称为“Externally Excited Torroidal Plasma Source with Magnetic Control of IonDistribution”，以及美国专利No.6,893,907号，专利名称为“Fabrication ofSilicon-on-Insulator Structure Using Plasma Immersion Ion Implantation”，在此皆将所述专利并入以做为参考。
本发明虽然以较佳实施例说明如上，然而所述实施例并非用以限定本发明，任何熟练技术人员，在不脱离本发明的精神和范围内所作的修改与修饰，仍应属本发明的技术范畴，而本发明的技术范畴由下附权利要求所界定。

Claims (25)

1.一种处理半导体基板的方法，包括：
将基板放置在处理腔室的处理区域内；
将设置在所述处理腔室中的基板的表面暴露于含氧气体中以在所述表面上形成第一含氧层；
自所述基板的至少一部分表面移除所述第一含氧层的至少一部分；以及
将所述基板的所述表面暴露于含氧气体中以在所述表面上形成第二含氧层。
2.根据权利要求1所述的方法，其中形成所述第一含氧层、移除所述第一含氧层的至少一部分以及形成所述第二含氧层全部是在所述处理腔室中执行。
3.根据权利要求1所述的方法，进一步包括：
自所述基板的表面移除所述第二含氧层的至少一部分；以及
在所述基板的至少一部分表面上沉积外延层。
4.根据权利要求3所述的方法，进一步包括：
自所述基板的表面移除所述第二含氧层的至少一部分，其中形成所述第一含氧层、移除所述第一含氧层的至少一部分、形成所述第二含氧层以及移除所述第二含氧层的至少一部分都是在将所述基板自所述处理腔室移除之前执行。
5.根据权利要求1所述的方法，进一步包括：
在将所述基板放置在所述处理区域之前，在设置在所述处理腔室的处理区域中的腔室部件的表面上形成集除层。
6.根据权利要求5所述的方法，其中所述集除层包括选自由硅和锗所组成组的材料。
7.根据权利要求1所述的方法，其中所述含氧气体包括氧气。
8.根据权利要求1所述的方法，其中所述含氧气体包括臭氧。
9.根据权利要求1所述的方法，其中形成所述第一含氧层或形成所述第二含氧层包括将所述基板暴露于紫外光。
10.一种处理半导体基板的方法，包括：
将基板放置在处理腔室的处理区域内；
将设置在所述处理腔室中的基板的表面暴露于含氧气体中以在所述表面上形成第一含氧层；
自所述基板的至少一部分表面移除所述第一含氧层的至少一部分；以及
将所述基板的所述表面暴露于含氧气体中以在所述表面上形成第二含氧层，其中形成所述第一含氧层、移除所述第一含氧层的至少一部分以及形成所述第二含氧层全部是在所述处理腔室中执行。
11.根据权利要求10所述的方法，进一步包括：
自所述基板的表面移除所述第二含氧层的至少一部分；以及
在所述基板的至少一部分表面上沉积外延层。
12.根据权利要求10所述的方法，进一步包括：
在将所述基板放置在处理区域之前，在设置在所述处理腔室的处理区域中的腔室部件的表面上形成集除层。
13.根据权利要求10所述的方法，其中所述含氧气体包括氧气。
14.根据权利要求10所述的方法，其中所述含氧气体包括臭氧。
15.根据权利要求10所述的方法，其中形成所述第一含氧层或形成所述第二含氧层包括将所述基板暴露于紫外光。
16.一种处理半导体基板的方法，包括：
将基板放置在处理腔室的处理区域内；
通过将设置在所述处理腔室的基板的表面暴露于含氧气体中以在所述基板上形成第一氧化层来氧化所述基板的表面；
自所述基板的至少一部分表面移除所述第一氧化层的至少一部分；以及
再氧化所述基板的表面以在所述基板的所述表面上形成第二氧化层，其中形成所述第一氧化层、移除所述第一氧化层的至少一部分以及再氧化所述表面全部是在所述处理腔室中执行。
17.根据权利要求16所述的方法，其中形成所述第一氧化层或形成所述第二氧化层包括将所述基板暴露于紫外光。
18.根据权利要求17所述的方法，其中所述含氧气体包括氧气。
19.权利要求17所述的方法，其中所述含氧气体包括臭氧。
20.根据权利要求17所述的方法，进一步包括：
自所述基板的表面移除所述第二氧化层的至少一部分；以及
在所述基板的至少一部分表面上沉积外延层。
21.一种处理基板的装置，包括：
低能量清洁腔室，所述低能量清洁腔室包括：
形成处理区域的一或多个壁；
适于传送电磁能至所述处理区域的等离子体产生源；
适于传送含硅气体或含锗气体至所述处理区域的第一气源；
适于传送氧化气体至所述处理区域的第二气源；
适于传送蚀刻气体至所述处理区域的蚀刻气体源；以及
基板支撑件，具有基板支撑表面、适于被RF功率源所偏压的偏压电极以及用于控制基板支撑表面温度的基板支撑件热交换装置；
外延层沉积腔室，包括：
形成处理区域的一或多个壁；以及
适于传送含硅气体至所述处理区域的第一气源；
传输室，所述传输室具有围出传输区域的一或多个壁以及所述传输室具有适于在低能量清洁腔室中的第一位置和外延层沉积腔室中的第一位置之间传输基板的机械手。
22.根据权利要求21所述的装置，进一步包括设置在所述基板支撑表面和在处理区域中产生的等离子体的实质部分之间的屏蔽，其中所述屏蔽中形成有多个孔洞并且所述屏蔽是由选自由硅、钇、氧化钇、锗、硼、磷及硅锗组成的组的材料形成。
23.根据权利要求21所述的装置，其中自所述第二气体源传送的所述蚀刻气体包括氦气、氢气或氖气。
24.根据权利要求21所述的装置，进一步包括紫外光源，所述紫外光源被设置为将一或多种波长的紫外光传送给设置在所述基板支撑表面上的基板。
25.根据权利要求21所述的装置，其中所述等离子体产生源适于将多种RF能量脉冲传送给所述处理区域。
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