CN102569359B - The horizontal double-diffused device of partial SOI - Google Patents
The horizontal double-diffused device of partial SOI Download PDFInfo
- Publication number
- CN102569359B CN102569359B CN201210047316.7A CN201210047316A CN102569359B CN 102569359 B CN102569359 B CN 102569359B CN 201210047316 A CN201210047316 A CN 201210047316A CN 102569359 B CN102569359 B CN 102569359B
- Authority
- CN
- China
- Prior art keywords
- type impurity
- oxygen buried
- buried layer
- source electrode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention relates to SOI technology.The invention solves the obvious problem of existing conventional SOI device self-heating effect, provide the horizontal double-diffused device of a kind of partial SOI, its technical scheme can be summarized as: the horizontal double-diffused device of partial SOI, its oxygen buried layer one end is positioned at below source electrode and contacts with device edge, the other end is not less than zero with the horizontal range of drain electrode Second-Type impurity ohmic contact regions, the other end of oxygen buried layer to drain electrode below device edge between, the first type impurity substrate contacts with Second-Type impurity top silicon layer and forms PN junction.The invention has the beneficial effects as follows, its oxygen buried layer, in drain electrode lower opening, effectively can transmit the heat that SOI device produces, be applicable to SOI device.
Description
The application is application number is 201010579250.7, and the applying date is on December 8th, 2010, and name is called the divisional application of the patent application of the horizontal double-diffused device of partial SOI.
Technical field
The present invention relates to SOI technology, particularly the horizontal double-diffused device of SOI.
Background technology
SOI (Silicon on Insulator) technology is described as " the silicon integrated circuit technology of 21 century ", it is one of mainstream technology of integrated circuit of new generation, be widely used in integrated low-voltage high performance chips as ultrahigh speed processor at present, thin film SOI is the Fully dielectric isolation device adopting LOCOS technique, thin film SOI adopts the isolation of LOCOS technique, there is not the preparation of trap, selective oxidation just can realize the formation of silicon island, decrease the area of isolated area to a great extent, but longitudinal withstand voltage of conventional SOI device is determined by drift region and oxygen buried layer, its serious self-heating effect limits its development, the people such as Park propose the form of partial SOI device architecture, due to the existence of silicon window, drift region is connected with substrate, depletion layer is expanded to substrate, part is assume responsibility for withstand voltage after substrate is exhausted, add the withstand voltage length of longitudinal direction of device, and along with the reduction of substrate concentration, longitudinally withstand voltage further increase, SOI device puncture voltage is determined by the smaller of vertical and horizontal voltage, conventional SOI device is in order to improve its puncture voltage, Withstand voltage layer all exhausts, drift region doping must be lower, longitudinally withstand voltage by drift region under drain terminal face and the decision of oxygen buried layer thickness, regular section SOI device is all identical to the drift region thickness of drain electrode from source electrode, and surface field is not optimised, although the longitudinally withstand voltage restriction of conventional SOI broken by partial SOI device, but its surface field must meet RESURF principle, surface field there will be distribution shape low between the senior middle school of two ends, Second-Type impurity device drift region is not fully optimized, and the limitation of RESURF own limits Electric Field Modulated in its drift region, Second-Type impurity device drift region Electric Field Distribution can not be improved, as shown in Figure 1, conventional SOI device comprises source electrode, drain electrode, first type impurity substrate 1, oxygen buried layer 2 and Second-Type impurity top silicon layer 3, described Second-Type impurity top silicon layer 3 comprises the first type impurity backgate contact zone 7, source electrode Second-Type impurity ohmic contact regions 6, Second-Type impurity device drift region 5 and drain electrode Second-Type impurity ohmic contact regions 4, described first type impurity substrate 1 arranges in the horizontal plane, oxygen buried layer 2 is arranged in the first type impurity substrate 1, Second-Type impurity device drift region 5 is arranged on oxygen buried layer 2, first type impurity substrate 1 is carried out electrical equipment isolation with Second-Type impurity top silicon layer 3 by oxygen buried layer 2, first type impurity backgate contact zone 8 and source electrode Second-Type impurity ohmic contact regions 7 mutually arranged side by side, be arranged on Second-Type impurity device drift region 5 upper surface near the position of source electrode, described drain electrode Second-Type impurity ohmic contact regions 4 is arranged on the position of Second-Type impurity device drift region 5 upper surface near drain electrode, wherein the first type impurity is p-type impurity or N-shaped impurity, Second-Type impurity is N-shaped impurity or p-type impurity.
Summary of the invention
The object of the invention is to overcome the obvious shortcoming of current conventional SOI device self-heating effect, provide a kind of partial SOI horizontal double-diffused device.
The present invention solves its technical problem, the technical scheme adopted is, the horizontal double-diffused device of partial SOI, comprise source electrode, drain electrode, first type impurity substrate, oxygen buried layer and Second-Type impurity top silicon layer, described Second-Type impurity top silicon layer comprises drain electrode Second-Type impurity ohmic contact regions and source electrode Second-Type impurity ohmic contact regions, described first type impurity substrate is arranged on horizontal plane, it is characterized in that, described oxygen buried layer one end is positioned at below source electrode and contacts with device edge, the other end is not less than zero with the horizontal range of drain electrode Second-Type impurity ohmic contact regions, the other end of oxygen buried layer to drain electrode below device edge between, first type impurity substrate contacts with Second-Type impurity top silicon layer and forms PN junction.
Concrete, described oxygen buried layer is pantostrat or is divided into n section between passing through, and the spacing between every two adjacent sections is greater than zero, has the PN junction that the first type impurity substrate and Second-Type impurity top silicon layer are formed in described spacing.
Further, described spacing increases from one end of the source electrode of oxygen buried layer successively to the one end near drain electrode, described section reduces from one end of oxygen buried layer source electrode successively to the one end near drain electrode, and the length of first section from oxygen buried layer source electrode one end is greater than the horizontal range of source electrode Second-Type impurity ohmic contact regions to source electrode.
Concrete, also comprise Second-Type impurity floating layer, described Second-Type impurity floating layer is horizontally set in the first type impurity substrate, and its one end is positioned at drain electrode below and contacts with device edge, and the horizontal range of the other end and source electrode Second-Type impurity ohmic contact regions is not less than zero.
Further, also comprise Second-Type impurity floating layer, described Second-Type impurity floating layer is horizontally set in the first type impurity substrate, its one end is positioned at drain electrode below and contacts with device edge, the horizontal range of the other end and source electrode Second-Type impurity ohmic contact regions is not less than zero, described spacing all has Second-Type impurity floating layer in the floor projection of Second-Type impurity floating aspect, and the horizontal range between the other end of the described Second-Type impurity floating layer device edge below source electrode is less than the length of first section from one end below oxygen buried layer source electrode.
Concrete, the concentration of described Second-Type impurity floating layer is 1e16cm
-3to 2e17cm
-3, its thickness is 1 μm to 5 μm, and the vertical range of itself and the first type impurity substrate upper surface is 3 μm to 15 μm.
Further, described first type impurity is p-type impurity or N-shaped impurity, and Second-Type impurity is N-shaped impurity or p-type impurity.
The invention has the beneficial effects as follows, by the horizontal double-diffused device of above-mentioned partial SOI, its oxygen buried layer is in drain electrode lower opening, effectively can transmit the heat that SOI device produces, the PN junction that formed for the first type impurity substrate and Second-Type impurity top silicon layer of drain electrode below simultaneously, wherein, first type impurity substrate doping content is lower, depletion layer can be extended to substrate, and owing to adding Second-Type impurity floating layer, it has shared oxygen buried layer electric field, electric field in oxygen buried layer is significantly reduced, thinner oxygen buried layer can be used to meet high tension apparatus, further reduce the self-heating effect of SOI device, simultaneously, Second-Type impurity floating layer can be modulated for electric field in drift region, strengthen drift region zone line electric field, compare conventional SOI device, it can obtain larger puncture voltage.
Accompanying drawing explanation
Fig. 1 is conventional SOI device cutaway view;
Fig. 2 is the horizontal double-diffused device oxygen buried layer of partial SOI of the present embodiment is the cutaway view of consecutive hours;
Fig. 3 be the horizontal double-diffused device oxygen buried layer of partial SOI of the present embodiment from one end of source electrode to the one end near drain electrode cutaway view when being divided into n section;
Fig. 4 is conventional SOI device equipotential lines distribution map when puncturing;
Fig. 5 is the horizontal double-diffused device of partial SOI of the present embodiment equipotential lines distribution map when puncturing;
Fig. 6 is the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment lateral surfaces Field distribution characteristic curve when puncturing;
Fig. 7 is the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment longitudinal electric field distribution character curve when puncturing;
Fig. 8 is the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment characteristic curve when puncturing;
Wherein, 1 is the first type impurity substrate, 2 is oxygen buried layer, 3 is Second-Type impurity top silicon layer, and 4 is drain electrode Second-Type impurity ohmic contact regions, and 5 is Second-Type impurity device drift region, 6 is source electrode Second-Type impurity ohmic contact regions, 7 is the first type impurity backgate contact zone, and 8 is Second-Type impurity floating layer, and 21 is first section from oxygen buried layer source electrode one end.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.
The horizontal double-diffused device of partial SOI of the present invention, first type impurity substrate 1 is not carried out electrical isolation with Second-Type impurity top silicon layer 3 by its oxygen buried layer 2 completely, one end of oxygen buried layer 2 is positioned at below source electrode and contacts with device edge, the other end is not less than zero with the horizontal range of drain electrode Second-Type impurity ohmic contact regions 4, the other end of oxygen buried layer 2 to drain electrode below device edge between, first type impurity substrate 1 contacts with Second-Type impurity top silicon layer 3 and forms PN junction, because its oxygen buried layer 2 is in drain electrode lower opening, effectively can transmit the heat that SOI device produces.
Embodiment
The oxygen buried layer 2 of the horizontal double-diffused device of the partial SOI of this example can be pantostrat or interruption be divided into n section, its oxygen buried layer is that the cutaway view of consecutive hours is as Fig. 2, oxygen buried layer is divided into cutaway view during n section as Fig. 3 from one end of source electrode to the one end near drain electrode, when conventional SOI device punctures, equipotential lines distribution map is as Fig. 4, when the horizontal double-diffused device of partial SOI of the present embodiment punctures, equipotential lines distribution map is as Fig. 5, when the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment punctures, lateral surfaces Field distribution characteristic curve is as Fig. 6, when the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment punctures, longitudinal electric field distribution character curve is as Fig. 7, when the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment punctures, characteristic curve is as Fig. 8.
First type impurity substrate 1 is not carried out electrical isolation with Second-Type impurity top silicon layer 3 by the oxygen buried layer 2 of the horizontal double-diffused device of this partial SOI completely, one end of oxygen buried layer 2 is positioned at below source electrode and contacts with device edge, the other end is not less than zero with the horizontal range of drain electrode Second-Type impurity ohmic contact regions 4, the other end of oxygen buried layer 2 to drain electrode below device edge between, first type impurity substrate 1 contacts with Second-Type impurity top silicon layer 3 and forms PN junction, it can be pantostrat that its oxygen buried layer 2 passes through, also can from its one end to the other end be divided into n section, spacing between every two adjacent sections is greater than zero, there is in spacing the first type impurity substrate 1 and contact with Second-Type impurity top silicon layer 3 PN junction formed, its spacing increases from one end of oxygen buried layer 2 successively to the other end, described section reduces from oxygen buried layer 2 one end successively to the other end, the length of first section 21 from one end below oxygen buried layer 2 source electrode is greater than the horizontal range of source electrode Second-Type impurity ohmic contact regions 6 to source electrode, Second-Type impurity floating layer 11 has also been horizontally disposed with in the first type impurity substrate 1, one end of second impurity floating layer 8 is positioned at drain electrode below and contacts with device edge, the horizontal range of the other end and source electrode Second-Type impurity ohmic contact regions 6 is not less than zero, when oxygen buried layer 2 for be interrupted be divided into n section time, its spacing all has Second-Type impurity floating layer 8 in the floor projection of 8, Second-Type impurity floating layer, horizontal range between the other end of Second-Type impurity floating layer 8 device edge below source electrode is less than the length of first section 21 from one end below oxygen buried layer 2 source electrode, the concentration of Second-Type impurity floating layer 8 is 1e16cm
-3to 2e17cm
-3, its thickness is 1 μm to 5 μm, and the vertical range of Second-Type impurity floating layer 8 to the first type impurity substrate 1 upper surface is 3 μm to 15 μm, when the first type impurity is p-type impurity, Second-Type impurity is N-shaped impurity, and when the first type impurity is N-shaped impurity, Second-Type impurity is p-type impurity.
When conventional SOI device punctures, equipotential lines distribution map is as Fig. 4, its adjacent equipotential lines voltage difference is 10V, as can be seen from Figure 4 to assume responsibility for the longitudinal direction of SOI device withstand voltage for the oxygen buried layer 2 of SOI device, electric field in its Second-Type impurity device drift region 5 is sparse, and this SOI device fails to reach making full use of of Second-Type impurity device drift region 5, when the horizontal double-diffused device of partial SOI of the present embodiment punctures, equipotential lines distribution map is as Fig. 5, its adjacent equipotential lines voltage difference is 10V, equipotential lines is no longer subject to oxygen buried layer 2 and limits as can be seen from Figure 5, it " can pass " oxygen buried layer 2, the first type impurity substrate 1 is made to bear device longitudinally withstand voltage, break its withstand voltage restriction being subject to oxygen buried layer 2 thickness of conventional SOI device, Second-Type impurity floating layer 8 is modulated for the electric field in Second-Type impurity device drift region 5 simultaneously, the electric field in Second-Type impurity device drift region 5 is impelled to distribute again, make the horizontal double-diffused device transverse electric field distribution of this partial SOI more even, the horizontal double-diffused device of this partial SOI has larger puncture voltage, when the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment punctures, lateral surfaces Field distribution characteristic curve is as Fig. 6, wherein, X-axis represents horizontal direction distance, Y-axis represents electric field, can find out that from Fig. 6 the horizontal double-diffused device of partial SOI that the present embodiment provides receives the modulation of Second-Type impurity floating layer 8 to it due to surface field, its distribution is obviously more even, and the LDMOS device integrated compared to conventional SOI technology has shown huge advantage, when the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment punctures, longitudinal electric field distribution character curve is as Fig. 7, wherein, X-axis represents vertical direction distance, Y-axis represents electric field, oxygen buried layer 2 electric field is down to 2.5E5V/cm from the 8.5E5V/cm of conventional SOI device by the horizontal double-diffused device of partial SOI that the present embodiment provides as can be seen from Figure 7, simultaneously depletion width has had and has increased substantially, so identical puncture voltage demand will be reached, the horizontal double-diffused device of the partial SOI that the present embodiment provides just can reach requirement with thinner oxygen buried layer 2 thickness, add horizontal its oxygen buried layer 2 of double-diffused device of partial SOI that the present embodiment provides in drain electrode perforate, the heat produced in this devices function can be transmitted to the first type impurity substrate 1, so it has less self-heating effect, when the horizontal double-diffused device of partial SOI of conventional SOI device and the present embodiment punctures, characteristic curve is as Fig. 8, wherein, X-axis represents drain voltage, Y-axis represents drain current, can find out because Second-Type impurity floating layer 8 is for the modulating action of transverse electric field and longitudinal electric field in Second-Type impurity device drift region 5 from Fig. 8, make the horizontal double-diffused device of the partial SOI of the present embodiment obtain 445V puncture voltage, and conventional SOI device puncture voltage only have 315V.
Claims (4)
1. the horizontal double-diffused device of partial SOI, comprise source electrode, drain electrode, first type impurity substrate, oxygen buried layer and Second-Type impurity top silicon layer, described Second-Type impurity top silicon layer comprises drain electrode Second-Type impurity ohmic contact regions and source electrode Second-Type impurity ohmic contact regions, described first type impurity substrate is arranged on horizontal plane, it is characterized in that, described oxygen buried layer one end is positioned at below source electrode and contacts with device edge, the other end is not less than zero with the horizontal range of drain electrode Second-Type impurity ohmic contact regions, the other end of oxygen buried layer to drain electrode below device edge between, first type impurity substrate contacts with Second-Type impurity top silicon layer and forms PN junction, n section is divided between described oxygen buried layer passes through, spacing between every two adjacent sections is greater than zero, there is in described spacing the first type impurity substrate contact with Second-Type impurity top silicon layer and form PN junction.
2. the horizontal double-diffused device of partial SOI according to claim 1, it is characterized in that, described spacing increases from one end of oxygen buried layer successively to the other end, described section reduces from one end of oxygen buried layer successively to the other end, and the length of first section from one end below oxygen buried layer source electrode is greater than the horizontal range of source electrode Second-Type impurity ohmic contact regions to source electrode.
3. the horizontal double-diffused device of partial SOI according to claim 1 or 2, it is characterized in that, also comprise Second-Type impurity floating layer, described Second-Type impurity floating layer is horizontally set in the first type impurity substrate, its one end is positioned at drain electrode below and contacts with device edge, the horizontal range of the other end and source electrode Second-Type impurity ohmic contact regions is not less than zero, described spacing all has Second-Type impurity floating layer in the floor projection of Second-Type impurity floating aspect, horizontal range between the other end of the described Second-Type impurity floating layer device edge below source electrode is less than the length of first section from one end below oxygen buried layer source electrode.
4. the horizontal double-diffused device of partial SOI according to claim 3, it is characterized in that, the concentration of described Second-Type impurity floating layer is 1e16cm
-3to 2e17cm
-3, its thickness is 1 μm to 5 μm, and the vertical range of itself and the first type impurity substrate upper surface is 3 μm to 15 μm.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105792507A CN102082169B (en) | 2010-12-08 | 2010-12-08 | Partial SOI (silicon on insulator) traverse double-diffusion device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105792507A Division CN102082169B (en) | 2010-12-08 | 2010-12-08 | Partial SOI (silicon on insulator) traverse double-diffusion device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102569359A CN102569359A (en) | 2012-07-11 |
| CN102569359B true CN102569359B (en) | 2015-07-29 |
Family
ID=44088021
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210047316.7A Active CN102569359B (en) | 2010-12-08 | 2010-12-08 | The horizontal double-diffused device of partial SOI |
| CN2010105792507A Active CN102082169B (en) | 2010-12-08 | 2010-12-08 | Partial SOI (silicon on insulator) traverse double-diffusion device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105792507A Active CN102082169B (en) | 2010-12-08 | 2010-12-08 | Partial SOI (silicon on insulator) traverse double-diffusion device |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN102569359B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103545346B (en) * | 2012-07-09 | 2016-11-16 | 上海华虹宏力半导体制造有限公司 | Isolated form N-type LDMOS device and manufacture method thereof |
| CN103426913B (en) * | 2013-08-09 | 2016-08-31 | 电子科技大学 | A kind of partial SOI ultra-junction high-voltage power semiconductor device |
| CN103515428B (en) * | 2013-09-09 | 2015-12-09 | 电子科技大学 | The horizontal high voltage power semiconductor device of a kind of PSOI |
| JP6591312B2 (en) * | 2016-02-25 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US10930777B2 (en) * | 2017-11-21 | 2021-02-23 | Globalfoundries U.S. Inc. | Laterally double diffused metal oxide semiconductor (LDMOS) device on fully depleted silicon on insulator (FDSOI) enabling high input voltage |
| CN108447904B (en) * | 2018-03-14 | 2020-09-29 | 电子科技大学 | Manufacturing method of transverse IGBT |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281054B1 (en) * | 1998-12-30 | 2001-08-28 | Hyundai Electronics Industries Co., Ltd. | SOI device and method for fabricating the same |
| US6319772B1 (en) * | 2000-10-30 | 2001-11-20 | Chartered Semiconductor Manufacturing Ltd. | Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer |
| CN101621009A (en) * | 2008-07-02 | 2010-01-06 | 中国科学院微电子研究所 | Method for manufacturing body-contact structure of partially depleted SOI MOSFET |
| CN101777584A (en) * | 2010-01-29 | 2010-07-14 | 四川长虹电器股份有限公司 | P-channel laterally double diffused metal oxide semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100593733B1 (en) * | 2003-12-18 | 2006-06-28 | 삼성전자주식회사 | DRAM cell adopting asymmetric buried insulating film and method of manufacturing the same |
| CN101488526A (en) * | 2009-02-27 | 2009-07-22 | 东南大学 | N type SOI lateral double-diffused metal-oxide semiconductor transistor |
| CN101552291B (en) * | 2009-03-30 | 2012-02-01 | 东南大学 | Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels |
-
2010
- 2010-12-08 CN CN201210047316.7A patent/CN102569359B/en active Active
- 2010-12-08 CN CN2010105792507A patent/CN102082169B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281054B1 (en) * | 1998-12-30 | 2001-08-28 | Hyundai Electronics Industries Co., Ltd. | SOI device and method for fabricating the same |
| US6319772B1 (en) * | 2000-10-30 | 2001-11-20 | Chartered Semiconductor Manufacturing Ltd. | Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer |
| CN101621009A (en) * | 2008-07-02 | 2010-01-06 | 中国科学院微电子研究所 | Method for manufacturing body-contact structure of partially depleted SOI MOSFET |
| CN101777584A (en) * | 2010-01-29 | 2010-07-14 | 四川长虹电器股份有限公司 | P-channel laterally double diffused metal oxide semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102569359A (en) | 2012-07-11 |
| CN102082169B (en) | 2012-07-25 |
| CN102082169A (en) | 2011-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102569359B (en) | The horizontal double-diffused device of partial SOI | |
| CN104201206B (en) | A kind of laterally SOI power LDMOS device | |
| CN102403315B (en) | Semiconductor device | |
| CN103050540B (en) | Use the lateral power of the low conduction resistance of high-dielectric constant groove structure | |
| CN103268890B (en) | A kind of power LDMOS device with junction type field plate | |
| CN102969358B (en) | A kind of horizontal high voltage power semiconductor device | |
| CN105633137B (en) | A kind of slot gate power MOSFET device | |
| US11145755B2 (en) | Silicon carbide semiconductor component with edge termination structure | |
| CN103715238A (en) | Transverse high-voltage component with ultra-low specific on-resistance | |
| CN105070759A (en) | Nldmos device and manufacturing method thereof | |
| CN108292677A (en) | A kind of folder-type terminal with internal field plate | |
| CN103928522B (en) | A kind of grooved accumulation layer MOSFET element | |
| CN102386211A (en) | LDMOS device and fabrication method thereof | |
| CN102130150A (en) | Junction terminal structure of semiconductor device | |
| JP2013069866A (en) | Semiconductor device | |
| CN103022134B (en) | A kind of horizontal high voltage power device of SOI of Ultra-low Specific conducting resistance | |
| CN103681826A (en) | Power semiconductor device | |
| CN102376762A (en) | Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN109087952A (en) | With low separate gate VDMOS device and manufacturing method than conducting resistance | |
| CN101573800B (en) | PN junction and MOS capacitor hybrid resurf transistor | |
| CN103545346A (en) | Isolated N-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN102694010A (en) | Semiconductor device | |
| CN108682691A (en) | The manufacturing method and semiconductor devices of transverse diffusion metal oxide semiconductor device | |
| CN102142460A (en) | SOI (Silicon On Insulator) type P-LDMOS (Lateral Diffused Metal-Oxide Semiconductor) | |
| CN107359194B (en) | Device for eliminating high electric field |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |