CN102609027A - Band-gap reference voltage source circuit - Google Patents

Abstract

An embodiment of the invention discloses a band-gap reference voltage source circuit which comprises a first p-channel metal oxide semiconductor (PMOS) pipe, a second PMOS pipe, a third PMOS pipe, a fourth PMOS pipe, a first NPN type triode, a second NPN type triode, a first resistor and a second resistor. An error amplifier is not applied to the band-gap reference voltage source circuit, the influence of offset voltage and noise of the error amplifier on a system are omitted, and the power consumption and the area are reduced. In addition, independent generation of a branch circuit is not adopted in an output branch circuit of reference voltage Vref, the influence of the offset voltage caused by current image failure is avoided to some extent, and the area and the power consumption are reduced.

Description

A kind of bandgap voltage reference circuit

Technical field

The invention belongs to integrated circuit power supply technique field, relate in particular to a kind of bandgap voltage reference circuit.

Background technology

In Analogous Integrated Electronic Circuits or mixed-signal designs field, reference voltage source is a very important module, for system provides voltage reference and current reference.Along with the raising of circuit level, the also increasing chip internal that is integrated into of reference voltage source is to reduce system cost.

Traditional reference voltage source relies on the bandgap voltage reference circuit to produce usually; As shown in Figure 1; This bandgap voltage reference circuit comprises error amplifier, PMOS mirror current source, PNP pipe and resistance, and reference voltage is generated by the independent branch road (in Fig. 1, marking with dotted line) of the mirror current source that comprises PMOS pipe PM3, resistance R 2 and PNP pipe Q3 usually.

But above-mentioned bandgap voltage reference circuit has number of drawbacks: because of it comprises error amplifier and corresponding biasing circuit, therefore have the bigger problem of area; The offset voltage of error amplifier self and noise also can be added to reference voltage output end Vref; And; Because reference voltage is generated separately by a branch road; Therefore, the mirror image mismatch between PM3, PM1 and PM2 mirror current source also can strengthen the offset voltage of reference voltage in this bandgap voltage reference circuit.

Summary of the invention

In view of this, the object of the present invention is to provide a kind of bandgap voltage reference circuit, to solve the problem that area is big, offset voltage is big that exists in the prior art.

For realizing above-mentioned purpose, the present invention provides following technical scheme:

A kind of bandgap voltage reference circuit comprises PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, a NPN type triode, the 2nd NPN type triode, first resistance and second resistance; Wherein:

The source electrode and the substrate of said PMOS pipe and the 2nd PMOS pipe insert supply voltage;

The grid of said PMOS pipe and the 2nd PMOS pipe is connected to the drain electrode of the source electrode and said the 2nd PMOS pipe of said the 4th PMOS pipe simultaneously;

The drain electrode of said PMOS pipe is connected to the source electrode of said the 3rd PMOS pipe;

The substrate of said the 3rd PMOS pipe and the 4th PMOS pipe inserts supply voltage;

The grid of said the 3rd PMOS pipe and the 4th PMOS pipe is connected to the drain electrode of the collector and said the 4th PMOS pipe of said the 2nd NPN type triode simultaneously;

The drain electrode of said the 3rd PMOS pipe is connected to the collector of a said NPN triode through said second resistance;

The base stage of a said NPN type triode and the 2nd NPN type triode is connected to the collector of a said NPN type triode;

The grounded emitter of a said NPN type triode;

The emitter of said the 2nd NPN type triode is through said first resistance eutral grounding;

The drain electrode of said the 3rd PMOS pipe is as reference voltage output end.

Preferably, said PMOS pipe is identical with the device parameters of the 2nd PMOS pipe; Said the 3rd PMOS pipe is identical with the device parameters of the 4th PMOS pipe; The emitter area of a said NPN type triode and the 2nd NPN triode is than being n: 1;

wherein; expression is differentiated; Vbe1 representes the base-emitter junction voltage of a NPN type triode; T representes absolute temperature; Q representes electronic charge; K representes Boltzmann constant, and R2 representes the resistance value of second resistance, and R1 representes the resistance value of first resistance.

Therefore this shows that beneficial effect of the present invention is: do not use error amplifier in the bandgap voltage reference circuit disclosed by the invention, saved the influence of offset voltage voltage and the noise of error amplifier self, and saved power consumption and area to system; In addition, the output branch road of reference voltage V ref does not adopt a branch road to produce separately, the influence of the offset voltage of also having avoided current mirror excuse me, but I must be leaving now to a certain extent causing, and saved area and power consumption.

Description of drawings

In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is the structural drawing of existing bandgap voltage reference circuit;

Fig. 2 is the structural drawing of a kind of bandgap voltage reference circuit disclosed by the invention;

Fig. 3 is the temperature variant Tcm curve map of the reference voltage V ref of bandgap voltage reference circuit shown in Figure 2.

Embodiment

For quote and know for the purpose of, the explanation of the technical term that hereinafter uses, write a Chinese character in simplified form or abridge and sum up as follows:

PMOS, positive channel Metal Oxide Semiconductor, the PMOS pipe refers to n type substrate, p raceway groove, leans on the mobile metal-oxide-semiconductor that transports electric current in hole.

The invention discloses a kind of bandgap voltage reference circuit, in order to solve the problem that area is big, offset voltage is big that exists in the prior art.Its basic ideas are: utilize the positive temperature coefficient (PTC) of base-emitter voltage difference between the NPN pipe be in the amplification region, the negative temperature coefficient of base-emitter voltage, design a kind of low-power consumption, low area, low maladjustment voltage, low noise, bandgap voltage reference circuit simple for structure.

For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer; To combine the accompanying drawing in the embodiment of the invention below; Technical scheme in the embodiment of the invention is carried out clear, intactly description; Obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.

Referring to Fig. 2, Fig. 2 is the structural drawing of a kind of bandgap voltage reference circuit disclosed by the invention.Comprise PMOS pipe PM1, the 2nd PMOS pipe PM2, the 3rd PMOS pipe PM3, the 4th PMOS pipe PM4, a NPN type triode Q1, the 2nd NPN type triode Q2, first resistance R 1 and second resistance R 2.Wherein:

Source electrode and the substrate of the one PMOS pipe PM1 and the 2nd PMOS pipe PM2 insert supply voltage VDDA.The grid of the one PMOS pipe PM1 and the 2nd PMOS pipe PM2 is connected to the drain electrode of source electrode and the 2nd PMOS pipe PM2 of the 4th PMOS pipe PM4 simultaneously.The drain electrode of the one PMOS pipe PM1 is connected to the source electrode of the 3rd PMOS pipe PM3.The substrate of the 3rd PMOS pipe PM3 and the 4th PMOS pipe PM4 inserts supply voltage VDDA.The grid of the 3rd PMOS pipe PM3 and the 4th PMOS pipe PM4 is connected to the collector of the 2nd NPN type triode Q2 and the drain electrode of the 4th PMOS pipe PM4 simultaneously.The drain electrode of the 3rd PMOS pipe PM3 is connected to the collector of a NPN triode Q1 through second resistance R 2.The base stage of the one NPN type triode Q1 and the 2nd NPN type triode Q2 is connected to the collector of a NPN type triode Q1.The grounded emitter of the one NPN type triode Q1.The emitter of the 2nd NPN type triode Q2 is through first resistance R, 1 ground connection.The drain electrode of the 3rd PMOS pipe PM3 is as reference voltage V ref output terminal.

In implementation process; Can make PMOS pipe PM1 identical through design with the device parameters of the 2nd PMOS pipe PM2; Make the 3rd PMOS pipe PM3 identical, and to make the emitter area ratio of a NPN triode Q1 and the 2nd NPN triode Q2 be 1: n with the device parameters of the 4th PMOS pipe PM4.

The principle of work of above-mentioned bandgap voltage reference circuit is following:

When bandgap voltage reference circuit operate as normal, all PMOS pipes, NPN type triode are in saturation region and amplification region, and PM1, PM2 and PM3, PM4 form the cascade mirror current source.

Because the effect of current mirror, the branch current Id1 of PM1 place branch road equates with the branch current Id2 of PM2 place branch road, and Id1=Id2=Id, and wherein, Id is the channel current of PM1 and PM3.(therefore β=Ic/Ib) bigger flows through the collector current Ic1 of Q1 and flows through the collector current Ic2 approximately equal of Q2, Ic1 ≈ Ic2=Id because the current amplification factor β of Q1 and Q2.

Therefore, the base-emitter voltage difference dVbe of Q2, Q1 is:

dVbe＝Vbe2-Vbe1＝(KT/q)*ln(Ic2/Is2)-(KT/q)*ln(Ic1/Is1)

=(KT/q) * ln (Is1/Is2) (formula 1)

Wherein, Vbe1 is the base-emitter junction voltage of Q1, and Vbe2 is the base-emitter junction voltage of Q2; K representes Boltzmann constant, and T is an absolute temperature, and q representes electronic charge; Is1 is the reverse saturation current of Q1; Is2 is the reverse saturation current of Q2, and Ic1 is the collector current of Q1, and Ic2 is the collector current of Q2.

Because the emitter area of Q1, Q2 is than being n: 1, thus Is1/Is2=n/1, so formula 1 can be reduced to:

DVbe=Vbe2-Vbe1=(KT/q) * ln (n) (formula 2)

Above-mentioned dVbe is the voltage difference of resistance R 1, and the electric current I R1 that therefore flows through resistance R 1 satisfies following formula:

IR1=IQ1=IQ2=Id=(KT/q) * ln (n)/R1 (formula 3)

Therefore the voltage difference VR2 at resistance R 2 two ends satisfies following formula:

VR2=Id*R2=(KT/q) * ln (n) * R2/R1 (formula 4)

Reference voltage source Vref satisfies following formula:

Vref=Vbe1+VR2=Vbe1+ (KT/q) * ln (n) * R2/R1 (formula 5)

5 pairs of temperature T of formula are differentiated, for:

$\mathrm{Vref}/_{\∂}T_{\∂}=\mathrm{Vbel}/_{\∂}^{\∂}T+(K/q)*\mathrm{Ln}\left(n\right)*R2/R1$ (formula 6)

Because above-mentioned

is positive temperature coefficient (PTC); (K/q) be negative temperature coefficient; Therefore according to formula 6 numerical value and the resistance R 1 of n, the resistance value of R2 are set suitably; Can make Vref is zero at normal temperature formula 6 in season, thereby guarantees in operating temperature range, to have minimum reference voltage rate of change.

In resistance one timing of resistance R 1 and resistance R 2, making

thereby making formula 6 is zero.

Bandgap voltage reference circuit shown in Figure 2 itself has the function of single-stage error amplifier.Because PM4 forms diode; Therefore can think that the source electrode of PM4 amplifies output terminal with drain electrode for error; The source electrode of PM4 is linked to each other with the grid of PM1, PM2, and the drain electrode with PM4 simultaneously links to each other with the grid of PM3, PM4, to form feedback loop; The voltage signal that error is amplified is converted into current signal, thereby keeps the establishment of formula (5) and formula (6).

Therefore to sum up, in bandgap voltage reference circuit shown in Figure 2, do not use error amplifier, saved the influence of offset voltage voltage and the noise of error amplifier self, and saved power consumption and area system; In addition, the output branch road of reference voltage V ref is not as shown in Figure 1, is produced separately by a branch road (PM3 branch road), the influence of the offset voltage of also having avoided current mirror excuse me, but I must be leaving now to a certain extent causing, and saved area and power consumption.

The temperature variant Tcm curve of the reference voltage V ref of bandgap voltage reference circuit shown in Figure 2 can be referring to Fig. 3.It is thus clear that in the ordinary course of things, the conventional bandgap reference source of the supply-voltage rejection ratio of reference voltage V ref of the present invention, temperature coefficient Tcm and employing error amplifier shown in Figure 1 and PMOS mirror current source is close.

Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the disclosed device of embodiment, because it is corresponding with the embodiment disclosed method, so description is fairly simple, relevant part is partly explained referring to method and is got final product.

To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.

Claims (2)

1. a bandgap voltage reference circuit is characterized in that, comprises PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, a NPN type triode, the 2nd NPN type triode, first resistance and second resistance; Wherein:

The source electrode and the substrate of said PMOS pipe and the 2nd PMOS pipe insert supply voltage;

The grid of said PMOS pipe and the 2nd PMOS pipe is connected to the drain electrode of the source electrode and said the 2nd PMOS pipe of said the 4th PMOS pipe simultaneously;

The drain electrode of said PMOS pipe is connected to the source electrode of said the 3rd PMOS pipe;

The substrate of said the 3rd PMOS pipe and the 4th PMOS pipe inserts supply voltage;

The grid of said the 3rd PMOS pipe and the 4th PMOS pipe is connected to the drain electrode of the collector and said the 4th PMOS pipe of said the 2nd NPN type triode simultaneously;

The drain electrode of said the 3rd PMOS pipe is connected to the collector of a said NPN triode through said second resistance;

The base stage of a said NPN type triode and the 2nd NPN type triode is connected to the collector of a said NPN type triode;

The grounded emitter of a said NPN type triode;

The emitter of said the 2nd NPN type triode is through said first resistance eutral grounding;

The drain electrode of said the 3rd PMOS pipe is as reference voltage output end.

2. circuit according to claim 1 is characterized in that: said PMOS pipe is identical with the device parameters of the 2nd PMOS pipe; Said the 3rd PMOS pipe is identical with the device parameters of the 4th PMOS pipe; The emitter area of a said NPN type triode and the 2nd NPN triode is than being n: 1;

wherein; expression is differentiated; Vbe1 representes the base-emitter junction voltage of a NPN type triode; T representes absolute temperature; Q representes electronic charge; K representes Boltzmann constant, and R2 representes the resistance value of said second resistance, and R1 representes the resistance value of said first resistance.

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