CN102610584A - Staggered-pins structure for substrate - Google Patents
Staggered-pins structure for substrate Download PDFInfo
- Publication number
- CN102610584A CN102610584A CN2012100390272A CN201210039027A CN102610584A CN 102610584 A CN102610584 A CN 102610584A CN 2012100390272 A CN2012100390272 A CN 2012100390272A CN 201210039027 A CN201210039027 A CN 201210039027A CN 102610584 A CN102610584 A CN 102610584A
- Authority
- CN
- China
- Prior art keywords
- pin
- substrate
- circuitry lines
- present
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a staggered-pins structure for a substrate; in the staggered-pins structure for the substrate, a solder pad arranged on a chip of the substrate is electrically connected with a pin by a bonding lead; the pin is connected to an external circuit through a circuit line, wherein each pin is in regular hexagon shape; a plurality of pins are staggered along an arrangement direction of the solder pad on the chip; according to the staggered-pins structure for the substrate, the space of the pin part can be utilized in maximum so as to realize high-density encapsulation; in addition, the size of an encapsulation piece can be reduced.
Description
Technical field
The invention belongs to the semiconductor packaging field, specifically, the present invention relates to a kind of pin configuration that can realize the interlaced arrangement of the superintegrated substrate that is used for semiconductor package part.
Background technology
Size is littler, density is higher and performance is better along with electronic product becomes, and semiconductor becomes fine and close more and correspondingly becomes littler along with its assembly and annexation.Usually, connect, utilize bonding wire to connect substrate draw-foot and chip port through lead key closing process in order to realize circuit.Lead key closing process is to utilize bonding wire to make the terminal (hereinafter will be called " pad ") and the known method that interconnects such as pin (also being known as " wire bond pads " or " bonding welding pad " sometimes) corresponding in substrate or the printed circuit board (PCB) (PCB) of integrated circuit (IC) chip.
The pad of traditional bonding that is used to go between is arranged the pin rectangular shaped of substrate regularly.Figure 1A shows the sketch map that the bonding wire according to conventional art is connected with the pin of substrate, and Figure 1B shows the sketch map according to the pin arrangement shown in Figure 1A of conventional art.Shown in Figure 1A, pin 101 interconnects through bonding wire 105 and the pad 103 that is arranged on the chip 104 on the substrate (not shown), thereby realizes being electrically connected of substrate and chip.Shown in Figure 1B; Has rectangular shape according to the pin on the substrate of conventional art 101; Pin-pitch P11 is typically about 80 μ m, and the width W 11 of each pin 101 is typically about 50 μ m, and the interval P12 between two pins 101 adjacent one another are is typically about 30 μ m.Here, the definition of pin-pitch is well-known to those skilled in the art, is meant the distance between the corresponding limit of two pins adjacent one another are, like the label among Figure 1B " P11 " indication.Therefore, for the packaging part of conventional art, the area in bonding zone is bigger, can not realize well that high density is integrated.
The patent No. is the solder pad arrangements that the United States Patent (USP) of US5444303 discloses a kind of bonding that goes between.Fig. 2 A shows the syndeton sketch map according to the pin of the bonding wire of prior art (this United States Patent (USP)) and flexible base, board.Fig. 2 B shows the sketch map according to the pin arrangement shown in Fig. 2 A of prior art.With reference to Fig. 2 A, similar with Figure 1A, the pin 201 among Fig. 2 A interconnects through bonding wire 205 and the pad 203 that is arranged on the chip 204 on the substrate 200, thereby realizes being electrically connected of chip and external circuit.Different with Figure 1A and Figure 1B is that the pin among Fig. 2 A and Fig. 2 B is trapezoidal shape.Shown in Fig. 2 B; Pin 201 forms has the parallel long limit and the trapezoidal shape of minor face; And be basically perpendicular to line from the central point of pin 201 to the central point of the corresponding bonding pad 203 of IC chip 204; Wherein, the arrangement of the pin 201 of trapezoidal shape is that the long limit of adjacent pin 201 is respectively by towards arranging alternately that with the mode away from the corresponding bonding pad 203 of IC chip 204 pin 201 is connected to external circuit through circuitry lines 202.With reference to Fig. 2 B; In a preferred embodiment; Pin-pitch P21 can be 279.4 μ m; Interval P22 between two pins 201 adjacent one another are can be 25 μ m, and the pin 201 with trapezoidal shape can have the long limit that length W21 is 203.2 μ m, and the length W22 of each pin 201 can be 406.4 μ m.Compare with the pin among Figure 1B with Figure 1A, though the interval between the pin among Fig. 2 A and Fig. 2 B is less relatively, the pin-pitch among Fig. 2 A and Fig. 2 B is still bigger, makes that the area in bonding zone is relatively large, can not realize well that high density is integrated.
The patent No. is the structure that the United States Patent (USP) of US5898213 discloses a kind of bonding pin of semiconductor package part.Fig. 3 shows the plane graph according to the radial bonding pin in the semiconductor package part of this United States Patent (USP).With reference to Fig. 3, pin is electrically connected to the pad 303 that is arranged on the chip 304 through bonding wire 305, in the pin structure of this semiconductor package part; With three pins is one group; Wherein, two pin 301a arrange that the 3rd pin 301b is arranged between these two pins with facing with each other.As shown in Figure 3, though this pin arranges that closely the area in bonding zone is still bigger, can not realize well that high density is integrated.
Therefore, in the prior art, through staggered difform pin reaching the pin that distributes as much as possible, thereby realize high-density packages.Yet existing technology still can not maximally utilise the space of pin part.
Summary of the invention
The object of the present invention is to provide to solve the problems referred to above that exist in the prior art, a kind of pin configuration that can maximally utilise the space of pin part is provided.
According to an aspect of the present invention; A kind of pin configuration that is used for the interlaced arrangement of substrate is provided; The bonding pads that bonding wire will be arranged on the substrate is electrically connected to pin, and pin is connected to external circuit through circuitry lines, wherein; Each pin has the regular hexagon shape, and the direction of the solder pad arrangements on a plurality of pins edge and the chip is arranged alternately.
According to embodiments of the invention, two limits that are parallel to each other that each pin can be arranged to this pin are parallel to the direction that circuitry lines is extended.
According to embodiments of the invention, each pin can be arranged to the direction of two limits that are parallel to each other of this pin perpendicular to the circuitry lines extension.
According to embodiments of the invention, at least some circuitry lines in many circuitry lines plural pin can be set.
According to embodiments of the invention, the arrangement of each pin can be that two parallel limits in each pin have predetermined angle beta with respect to horizontal direction, wherein, and 0 °≤β≤90 ° or-90 °≤β≤0 °.
According to the pin configuration that is used for substrate of the present invention, can maximally utilise pin space partly with the realization high-density packages, and can reduce the size of packaging part.
Description of drawings
Comprise that accompanying drawing provides further understanding, and the part of this specification is incorporated in this manual and constituted to accompanying drawing into.Accompanying drawing shows exemplary embodiment, and with describing the principle that is used for explaining inventive concept.In the accompanying drawings:
Figure 1A shows the sketch map that the bonding wire according to conventional art is connected with the pin of substrate;
Figure 1B shows the sketch map of the pin arrangement shown in Figure 1A;
Fig. 2 A shows the syndeton sketch map according to the pin of the bonding wire of prior art and flexible base, board;
Fig. 2 B shows the sketch map of the pin arrangement shown in Fig. 2 A;
Fig. 3 shows the plane graph according to the radial bonding pin in the semiconductor package part of another prior art;
Fig. 4 A shows the sketch map that the bonding wire of first exemplary embodiment according to the present invention is connected with the pin of substrate;
Fig. 4 B shows the sketch map of the pin arrangement shown in Fig. 4 A;
Fig. 5 A shows the sketch map that the bonding wire of second exemplary embodiment according to the present invention is connected with the pin of substrate;
Fig. 5 B shows the sketch map of the pin arrangement shown in Fig. 5 A;
Fig. 6 shows the sketch map that the bonding wire of the 3rd exemplary embodiment according to the present invention is connected with the pin of substrate;
Fig. 7 A shows the sketch map that the bonding wire of the 4th exemplary embodiment according to the present invention is connected with the pin of substrate;
Fig. 7 B shows the sketch map of each pin shown in Fig. 7 A.
Embodiment
Hereinafter, will come to describe more fully the present invention, exemplary embodiment of the present invention be shown in the accompanying drawing with reference to accompanying drawing.As those skilled in the art will recognize that, under the situation that does not all break away from the spirit that is used for principle of the present invention or scope, can revise the embodiment of description with various mode.
Recognize that describe in order to understand better and to be convenient to, the size of the composition member shown in the accompanying drawing provides arbitrarily, the present invention does not receive the restriction of illustrated size.In the accompanying drawings, for clarity, exaggerated the thickness in layer, zone etc.Same or analogous label is represented components identical in whole specification.
The invention provides a kind of regular hexagon pin of the novel interlaced arrangement that is used for substrate, be used for realizing high-density wiring, reduce the bonding region area simultaneously to reach the effect that packaging part overall dimension reduces.
To combine accompanying drawing to describe the pin configuration that is used for the substrate of semiconductor package part according to of the present invention in detail below.
Fig. 4 A shows the sketch map that the bonding wire of first exemplary embodiment according to the present invention is connected with the pin of substrate.Fig. 4 B shows the sketch map of the pin arrangement shown in Fig. 4 A.
With reference to Fig. 4 A, bonding wire (will be called " lead-in wire " hereinafter) 5 connects pins 1 and the pad 3 that is arranged on the chip 4 on the substrate (not shown), and each pin 1 is electrically connected with the substrate circuit external through circuitry lines 2, with the realization circuit communication.According to the present invention, all pins 1 all are hexagon, and the direction (in Fig. 4 A, along Y direction) that the pad on a plurality of pin 1 edge and the chip 43 is arranged arranges alternately, with the pin of maximum quantity of arranging to greatest extent and most effectively.In first exemplary embodiment of the present invention, pin 1 has three pairs of limits that are parallel to each other, and the arrangement of pin 1 is to make the wherein a pair of parallel limit of each pin 1 be parallel to the direction that circuitry lines 2 is extended.
With reference to Fig. 4 B, two pins 1 adjacent one another are closely are arranged together.Can find out that through Figure 1B and Fig. 4 B in the conventional art shown in Figure 1B, pin-pitch P11 is pin widths W11 and pin interval P12 sum, that is, and P11=W11+P12; Yet in the structure according to the regular hexagon pin of interlaced arrangement of the present invention, pin-pitch P1＜W1＜W1+P2 is much smaller than the pin-pitch P1 shown in Figure 1B.Therefore; In pin configuration according to current exemplary embodiment of the present invention; Because two adjacent pins have certain overlapping, make pin-pitch P1 less than pin widths W1, so two shared zones of adjacent pin reduce; Therefore the shared area of pin obviously reduces, thereby can significantly increase the effective area that routing can be used.
Therefore; In current exemplary embodiment of the present invention; Processing procedure ability according to substrate manufacture; Cooperate the width W 3 of pin-pitch P1, wire distribution distance P2 (at interval), pin widths W1 and circuitry lines 2 to design together through the length of side W2 that makes pin 1, can make bonding region territory area realize the high density designs requirement, reach the purpose of dwindling package size simultaneously corresponding to pin.Those skilled in the art can select the width W 3 of suitable pin-pitch P1, pin size W1 or W2, pin-pitch P2 and circuitry lines 2 under instruction of the present invention.
Preferably, each parameter of the pin shown in Fig. 4 B can satisfy formula: P1=0.5W1+P2+0.5W3, wherein, and W1
2=3W2
2The preferred embodiment of current exemplary embodiment according to the present invention, according to the basal plate making process ability, the major limitation pin is the W3 of P2 and circuitry lines 2 at interval, can control pin-pitch P2 minimum about 20um, and the I of the width W of circuitry lines 3 is to about the 15um.Calculating by top formula, suppose P2=20 μ m and W3=15 μ m, under the pin design pitch of P1=80 μ m requires, is 105 μ m through calculating the pin widths W1 that can draw the optimization according to the present invention so.Therefore, with respect to prior art, can under the situation of same pin-pitch, can guarantee bonding stability better.
Fig. 5 A shows the sketch map that the bonding wire of second exemplary embodiment according to the present invention is connected with the pin of substrate, and Fig. 5 B shows the sketch map of the pin arrangement shown in Fig. 5 A.
The same with first exemplary embodiment of Fig. 4 A and Fig. 4 B; According to second exemplary embodiment of the present invention; Lead-in wire 5 with the pad on the chip 43 be electrically connected to pin 1 ', pin 1 ' be electrically connected to the substrate circuit external through circuitry lines 2, thus realize being electrically connected of substrate and external circuit.Different with first exemplary embodiment shown in Fig. 4 A and Fig. 4 B is, shown in Fig. 5 A, pin 1 ' arrangement be each pin 1 ' a pair of parallel limit direction of extending perpendicular to circuitry lines 2.
With reference to Fig. 5 B, two pins 1 adjacent one another are ' closely be arranged together.Can find out that through Figure 1B and Fig. 5 B in the conventional art shown in Figure 1B, pin-pitch P11 is pin widths W11 and pin interval P12 sum, that is, and P11=W11+P12; Yet in the structure according to the regular hexagon pin of interlaced arrangement of the present invention, pin-pitch P1 '＜W1 '+P2 ' is much smaller than the pin-pitch P1 shown in Figure 1B.Therefore; Compare with the pin configuration of conventional art; Pin-pitch according to the pin configuration of current exemplary embodiment of the present invention is obviously less; Can significantly reduce two zones that adjacent pin is shared, make the shared area of pin obviously reduce, thereby can significantly increase the effective area that routing can be used.
For advantage of the present invention place is described better; Be spaced apart example to adopt with pin-pitch and pin interval (shown in Figure 1B) identical pin-pitch and pin of conventional art; That is, in second exemplary embodiment according to the present invention, pin-pitch P1 ' be approximately 80 μ m and two pins 1 adjacent one another are ' between interval P2 ' be approximately 30 μ m; In this case, wire widths W1 ' can be 70 μ m.Therefore, compared with prior art, in the structure of the regular hexagon pin of the interlaced arrangement of second exemplary embodiment according to the present invention, two shared zones of adjacent pin reduce, and therefore can significantly increase the effective area that routing can be used.
In addition; If with the pin among Fig. 5 B 1 ' width and pin 1 ' between the interval be set at the same with at interval with the width of the rectangular pins of the conventional art shown in Figure 1B; That is, with pin 1 ' width W 1 ' be set at 50 μ m, the interval P2 ' between pin is set at 30 μ m; Then pin-pitch P1 ' can correspondingly become 60 μ m, and is obviously littler than the pin-pitch (being 80 μ m) of the rectangular pins of conventional art.Therefore, according to the present invention, can reduce the occupied area of pin significantly, thereby can realize highly integrated.
Fig. 6 shows the sketch map that the bonding wire of the 3rd exemplary embodiment according to the present invention is connected with the pin of substrate.
The same with Fig. 4 B with Fig. 4 A, lead-in wire 5 is electrically connected to pin 1 with the pad on the chip 43, and pin 1 is electrically connected to the substrate circuit external through circuitry lines 2, thereby realizes being electrically connected of substrate and external circuit.With according to the pin arrangement of first exemplary embodiment of the present invention different be; In pin arrangement shown in Figure 6; Be provided with two pins 1 for same circuitry lines 2; That is, apart from nearer relatively first pin of the pad on the chip 43 with apart from 3 relative second pins far away of the pad on the chip 4.That is to say can arrange 2 circles and 2 circles are above convenient actual when carrying out the lead-in wire bonding to the selection of line length and routing angle of pin 1.For for simplicity, in Fig. 6, only show the structure of the 2 circle pins of arranging, will be described in greater detail below; Yet, the invention is not restricted to this.In one embodiment of the invention; Can at least some circuitry lines of many circuitry lines, plural pin be set; Promptly; On some circuitry lines that can be in many circuitry lines or all circuitry lines plural pin is set, and the pin that is arranged on two adjacent circuitry lines is arranged alternately.
In current exemplary embodiment according to the present invention; Through the pad 3 on go between 5 connection pins 1 and the chip 4; Can angulation α and line length d, therefore, first pin that is arranged on the same circuitry lines 2 has different angles with second pin with respect to the pad on the chip of correspondence.As shown in Figure 6; Specifically; For the same pad on the chip 4; Line from the center of this pad to the center of first pin that is connected with this pad has length d 1, and the line from the center of this pad to the center of first pin that is connected with this pad has angle [alpha] 1 with respect to horizontal direction (that is X-direction); Line from the center of this pad to the center of second pin that is connected with this pad has length d 2; And to the line at the center of second pin that is connected with this pad (promptly with respect to horizontal direction from the center of this pad; X-direction) has angle [alpha] 2; Second pin can be connected to pad 3 through another 5a that goes between, wherein, and d1＜d2 and α 1＞α 2.The preferred embodiment of the 3rd exemplary embodiment according to the present invention can be defined as 45 °＞α, 1＞α 2 with α 1 with angle [alpha] 1.
Therefore, as shown in Figure 6, current exemplary embodiment according to the present invention has the design of the staggered regular hexagon pin 1 of many circles, and through the pad 3 on go between 5 connection pins 1 and the chip 4, shape has a certain degree and line length.For the lead-in wire bonding of high density thin space, routing angle and length are very big to breast the tape yield influence of injection moulding; According to the present invention, carry out optional line through the staggered regular hexagon pin of many circles and use the production of carrying out reality, help improving the whole yield of product.
In Fig. 4 A, Fig. 4 B and Fig. 6, wherein two the parallel edges that show pin 1 and the bearing of trend (X-direction) of circuitry lines 2 structures arranged abreast.Yet, the invention is not restricted to this.In a variant embodiment of the present invention; Can the pin arrangement shown in Fig. 5 A be applied in the exemplary embodiment of Fig. 6; In this case; Can at least some circuitry lines of many circuitry lines, arrange plural pin alternately, wherein, the direction that extend perpendicular to circuitry lines 2 on a pair of parallel limit of each pin.In another variant embodiment of the present invention; Can the pin arrangement shown in Fig. 4 A and Fig. 5 A be applied in the exemplary embodiment of Fig. 6 simultaneously; Specifically, can at least some circuitry lines of many circuitry lines, arrange plural pin alternately, wherein; The direction that extend perpendicular to circuitry lines 2 on a pair of parallel limit of at least one pin, and a pair of parallel limit of remaining pin is parallel to the direction that circuitry lines 2 is extended.Under instruction of the present invention, those skilled in the art can confirm the arrangement of pin according to actual conditions.Therefore, in the present invention, two parallel limits with pin 1 of hexagonal shape can have certain angle with respect to the bearing of trend of circuitry lines 2, will carry out detailed description to this below.
Fig. 7 A shows the sketch map that the bonding wire of the 4th exemplary embodiment according to the present invention is connected with the pin of substrate, and Fig. 7 B shows the sketch map of each pin shown in Fig. 7 A.
The same with Fig. 4 B with Fig. 4 A, lead-in wire 5 is electrically connected to pin 1 with the pad on the chip 43 ", pin 1 " is electrically connected to the substrate circuit external through circuitry lines 2, thereby realizes being electrically connected of substrate and external circuit.With according to the pin arrangement of aforementioned exemplary embodiment of the present invention different be that shown in Fig. 7 A, according to different routing requirements, the pin 1 with positive six shape shapes " can rotate different angles.
Shown in Fig. 7 A, the regular hexagon pin 1 of interlaced arrangement " direction that can be designed to extend with respect to circuitry lines along clockwise or counterclockwise rotate arbitrarily angled, and to the pin that is rotated into different angles and the pad 3 on the chip 4 bonding that goes between.Because the existence of routing angle, the position of second Breadth Maximum of lead-in wire bonding changes thereupon.The principle corresponding, or, can change pin 1 accordingly according to comprehensive other factors according to the position of the Breadth Maximum that pin 1 " is rotated into to the position and the pin 1 of the Breadth Maximum of second width " " the anglec of rotation, to reach the best effort effect.
With reference to Fig. 7 A; " can comprise the pin 1a, 1b and the 1c that have rotated different angles, that is, two parallel limits that pin 1a, 1b and 1c are arranged to each pin have predetermined angle beta with respect to horizontal direction to pin 1; wherein, 0 °≤β≤90 ° or-90 °≤β≤0 °.Each pin 1 " has pin (stich) 6." the structure after the different rotation angle that Fig. 7 B shows pin 1.Shown in Fig. 7 A and Fig. 7 B, the first pin 1a is the same with the pin of aforementioned exemplary embodiment, is arranged to its two parallel limits and is parallel to horizontal direction (X-direction).The arrangement of the second pin 1b and the 3rd pin 1c is different from the pin among the aforementioned exemplary embodiment.Specifically, the second pin 1b be arranged to center with respect to the first pin 1a be rotated in a clockwise direction 30 ° (with the pin 1 shown in Fig. 5 A ' layout identical); The 3rd pin 1c is arranged to be rotated in a clockwise direction 70 ° with respect to the center of the first pin 1a.Therefore, " correspondingly the predetermined angle of rotation can make pin reach best work according to current exemplary embodiment of the present invention, through making pin 1.
In the exemplary embodiment shown in Fig. 7 A and Fig. 7 B, though illustrate to be second pin and the 3rd pin rotate 30 ° and 70 ° respectively along clockwise direction with respect to the center of first pin, the invention is not restricted to this.Under instruction of the present invention, those skilled in the art can require to make pin with respect to along clockwise or counterclockwise rotate different angle beta (0 °≤β≤90 °) according to reality.
According to the present invention, can carry out various modification to the exemplary embodiment shown in Fig. 4 A to Fig. 7 B.In one embodiment of the invention; Can be at the pin that is provided with on the same circuitry lines more than 2 circles; And make the some of them pin rotate different angle beta (0 °≤β≤90 °) along clockwise direction or counterclockwise, thereby be beneficial to whole yield that improves product and the best effort effect that reaches pin.
According to the present invention, two limits that are parallel to each other of regular hexagon pin not with the technical scheme of horizontal direction parallel, be in order to be adapted to bonding wire.Specifically, bonding wire can form second bonding point of different profiles with leads ends when different directions, and the most wide degree of this incomplete same second bonding point is also incomplete same, shown in Fig. 7 A.Pin 1a, 1b, 1c are three kinds of different anglec of rotation signals; Direction (angle) corresponding to different bonding wires; Its basic purpose is to make second bonding point (promptly; Pin) the widest part uses the pin area corresponding to the widest part of regular hexagon pin of the present invention to reach most effectively.The regular hexagon pin of the anglec of rotation shown in Fig. 7 A is a special applications of the present invention; When using this to use; The number of pins of maximum quantity of arranging to greatest extent in the identical pin-pitch is not a most preferred embodiment; The arrange zone of pin of part is correspondingly wasted in this rotation meeting, but in the position of the most wide degree of second bonding point and pin need keep the application of correspondence, can improve the quality of second bonding effectively.
Though combined accompanying drawing of the present invention to describe the present invention, it should be understood that under the situation that does not break away from the spirit and scope of the present invention, can make various variants and modifications to the present invention.
Claims (6)
1. pin configuration that is used for the interlaced arrangement of substrate; Wherein, The bonding pads that bonding wire will be arranged on the substrate is electrically connected to pin; Pin is connected to external circuit through circuitry lines, it is characterized in that each pin has the regular hexagon shape, and the direction of the solder pad arrangements on a plurality of pins edge and the chip is arranged alternately.
2. the pin configuration that is used for the interlaced arrangement of substrate according to claim 1 is characterized in that two limits that are parallel to each other that each pin is arranged to this pin are parallel to the direction that circuitry lines is extended.
3. the pin configuration that is used for the interlaced arrangement of substrate according to claim 1 is characterized in that each pin is arranged to the direction of two limits that are parallel to each other of this pin perpendicular to the circuitry lines extension.
4. according to claim 2 or the 3 described pin configuration that are used for the interlaced arrangement of substrate, it is characterized in that at least some circuitry lines in many circuitry lines plural pin being set.
5. the pin configuration that is used for the interlaced arrangement of substrate according to claim 1 is characterized in that at least some circuitry lines in many circuitry lines plural pin being set.
6. according to claim 1 or the 5 described pin configuration that are used for the interlaced arrangement of substrate; The arrangement that it is characterized in that each pin is that two parallel limits in each pin have predetermined angle beta with respect to horizontal direction; Wherein, 0 °≤β≤90 ° or-90 °≤β≤0 °.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210039027.2A CN102610584B (en) | 2012-02-21 | 2012-02-21 | Staggered-pins structure for substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210039027.2A CN102610584B (en) | 2012-02-21 | 2012-02-21 | Staggered-pins structure for substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102610584A true CN102610584A (en) | 2012-07-25 |
| CN102610584B CN102610584B (en) | 2015-02-04 |
Family
ID=46527865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210039027.2A Active CN102610584B (en) | 2012-02-21 | 2012-02-21 | Staggered-pins structure for substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102610584B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076937A (en) * | 2013-01-30 | 2013-05-01 | 福建科创光电有限公司 | Electrode pin of capacitive touch screen |
| CN105093728A (en) * | 2015-07-10 | 2015-11-25 | 武汉华星光电技术有限公司 | Drive circuit and liquid-crystal display panel |
| WO2018176357A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | Peripheral component coupler method and apparatus |
| CN110689812A (en) * | 2019-11-11 | 2020-01-14 | 昆山国显光电有限公司 | Flexible structure, display panel and display device |
| CN113053276A (en) * | 2021-03-17 | 2021-06-29 | 京东方科技集团股份有限公司 | Display module, display device and binding detection method |
| CN113376907A (en) * | 2021-06-11 | 2021-09-10 | 四川京龙光电科技有限公司 | LCD module with integrated function |
| CN117275426A (en) * | 2023-10-27 | 2023-12-22 | 北京显芯科技有限公司 | Backlight circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
| US20030197251A1 (en) * | 2000-12-04 | 2003-10-23 | Akio Nakamura | Semiconductor device with staggered hexagonal electrodes and increased wiring width |
| CN1750243A (en) * | 2004-09-16 | 2006-03-22 | 日月光半导体制造股份有限公司 | No external leading pin type semiconductor package structure and its producing method |
| US7411287B2 (en) * | 2004-11-05 | 2008-08-12 | Advanced Semiconductor Engineering, Inc. | Staggered wirebonding configuration |
| CN101501844A (en) * | 2006-05-16 | 2009-08-05 | 飞思卡尔半导体公司 | Integrated circuit having pads and input/output (I/O) cells |
| JP4510961B2 (en) * | 1999-10-19 | 2010-07-28 | Ｏｋｉセミコンダクタ株式会社 | Optical module |
| CN102222657A (en) * | 2011-06-30 | 2011-10-19 | 天水华天科技股份有限公司 | Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof |
-
2012
- 2012-02-21 CN CN201210039027.2A patent/CN102610584B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
| JP4510961B2 (en) * | 1999-10-19 | 2010-07-28 | Ｏｋｉセミコンダクタ株式会社 | Optical module |
| US20030197251A1 (en) * | 2000-12-04 | 2003-10-23 | Akio Nakamura | Semiconductor device with staggered hexagonal electrodes and increased wiring width |
| CN1750243A (en) * | 2004-09-16 | 2006-03-22 | 日月光半导体制造股份有限公司 | No external leading pin type semiconductor package structure and its producing method |
| US7411287B2 (en) * | 2004-11-05 | 2008-08-12 | Advanced Semiconductor Engineering, Inc. | Staggered wirebonding configuration |
| CN101501844A (en) * | 2006-05-16 | 2009-08-05 | 飞思卡尔半导体公司 | Integrated circuit having pads and input/output (I/O) cells |
| CN102222657A (en) * | 2011-06-30 | 2011-10-19 | 天水华天科技股份有限公司 | Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076937A (en) * | 2013-01-30 | 2013-05-01 | 福建科创光电有限公司 | Electrode pin of capacitive touch screen |
| CN105093728A (en) * | 2015-07-10 | 2015-11-25 | 武汉华星光电技术有限公司 | Drive circuit and liquid-crystal display panel |
| WO2018176357A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | Peripheral component coupler method and apparatus |
| US11336043B2 (en) | 2017-03-31 | 2022-05-17 | Intel Corporation | Peripheral component coupler method and apparatus |
| CN110689812A (en) * | 2019-11-11 | 2020-01-14 | 昆山国显光电有限公司 | Flexible structure, display panel and display device |
| CN110689812B (en) * | 2019-11-11 | 2022-05-10 | 昆山国显光电有限公司 | Flexible structure, display panel and display device |
| CN113053276A (en) * | 2021-03-17 | 2021-06-29 | 京东方科技集团股份有限公司 | Display module, display device and binding detection method |
| CN113053276B (en) * | 2021-03-17 | 2023-09-19 | 京东方科技集团股份有限公司 | Display module, display device and binding detection method |
| CN113376907A (en) * | 2021-06-11 | 2021-09-10 | 四川京龙光电科技有限公司 | LCD module with integrated function |
| CN117275426A (en) * | 2023-10-27 | 2023-12-22 | 北京显芯科技有限公司 | Backlight circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102610584B (en) | 2015-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102610584B (en) | Staggered-pins structure for substrate | |
| CN101276811B (en) | Semiconductor device | |
| CN103843136B (en) | DRAM and SOC is encapsulated in IC package | |
| US9299685B2 (en) | Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer | |
| CN101150118A (en) | Semiconductor device | |
| CN103258806A (en) | Semiconductor package structure with bridging structure and manufacturing method thereof | |
| US20200402959A1 (en) | Stacked semiconductor package having an interposer | |
| CN101459170A (en) | Semiconductor device | |
| US20070035036A1 (en) | Semiconductor device, laminated semiconductor device, and wiring substrate | |
| CN102163595A (en) | Stacked semiconductor package | |
| CN205177808U (en) | Chip packaging structure | |
| KR20220065781A (en) | Wiring Design Methods, Wiring Structures, and Flip Chips | |
| CN1568543B (en) | Semiconductor component | |
| US6091089A (en) | Semiconductor integrated circuit device | |
| JP2001177050A (en) | Semiconductor device | |
| CN101236940B (en) | Line structure for reconfiguration line layer | |
| CN103650135B (en) | Semiconductor device | |
| CN210899808U (en) | Differential pair wiring structure and circuit board with same | |
| CN105704918A (en) | High density printed circuit board | |
| US20230133965A1 (en) | Semiconductor Device With Unbalanced Die Stackup | |
| CN104299947B (en) | The method for manufacturing semiconductor devices | |
| CN103050475B (en) | Anti-warping packaging substrate | |
| US20080169573A1 (en) | Circuit substrate and the semiconductor package having the same | |
| CN206584919U (en) | A kind of townhouse substrate | |
| CN101246872A (en) | Semiconductor package substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |