CN102637693A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN102637693A CN102637693A CN2011100358728A CN201110035872A CN102637693A CN 102637693 A CN102637693 A CN 102637693A CN 2011100358728 A CN2011100358728 A CN 2011100358728A CN 201110035872 A CN201110035872 A CN 201110035872A CN 102637693 A CN102637693 A CN 102637693A
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Abstract
The invention discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, first stacked structures, second stacked structures, dielectric components and electric leads, wherein the first stacked structures and the second stacked structures are configured on the susbtrate; each of the first stacked structures and the second stacked structures comprises conducting stripes and insulating stripes, which are stacked in a staggered manner; the conducting stripes are separated by the insulating stripes; the dielectric components are configured on the first stacked structures and the second stacked structures and comprise second dielectric parts; the first stacked structures and the second stacked structures are separated from each other only by the second dielectric parts; the electric leads are configured on the stacked side walls of the first stacked structures and the second stacked structures, far from the second dielectric parts; and the dielectric components are arranged between the electric leads and the first stacked structures as well as between the electric leads and the second stacked structures.
Description
Technical field
The present invention relates to semiconductor structure and manufacturing approach thereof, particularly relate to storage device and manufacturing approach thereof.
Background technology
Storage device is used among many products, for example in the memory element of MP3 player, digital camera, computer archive or the like.Along with the increase of using, also tend to less size, bigger memory capacity for the demand of storage device.In response to this demand, need to make the storage device of high component density.
Designers develop a kind of method that improves density of memory devices and are to use three-dimensional stacked storage device, are used to reach higher memory capacity, reduce the cost of each bit simultaneously.Yet the micro limit of the memory cell size of this kind storage device is difficult to great breakthrough still greater than 50nm at present.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor structure and manufacturing approach thereof.Semiconductor structure has very little micro size.
A kind of semiconductor structure is provided.Semiconductor structure comprises substrate, first stacked structure, second stacked structure, dielectric element and conductor wire.First stacked structure and second stacked structure are disposed in the substrate.Each of first stacked structure and second stacked structure comprises the conductive stripe and insulation striped that is staggeredly stacked.Conductive stripe through the insulation striped separately.Dielectric element is disposed on first stacked structure and second stacked structure and comprises second dielectric part.First stacked structure and second stacked structure are only spaced-apart through second dielectric part.Conductor wire is disposed at the piling up on the sidewall away from second dielectric part of first stacked structure and second stacked structure.Dielectric element is between between the conductor wire and first stacked structure and between the conductor wire and second stacked structure.
A kind of manufacturing approach of semiconductor structure is provided.Method may further comprise the steps.In substrate, form first stacked structure and second stacked structure.Each of first stacked structure and second stacked structure comprises the conductive stripe and insulation striped that is staggeredly stacked.Conductive stripe through the insulation striped separately.Form dielectric element.Dielectric element comprises second dielectric part.First stacked structure and second stacked structure are only spaced-apart through second dielectric part.
Hereinafter is special lifts preferred embodiment, and cooperates appended accompanying drawing, elaborates as follows:
Description of drawings
Fig. 1 is the stereogram of the semiconductor structure of one embodiment of the invention;
The cutaway view that Fig. 2 is drawn out along the AA line for the semiconductor structure of Fig. 1;
Fig. 3 is the semiconductor structure sketch map of one embodiment of the invention;
Fig. 4 is the semiconductor structure sketch map of one embodiment of the invention;
Fig. 5 is the semiconductor structure sketch map of one embodiment of the invention;
Fig. 6 to Figure 12 is the manufacturing approach sketch map of semiconductor structure in one embodiment of the invention.
The main element symbol description
2,402: substrate
4,404,504: the first stacked structures
6,406,506: the second stacked structures
8,408: the three stacked structures
10,410: the four stacked structures
12,412,512: conductive stripe
14,414: the insulation striped
16: the first gaps
18: the second gaps
20: third space
Pile up sidewall at 22: the first
Pile up sidewall at 24: the second
Piled up sidewall in 26: the three
Piled up sidewall in 28: the four
Piled up sidewall in 30: the five
Piled up sidewall in 32: the six
Piled up sidewall in 34: the seven
Piled up sidewall in 36: the eight
38,138,238,438,538: dielectric element
40,140,240,540: the first dielectric part
42,142,242,542: the second dielectric part
44,144,244,544: the three dielectric part
46,146,246,546: the four dielectric part
48,148,248: the five dielectric part
50,150,250,550: the six dielectric part
52,152,252,552: the seven dielectric part
54,154,254,554: the eight dielectric part
56,456: conductor wire
135,137,139,235,237,239,521,523,525,527,529: dielectric layer
403: conductive layer
405: insulating barrier
407,443: mask layer
439: electric conducting material
441: contact material
458: contact structures
E: half spacing
F, N: distance
G, K, M, Q: thickness
Embodiment
Fig. 1 illustrates the stereogram of the semiconductor structure of an embodiment.The cutaway view that Fig. 2 is drawn out along the AA line for the semiconductor structure of Fig. 1.In an embodiment, semiconductor structure is three-dimensional perpendicular grid storage device (3D vertical gate memory device), for example comprises anti-and grid (NAND) type flash memories or anti-fuse memory or the like.
Please with reference to Fig. 1, semiconductor structure comprises substrate 2.First stacked structure 4, second stacked structure 6, the 3rd stacked structure 8 and the 4th stacked structure 10 are disposed in the substrate 2.Each of first stacked structure 4, second stacked structure 6, the 3rd stacked structure 8 and the 4th stacked structure 10 comprises the conductive stripe 12 and insulation striped 14 that is staggeredly stacked.Conductive stripe 12 is separated from each other through insulation striped 14.Insulation striped 14 can comprise for example silica of oxide.Conductive stripe 12 can comprise for example P-type polysilicon of metal or semi-conducting material.In one embodiment, the conductive stripe 12 of different levels is respectively as the bit line (BL) of different memory planes.
Has first gap 16 between first stacked structure 4 and second stacked structure 6.Has second gap 18 between second stacked structure 6 and the 3rd stacked structure 8.Has third space 20 between the 3rd stacked structure 8 and the 4th stacked structure 10.First stacked structure 4 comprises that relative first piles up sidewall 22 and second and pile up sidewall 24.Second stacked structure 6 comprises that the relative the 3rd piles up sidewall 26 and the 4th and pile up sidewall 28.The 3rd stacked structure 8 comprises that the relative the 5th piles up sidewall 30 and the 6th and pile up sidewall 32.The 4th stacked structure 10 comprises that the relative the 7th piles up sidewall 34 and the 8th and pile up sidewall 36.First piles up sidewall 22 and the 4th piles up sidewall 28 away from first gap 16.Second piles up sidewall 24 and the 3rd piles up sidewall 26 contiguous first gaps 16.The 4th piles up sidewall 28 and the 5th piles up sidewall 30 contiguous second gaps 18.The 3rd piles up sidewall 26 and the 6th piles up sidewall 32 away from second gap 18.The 6th piles up sidewall 32 and the 7th piles up sidewall 34 contiguous third spaces 20.The 5th piles up sidewall 30 and the 8th piles up sidewall 36 away from third space 20.
Please with reference to Fig. 1, dielectric element 38 is configurable on first stacked structure 4, second stacked structure 6, the 3rd stacked structure 8 and the 4th stacked structure 10.Dielectric element 38 for example comprises first dielectric part 40, second dielectric part 42, the 3rd dielectric part 44, the 4th dielectric part 46, the 5th dielectric part 48, the 6th dielectric part 50, the 7th dielectric part 52 and the 8th dielectric part 54.First dielectric part 40 is disposed at first and piles up on the sidewall 22.Second dielectric part 42 is disposed in first gap 16.The 3rd dielectric part 44 is disposed at the 4th and piles up on the sidewall 28.The 4th dielectric part 46 is disposed at the 5th and piles up on the sidewall 30.The 5th dielectric part 48 is disposed in the third space 20.The 6th dielectric part 50 is disposed at the 8th and piles up on the sidewall 36.The 7th dielectric part 52 is configured on the upper surface of first stacked structure 4 and second stacked structure 6.The 8th dielectric part 54 is configured on the upper surface of the 3rd stacked structure 8 and the 4th stacked structure 10.
Please with reference to Fig. 1, conductor wire 56 is disposed on the dielectric element 38.For instance, conductor wire 56 is disposed in second gap 18 and between the 3rd dielectric part 44 and the 4th dielectric part 46.First dielectric part 40 is between first stacked structure 4 and conductor wire 56.The 3rd dielectric part 44 is between second stacked structure 6 and conductor wire 56.The 4th dielectric part 46 is between the 3rd stacked structure 8 and conductor wire 56.The 6th dielectric part 50 is between the 4th stacked structure 10 and conductor wire 56.In one embodiment, conductor wire 56 is as word line (WL).Conductor wire 56 can comprise for example P+ type polysilicon of metal or semi-conducting material.Moreover please with reference to Fig. 1, first stacked structure 4 and second stacked structure 6 are only spaced-apart through second dielectric part 42.The 3rd stacked structure 8 and the 4th stacked structure 10 are only spaced-apart through the 5th dielectric part 48.Because memory cell has asymmetric structure, so the size of memory cell (directions X) can be reduced further.Please with reference to Fig. 2, for instance, (directions X) half spacing (half pitch) of asymmetric vertical gate) but the E micro to below about 18nm.Therefore semiconductor structure has very high component density.
In one embodiment, for instance, second of first stacked structure 4 piles up the 3rd of the sidewall 24 and second stacked structure 6 and piles up and be about 15nm apart from F between the sidewall 26.The thickness G of the conductive stripe 12 of first stacked structure 4 is about 10nm.The thickness K that first of first stacked structure 4 piles up first dielectric part 40 on the sidewall 22 is about 15nm.The thickness M of the conductor wire 56 on first dielectric part 40 is about 10nm.In other embodiments, for instance, second pile up sidewall 24 and the 3rd pile up between the sidewall 26 apart from F can less than the 4th pile up sidewall 28 and the 5th pile up between the sidewall 30 apart from N.Can be apart from F less than the twice of the thickness Q of the 3rd dielectric part 44 (that is F＜2Q).Can be apart from F greater than 1/2nd times of thickness Q (that is F＞Q/2).Can be less than or equal to 30nm apart from F.Can be apart from N more than or equal to 30nm.Thickness Q can be greater than 12nm.In certain embodiments, be 16nm apart from F.Apart from N is 24nm.Thickness Q is 14nm.In one embodiment, the drain side of three-dimensional perpendicular grid storage device has the design of diode, and source side has the stack layer of each layer.In other embodiments, source side has the design of diode, and drain side has the stack layer of each layer.
Please with reference to Fig. 1, dielectric element 38 can have single dielectric material.In other words, each of first dielectric part 40, second dielectric part 42, the 3rd dielectric part 44, the 4th dielectric part 46, the 5th dielectric part 48, the 6th dielectric part 50, the 7th dielectric part 52 and the 8th dielectric part 54 has single dielectric material.In one embodiment, dielectric element 38 constitutes as anti-fuse accumulation layer and by anti-fuse materials, for instance, can comprise for example silica or nitride silicon nitride for example of oxide.
Fig. 3 illustrates the semiconductor structure of another embodiment.The semiconductor structure of Fig. 3 and the semiconductor structure of Fig. 1 different be in, in dielectric element 138, second dielectric part 142 and the 5th dielectric part 148 have single dielectric material, comprise for example silica of oxide; And each of first dielectric part 140, the 3rd dielectric part 144, the 4th dielectric part 146, the 6th dielectric part 150, the 7th dielectric part 152 and the 8th dielectric part 154 has the sandwich construction that the for example dielectric layer 135,137,139 by most different dielectric materials (comprising for example silica or nitride silicon nitride for example of oxide for example) is constituted.In one embodiment, dielectric layer 135 and 139 has silica, and dielectric layer 137 has silicon nitride, and dielectric layer 135,137 and 139 constitutes the sandwich construction of an ONO.For instance, the thickness of dielectric layer 135 can be 5nm-10nm.The thickness of dielectric layer 137 can be 5nm-10nm.The thickness of dielectric layer 139 can be 5nm-12nm.。In one embodiment, dielectric layer 137 is as charge storage layer.
Fig. 4 illustrates the semiconductor structure of an embodiment.The semiconductor structure of Fig. 4 and the semiconductor structure of Fig. 3 different be in; In dielectric element 538; Each of first dielectric part 540, the 3rd dielectric part 544, the 4th dielectric part 546, the 6th dielectric part 550, the 7th dielectric part 552 and the 8th dielectric part 554 has the ONONO structure; Wherein dielectric layer 521,525 and 529 can be silica, and dielectric layer 523 and 527 can be silicon nitride.In addition, the thickness of dielectric layer 521,523,525 is less than dielectric layer 527,529.For instance, the thickness of dielectric layer 521,523,525 can be respectively 1nm-3nm.The thickness of dielectric layer 527 can be 5nm-10nm.The thickness of dielectric layer 529 can be 5nm-12nm.In one embodiment, dielectric layer 521,523 and 525 pierces the tunnel structure as electricity.Dielectric layer 527 is as charge storage layer.Dielectric layer 523 is as tunneling dielectric layer.
Please with reference to Fig. 4; For instance; Distance (in this example, can be considered the thickness of second dielectric part 542) between (as bit line) conductive stripe 512 of first stacked structure 504 and second stacked structure 506 will equal the thickness of the 3rd dielectric part 544 or the 7th dielectric part 552 (having the ONONO structure) at least, to avoid having too high coupling capacitance between the contiguous conductive stripe 512.
Fig. 5 illustrates the semiconductor structure of an embodiment.The semiconductor structure of Fig. 5 and the semiconductor structure of Fig. 1 different be in, dielectric element 238 is made up of most different dielectric materials.For instance, each sandwich construction that is constituted for dielectric layer 235,237,239 of first dielectric part 240, the 3rd dielectric part 244, the 4th dielectric part 246, the 6th dielectric part 250, the 7th dielectric part 252 and the 8th dielectric part 254.In one embodiment, dielectric layer 235 and 239 has silica, and dielectric layer 237 has silicon nitride, and dielectric layer 235,237 and 239 constitutes the sandwich construction of an ONO.Second dielectric part 242 also is made up of the different dielectric material that dielectric layer 235,237 and 239 is comprised with the 5th dielectric part 248.
Fig. 6 to Figure 12 illustrates the manufacturing approach of semiconductor structure among the embodiment.Please with reference to Fig. 6, stacked conductive layer 403 and insulating barrier 405 alternately in substrate 402.Conductive layer 403 is separated from each other through insulating barrier 405.Conductive layer 403 electrically isolates from substrate 402.Substrate 402 can comprise for example silica of oxide.Substrate 402 also can comprise silicon base, and electrically isolates from conductive layer 403 through a dielectric layer (not shown).
Please, on conductive layer that piles up 403 and insulating barrier 405, form the mask layer 407 of patterning with reference to Fig. 7.Remove the part that conductive layer 403 and the not masked layer 407 of insulating barrier 405 cover, to form first stacked structure 404 as shown in Figure 8, second stacked structure 406, the 3rd stacked structure 408 and the 4th stacked structure 410.Each of first stacked structure 404, second stacked structure 406, the 3rd stacked structure 408 and the 4th stacked structure 410 comprises the conductive stripe 412 and insulation striped 414 that is staggeredly stacked.
Please with reference to Fig. 9, on first stacked structure 404, second stacked structure 406, the 3rd stacked structure 408 and the 4th stacked structure 410, form dielectric element 438.Please, on dielectric element 438, form electric conducting material 439 with reference to Figure 10.Contact material 441 can be formed on the electric conducting material 439.In one embodiment, electric conducting material 439 comprises for example P+ type polysilicon, and contact material 441 comprises for example tungsten silicide of metal silicide.Please, on contact material 441, form the mask layer 443 of patterning with reference to Figure 11.Remove not masked layer 443 part of covering of electric conducting material 439 and contact material 441 to form conductor wire shown in figure 12 456 and contact structures 458.
Though disclose as above the present invention in conjunction with above preferred embodiment; Yet it is not in order to limit the present invention; Anyly be familiar with this operator; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining who encloses.
Claims (10)
1. semiconductor structure comprises:
Substrate;
First stacked structure and second stacked structure are disposed in this substrate, and wherein each of this first stacked structure and this second stacked structure comprises the conductive stripe and insulation striped that is staggeredly stacked, and this conductive stripe through this insulation striped separately;
Dielectric element is disposed on this first stacked structure and this second stacked structure and comprises second dielectric part, and wherein this first stacked structure and this second stacked structure are only spaced-apart through this second dielectric part; And
Conductor wire, be disposed at this first stacked structure and this second stacked structure away from the piling up on the sidewall of this second dielectric part, wherein this dielectric element is between between this conductor wire and this first stacked structure and between this conductor wire and this second stacked structure.
2. semiconductor structure as claimed in claim 1, wherein,
Have one first gap between this first stacked structure and this second stacked structure,
This first stacked structure comprises that relative one first piles up sidewall and one second and piles up sidewall,
This second stacked structure comprises that relative one the 3rd piles up sidewall and the 4th and piles up sidewall,
This first piles up sidewall and the 4th and piles up sidewall away from this first gap, and this second piles up sidewall and the 3rd and pile up contiguous this first gap of sidewall,
This dielectric element also comprises:
First dielectric part is disposed at this and first piles up on the sidewall; And
The 3rd dielectric part is disposed at the 4th and piles up on the sidewall,
Wherein this second dielectric part is disposed in this first gap.
3. semiconductor structure as claimed in claim 2, wherein this first dielectric part is between this first stacked structure and this conductor wire, and the 3rd dielectric part is between this second stacked structure and this conductor wire.
4. semiconductor structure as claimed in claim 2 also comprises the 3rd stacked structure, wherein,
Have second gap between this second stacked structure and the 3rd stacked structure,
The 3rd stacked structure comprises that relative one the 5th piles up sidewall and the 6th and piles up sidewall,
The 4th piles up sidewall and the 5th piles up contiguous this second gap of sidewall, and the 3rd piles up sidewall and the 6th piles up sidewall away from this second gap,
This dielectric element also comprises the 4th dielectric part, and the 4th dielectric part is disposed at the 5th and piles up on the sidewall,
This conductor wire is disposed in this second gap and between the 3rd dielectric part and the 4th dielectric part.
5. semiconductor structure as claimed in claim 4 also comprises the 4th stacked structure, wherein,
Have third space between the 3rd stacked structure and the 4th stacked structure,
The 4th stacked structure comprises that relative one the 7th piles up sidewall and the 8th and piles up sidewall,
The 6th piles up sidewall and the 7th piles up contiguous this third space of sidewall, and the 5th piles up sidewall and the 8th piles up sidewall away from this third space,
This dielectric element also comprises the 5th dielectric part and the 6th dielectric part, and the 5th dielectric part is disposed in this third space, and the 6th dielectric part is disposed at the 8th and piles up on the sidewall.
6. the manufacturing approach of a semiconductor structure comprises:
In a substrate, form one first stacked structure and one second stacked structure, wherein each of this first stacked structure and this second stacked structure comprises the conductive stripe and insulation striped that is staggeredly stacked, and this conductive stripe is separated through this striped that insulate; And
Form a dielectric element on this first stacked structure and this second stacked structure, wherein this dielectric element comprises second dielectric part, and this first stacked structure and this second stacked structure are only spaced-apart through this second dielectric part.
7. the manufacturing approach of semiconductor structure as claimed in claim 6; Also comprise form a conductor wire in this first stacked structure and this second stacked structure away from the piling up on the sidewall of this second dielectric part, wherein this dielectric element is between between this conductor wire and this first stacked structure and between this conductor wire and this second stacked structure.
8. the manufacturing approach of semiconductor structure as claimed in claim 6, wherein,
Have first gap between this first stacked structure and this second stacked structure,
This first stacked structure comprises that relative one first piles up sidewall and one second and piles up sidewall,
This second stacked structure comprises that relative one the 3rd piles up sidewall and the 4th and piles up sidewall,
This first piles up sidewall and the 4th and piles up sidewall away from this first gap, and this second piles up sidewall and the 3rd and pile up contiguous this first gap of sidewall,
This dielectric element also comprises:
One first dielectric part is disposed at this and first piles up on the sidewall; And
One the 3rd dielectric part is disposed at the 4th and piles up on the sidewall,
Wherein this second dielectric part is disposed in this first gap.
9. the manufacturing approach of semiconductor structure as claimed in claim 8 also comprises forming a conductor wire, and wherein this first dielectric part is between this first stacked structure and this conductor wire, and the 3rd dielectric part is between this second stacked structure and this conductor wire.
10. the manufacturing approach of semiconductor structure as claimed in claim 8 also comprises:
Form one the 3rd stacked structure; And
Form a conductor wire, wherein,
Have second gap between this second stacked structure and the 3rd stacked structure,
The 3rd stacked structure comprises that relative one the 5th piles up sidewall and the 6th and piles up sidewall,
The 4th piles up sidewall and the 5th piles up contiguous this second gap of sidewall, and the 3rd piles up sidewall and the 6th piles up sidewall away from this second gap,
This dielectric element also comprises the 4th dielectric part, and the 4th dielectric part is disposed at the 5th and piles up on the sidewall,
This conductor wire is disposed in this second gap and between the 3rd dielectric part and the 4th dielectric part.
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Application publication date: 20120815 |