CN102640291A - 自对准接触部 - Google Patents

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Publication number
CN102640291A
CN102640291A CN2010800545535A CN201080054553A CN102640291A CN 102640291 A CN102640291 A CN 102640291A CN 2010800545535 A CN2010800545535 A CN 2010800545535A CN 201080054553 A CN201080054553 A CN 201080054553A CN 102640291 A CN102640291 A CN 102640291A
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China
Prior art keywords
layer
gate electrode
insulator cap
metal
interval body
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CN2010800545535A
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CN102640291B (zh
Inventor
M·T·博尔
T·加尼
N·M·拉哈尔-乌拉比
S·乔希
J·M·施泰格瓦尔德
J·W·克劳斯
J·黄
R·马茨凯维奇
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Intel Corp
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Intel Corp
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Priority to CN201510084707.XA priority Critical patent/CN104795444B/zh
Publication of CN102640291A publication Critical patent/CN102640291A/zh
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Abstract

一种晶体管，包括衬底、在所述衬底上的间隔体对、在所述衬底上且在所述间隔体对之间的栅极电介质层、在所述栅极电介质层上且在所述间隔体对之间的栅电极层、在所述栅电极层上且在所述间隔体对之间的绝缘帽层以及邻近所述间隔体对的扩散区对。所述绝缘帽层形成蚀刻停止结构，所述蚀刻停止结构与所述栅极自对准，并且防止接触部蚀刻使所述栅电极暴露，由此防止所述栅极与所述接触部之间的短路。所述绝缘帽层能够使接触部自对准，这使得较宽接触部的初始构图对构图限制而言更加鲁棒。

Description

自对准接触部
背景技术
在集成电路的制造中使用金属氧化物半导体（MOS）晶体管，诸如MOS场效应晶体管（MOSFET）。MOS晶体管包括诸如栅电极、栅极电介质层、间隔体等若干部件以及诸如源区和漏区等扩散区。层间电介质（ILD）通常形成在MOS晶体管之上并且覆盖扩散区。
通过接触插塞的方式对MOS晶体管进行电连接，接触插塞通常由诸如钨等金属形成。首先通过对ILD层进行构图以形成向下至扩散区的过孔来制造接触插塞。构图工艺通常是光刻工艺。接下来，将金属沉积在过孔中以形成接触插塞。通过使用同样的或类似的工艺，向下至栅电极形成分离的接触插塞。
在接触插塞的制造期间可能发生的一个问题是形成接触部到栅极短路。接触部到栅极短路是当接触插塞未对准并且与栅电极电接触时发生的短路。一种用于防止接触部到栅极短路的常规方法是通过控制定位（registration）和临界尺寸（CD）。但是不幸的是，对于具有小于或等于100纳米（nm）的栅极间距（栅极长度+间隔）的晶体管而言，对栅极和接触部尺寸的CD控制需要小于10nm，并且栅极与接触层之间的定位控制也需要小于10nm，以便实现可制造的工艺窗口（process window）。因此，对栅极的接触短路的可能性很高。随着晶体管栅极间距尺寸的进一步缩减，因为临界尺寸变得小得多，所以该问题变得更加普遍。
附图说明
图1A示出了具有正确对准的沟槽接触部的两个常规的MOS晶体管和衬底。
图1B示出了形成到MOS晶体管的扩散区的、导致接触部到栅极短路的未对准的沟槽接触部。
图2A示出了根据本发明的一个实施方式的在它们各自的金属栅电极的顶上具有绝缘帽层的两个MOS晶体管和衬底。
图2B示出了在具有绝缘帽层的本发明的两个MOS晶体管之间形成的正确对准的沟槽接触部。
图2C示出了在具有绝缘帽层的本发明的两个MOS晶体管之间形成的未对准的沟槽接触部，其中未对准未导致接触部到栅极短路。
图3A至3C示出了根据本发明的实施方式的、在置换金属栅极工艺之后形成的绝缘帽层。
图4A至4C示出了根据本发明的另一实施方式的、在置换金属栅极工艺之后形成的绝缘帽层。
图5A至5I示出了在根据本发明的实施方式的、在MOS晶体管的间隔体之上延伸的绝缘帽层的制造工艺。
图6A至6F示出了根据本发明的实施方式的、具有阶梯式剖面的金属栅电极的制造工艺。
图7A至7C示出了根据本发明的实施方式的、具有有着阶梯式剖面的金属栅电极和在间隔体之上延伸的绝缘帽层两者的MOS晶体管。
图8A至8F示出了根据本发明的实施方式的接触部侧壁间隔体。
图9A至9D示出了根据本发明的实施方式的、在金属栅电极的顶上形成绝缘帽的制造工艺。
图10A至10G示出了根据本发明的实施方式的、在沟槽接触部的顶上形成金属螺栓（stud）和绝缘间隔体的制造工艺。
具体实施方式
这里描述了用于在金属氧化物半导体（MOS）晶体管的制造期间减少接触部到栅极短路的可能性的系统和方法。在以下描述中，将会使用本领域技术人员通常用来将他们的工作的实质传达给本领域的其他技术人员的术语来描述说明性的实施方式的各方面。然而，对本领域的技术人员而言将更加明显的是，可以仅利用所描述的方面中的一些来实施本发明。出于解释的目的，阐述具体数字、材料和结构，以便提供对说明性的实施方式的透彻理解。然而，对本领域的技术人员而言将更加明显的是，可以在没有具体细节的情况下实施本发明。在其它情况下，省略或者简化众所周知的特征，以免使说明性的实施方式难以理解。
以最有助于理解本发明的方式，将各种操作依次描述为多个分立的操作，然而，不应当将描述的顺序解释为暗示这些操作必须依赖于顺序。更具体地，这些操作无需以所介绍的顺序来执行。
图1A示出了衬底100和两个MOS晶体管101。MOS晶体管101包括栅电极102、栅极电介质层104和间隔体108。在衬底100中形成扩散区106。诸如ILD层110a和110b等层间电介质（ILD）沉积在两个MOS晶体管101之间和周围的区域中。
图1A也示出了穿过ILD层110a/b向下形成到扩散区106的沟槽接触部200。通常使用光刻构图工艺接着使用金属沉积工艺，来形成沟槽接触部200。光刻构图工艺和金属沉积工艺是本领域公知的。光刻构图工艺穿过ILD层110a/b向下至扩散区106来蚀刻沟槽开口。诸如电镀、无电镀覆、化学气相沉积、物理气相沉积、溅射或原子层沉积等金属沉积工艺利用诸如钨或铜等金属来填充沟槽开口。在金属之前通常沉积金属衬垫（liner），诸如钽或氮化钽衬垫。诸如化学机械抛光（CMP）等平坦化工艺用于去除任何过量金属并且完成沟槽接触部200的制造。
应当注意的是，在本发明的替换实施方式中，可以使用过孔接触部替代沟槽接触部。因此，接触部开口可以是沟槽形或者过孔形，这取决于所使用的构图工艺或具体集成电路工艺的需要。这里描述的本发明的实施方式将涉及接触部沟槽开口和沟槽接触部，但是应当注意的是在任何这些实施方式中，能够使用过孔开口和过孔接触部（也称为接触插塞或过孔插塞）来代替接触部沟槽开口和沟槽接触部。
随着集成电路技术的进展，晶体管栅极间距逐渐缩减。该栅极间距缩减导致许多新的、棘手的问题，问题之一是由一侧上的沟槽接触部200和扩散区106与另一侧上的栅电极102之间的相对紧密的间隔引起的增加的寄生电容（在图1A中由“C”表示）。间隔体108倾向于在沟槽接触部200/扩散区106与栅电极102之间提供分隔的块体。诸如氮化硅等常规的间隔体材料几乎起不到减小该寄生电容的作用。不幸的是，寄生电容降低晶体管性能并且增大芯片功率。
由栅极间距缩减所引起的另一棘手的问题是接触部到栅极（CTG）短路的形成。将用于沟槽接触部200的制造工艺设计为防止沟槽接触部200与金属栅电极102物理接触。当这种接触发生时，形成CTG短路，该CTG短路实际上破坏了MOS晶体管。由于晶体管栅极间距已经缩减到100纳米（nm）以下，所以CTG短路已经变成主要的成品率限制因素。
当前用于减少CTG短路的方法包括控制定位和对具有较小临界尺寸的接触部进行构图。然而，由于栅极间距已经缩减，所以定位要求变得非常难以与现有技术相适应。例如，栅极间距小于或等于100nm的晶体管需要小于10nm的层定位控制和CD控制，以实现可制造的工艺窗口。因此，对栅极的接触短路的可能性非常高。
图1B示出了当沟槽接触部200未对准时发生的情况。使用了相同的光刻工艺，但是如图所示，沟槽接触部200的形成位置不完全处于两个间隔体108之间的区域内。未对准导致沟槽接触部200与栅电极102之一物理接触，从而产生接触部到栅极短路。
根据本发明的实施方式，绝缘帽栅电极可以用于最小化接触部到栅极短路的可能性。在一个实施方式中，绝缘帽层形成在栅电极102的顶上，并且在MOS晶体管101的间隔体108内。在本发明的一些实施方式中，绝缘帽能够占据间隔体之间存在的很大部分体积。例如，绝缘帽能够占据间隔体之间存在的体积的10%至80%间的任何比例，但是通常占据体积的20%至50%。栅电极和栅极电介质层占据大部分的剩余体积。以下描述可以用于形成绝缘帽的材料。
图2A示出了根据本发明的一个实施方式的绝缘帽金属栅电极。图2A中示出了衬底100，在衬底100上形成MOS晶体管101。衬底100可以是通过使用体硅衬底或绝缘体上硅子结构而形成的晶体半导体衬底。在其它实施方式中，可以使用替代材料来形成半导体衬底，替代材料可以与或不与硅结合，其包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓或其它III-V族材料。虽然这里描述了可以形成衬底的材料的几个示例，但是可以用作可以在其上构建半导体器件的基础的任何材料都落入本发明的精神和范围内。
如图2A中所示，每个MOS晶体管101可以是平面晶体管，或者可以是诸如双栅极或三栅极晶体管等非平面晶体管。虽然这里描述的实施方式例示了平面晶体管，但是本发明不限于平面晶体管。本发明的实施方式也可以用于非平面晶体管，包括但不限于FinFET或三栅极晶体管。每个MOS晶体管101包括由以下三层所形成的栅极叠置体：栅极电介质层104、栅电极层102和绝缘帽层300。栅极电介质层104可以由诸如二氧化硅或高k材料等材料形成。可以在栅极电介质层104中使用的高k材料的示例包括但不限于氧化铪、氧化硅铪、氧化镧、氧化铝镧、氧化锆、氧化硅锆、氧化钽、氧化钛、氧化钛锶钡、氧化钛钡、氧化钛锶、氧化钇、氧化铝、氧化钽钪铅和铌锌酸铅。在一些实施例中，栅极电介质层104的厚度可以在约1埃
Figure BDA00001715530300051
至约50埃之间。在另一实施例中，可以在栅极电介质层104上执行诸如退火工艺等附加工艺，以便在使用高k材料时提高其质量。
栅电极层102形成在栅极电介质层104上并且可以至少由P型功函数金属或N型功函数金属构成，这取决于晶体管是PMOS晶体管还是NMOS晶体管。在一些实施方式中，栅电极层102可以由两层或更多层金属层构成，其中至少一层金属层是功函数金属层，并且至少一层金属层是填充金属层。
对于PMOS晶体管而言，可以用于栅电极的金属包括但不限于钌、钯、铂、钴、镍和导电金属氧化物（例如氧化钌）。P型金属层将允许形成具有约4.9eV至约5.2eV之间的功函数的PMOS栅电极。对于NMOS晶体管而言，可以用于栅电极的金属包括但不限于铪、锆、钛、钽、铝、这些金属的合金以及诸如碳化铪、碳化锆、碳化钛、碳化钽和碳化铝等这些金属的碳化物。N型金属层将允许形成具有约3.9eV至约4.2eV之间的功函数的NMOS栅电极。
绝缘帽层300形成在栅电极层102上，并且可以由包括但不限于以下材料的材料形成：氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅、其它氮化物材料、其它碳化物材料、氧化铝、其它氧化物材料、其它金属氧化物、氮化硼、碳化硼以及其它低k电介质材料或掺杂有碳、氮和氢中的一种或多种的低k电介质材料。以下将更详细地描述绝缘帽层300。
一对间隔体108把栅极叠置体围住。间隔体108可以由诸如氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅和氮氧化硅等材料形成。用于形成间隔体的工艺是本领域公知的，并且通常包括沉积和蚀刻工艺步骤。
扩散区106形成在邻近MOS晶体管101的栅极叠置体的衬底100内。对于每个MOS晶体管101而言，一个邻近的扩散区106起到源区的作用，而另一个邻近的扩散区106起到漏区的作用。
可以使用本领域公知的方法或工艺来形成扩散区106。在一个实施方式中，可以将诸如硼、铝、锑、磷或砷等掺杂剂注入衬底100中，以形成扩散区106。在另一实施方式中，首先，可以蚀刻衬底100以在扩散区106的位置处形成凹槽。然后，可以进行外延沉积工艺来利用诸如硅锗或碳化硅等硅合金填充凹槽，由此形成扩散区106。在一些实施方式中，可以用诸如硼、砷或磷等掺杂剂对外延沉积的硅合金进行原位掺杂。在另一实施方式中，可以将替代材料沉积到凹槽中，以形成扩散区106。
在MOS晶体管101之上沉积一层或多层ILD层110a/b。可以使用诸如低k电介质材料等以其在集成电路结构中的适用性而闻名的电介质材料来形成ILD层110a/b。可以使用的电介质材料的示例包括但不限于二氧化硅（SiO2）、掺杂碳氧化物（CDO）、氮化硅、诸如八氟环丁烷或聚四氟乙烯等有机聚合物、氟硅酸盐玻璃（FSG）以及诸如倍半硅氧烷、硅氧烷或有机硅酸盐玻璃等有机硅酸盐。ILD层110a/b可以包括气孔（pore）或其它空隙（void），以进一步减小其介电常数。
也被称为接触部构图的沟槽接触部200的制造至少涉及光刻工艺和蚀刻工艺。光刻工艺形成限定沟槽接触部200的位置的光刻胶硬掩膜。光刻工艺从在ILD层110b上沉积光刻胶材料开始。将所沉积的光刻胶层通过经构图的光掩模而暴露于紫外线辐射，其中图案限定沟槽接触部200。然后对光刻胶层进行显影，以形成包括待形成沟槽接触部200的开口的光刻胶硬掩膜层。应当注意的是，光刻工艺是本领域公知的，并且此描述仅是典型的光刻工艺的简要概述。已经省略了许多诸如烘烤和对准步骤等中间步骤。
一旦将光刻胶硬掩膜设置在限定沟槽接触部200的位置，就进行蚀刻工艺。蚀刻剂蚀刻ILD层110a/b被光刻胶硬掩膜中的开口（诸如用于沟槽接触部200的开口）暴露出来的部分。由此，蚀刻剂将沟槽开口向下蚀刻至扩散区106。所使用的蚀刻工艺可以是常规的化学湿法蚀刻工艺或等离子体干法蚀刻工艺。进行蚀刻工艺一段时间（表示为TETCH），该一段时间足以蚀刻ILD层110一直向下至扩散区106。然后，用上述的一种或多种金属填充所蚀刻的沟槽开口，以形成沟槽接触部200。
根据本发明的实施方式，绝缘帽层300的厚度足以在沟槽接触部200的制造期间、当接触部沟槽开口在绝缘帽层之上对准时保护金属栅电极102，使其不被暴露。而且，绝缘帽层300的厚度足以在形成沟槽接触部200后使金属栅电极102与沟槽接触部200电隔离。在本发明的一个实施方式中，该厚度的范围可以从5nm至50nm。在另一实施方式中，绝缘帽层的高度可以占栅极叠置体的整个高度的20%至80%。用于形成接触部沟槽开口的蚀刻工艺对绝缘帽层300是选择性的。这意味着湿法或干法蚀刻化学试剂（chemistry）会蚀刻ILD层110a/b的材料，但是会选择性地停止并且与绝缘帽层300以及侧壁间隔体108自对准。
根据本发明的实施方式，绝缘帽层300的厚度也足以经受整个TETCH期间的蚀刻工艺，而不暴露下面的金属栅电极102。也就是说，绝缘帽层300的初始厚度足以经受蚀刻ILD层110a/b一直向下至扩散区106所需的时间段期间的蚀刻工艺，而不会使绝缘帽层300的任何部分的厚度减小至将允许金属栅电极102与随后形成的沟槽接触部200之间的电导性的厚度。在蚀刻工艺后，绝缘帽层300与间隔体108的组合使金属栅电极102与沟槽接触部200电隔离，由此消除了CTG短路。
存在多种不同的形成本发明的绝缘帽层300的方法。在本发明的一个实施方式中（其中使用先栅极工艺来形成栅电极102），首先在衬底上沉积均厚（blanket）电介质层。接着，均厚电极层沉积在电介质层的顶上。最后，均厚绝缘层形成在电极层的顶上。用于沉积电介质层、电极层和绝缘层的沉积工艺是本领域公知的，可以包括但不限于诸如电镀、无电镀覆、化学气相沉积、原子层沉积、物理气相沉积和溅射等工艺。然后使用诸如光刻工艺等常规的构图工艺蚀刻所述三层，以形成由栅极电介质层104、栅电极层102和绝缘帽层300构成的栅极叠置体。然后在栅极叠置体的相对侧上形成间隔体108和扩散区106。在栅极叠置体、间隔体108和扩散区110之上沉积ILD层110a。随后可以如上所述地形成沟槽接触部200。
在先栅极工艺的替代实施方式中，可以沉积均厚电介质层和均厚电极层并对其进行构图以形成由栅极电介质层104和栅电极102构成的栅极叠置体。可以在栅极叠置体的任一侧上形成一对间隔体108和扩散区106。接着，可以执行蚀刻工艺，以使金属栅电极102凹入间隔体108内，由此减小金属栅电极102的厚度。金属栅电极102的凹入导致间隔体108之间的沟槽的形成，其中沟槽的底表面对应于凹入的金属栅电极102的顶表面。金属蚀刻工艺之后是绝缘材料沉积工艺，所述绝缘材料沉积工艺沉积绝缘材料的均厚层并且填充间隔体108之间的沟槽。诸如化学机械平坦化工艺等抛光工艺用于向下抛光绝缘材料层，并且大体上去除间隔体108外部的任何绝缘材料。该过量绝缘材料的去除产生了大体上包含在间隔体108内的绝缘帽层300。
在本发明的另一实施方式中，诸如置换金属栅极工艺等后栅极工艺用于形成栅电极。在此实施方式中，首先可以沉积均厚电介质层和均厚伪电极层，并对其进行构图以形成由栅极电介质层104和伪栅电极（未示出）构成的栅极叠置体。应当注意的是术语“伪”用于表示该层实际上是牺牲层。伪层中所使用的材料可以与非伪层中所使用的材料相同或不同。例如，伪电极层可以由实栅电极中所使用的多晶硅构成。可以在栅极叠置体的任一侧上形成一对间隔体108和扩散区106。接着，可以将伪栅电极蚀刻出来，从而在间隔体108之间和栅极电介质层104的顶上形成沟槽。随后，可以沉积电极金属层，以填充沟槽。可以向下抛光电极金属层以去除间隔体108外部的金属，并且将电极金属限制至间隔体108之间的沟槽，由此形成金属栅电极102。
如上所述，执行蚀刻工艺，以使金属栅电极102凹入间隔体108内。金属栅电极102的凹入导致在间隔体108之间的沟槽的形成。绝缘材料沉积工艺填充沟槽，抛光工艺用于向下抛光绝缘材料层并且大体上去除间隔体108外部的任何绝缘材料。这产生了大体上包含在间隔体108内的绝缘帽层300。
图2B示出了在具有绝缘帽层300的两个MOS晶体管之间正确对准的沟槽接触部200。在此示例中，未使用绝缘帽300。
图2C示出了在具有绝缘帽层300的两个MOS晶体管之间形成的未对准的沟槽接触部200。如图所示，部分未对准的沟槽接触部200直接位于栅电极102之上。然而，与图1B中所示的现有技术晶体管不同，由于绝缘帽层300的使用，避免了CTG短路。绝缘帽层300使金属栅电极102与未对准沟槽接触部200电隔离，这使得沟槽接触部200“自对准”。
图3A至3C示出了图2A的晶体管基础上的细微变型。在图3A中，使用不同的置换金属栅极工艺的实施方式来形成晶体管。在此实施方式中，将均厚伪电介质层和均厚伪电极层沉积在衬底上。这里，伪电极层可以由多晶硅构成，而伪电介质层可以由二氧化硅构成，多晶硅和二氧化硅两者都用于实栅电极和实栅极电介质层中。蚀刻这两层伪层以形成由伪栅极电介质层和伪栅电极层构成的栅极叠置体。然后在栅极叠置体的相对侧上形成间隔体108和扩散区106。在栅极叠置体、间隔体108和扩散区106之上沉积ILD层110a。将ILD层110a平坦化，以暴露伪电极层。
接着，使用一种或多种蚀刻工艺来去除伪电极层和伪栅极电介质层。伪层的去除在间隔体108之间产生沟槽。衬底100形成沟槽的底表面。使用化学气相沉积工艺或原子层沉积工艺来将新的高k栅极电介质层104沉积在沟槽中。如图3A中所示，沿沟槽的底部和侧壁沉积高k栅极电介质层104，由此形成“U”形栅极电介质层104。接着，在高k栅极电介质层104的顶上沉积金属栅电极层102。用于形成金属栅电极102的工艺是本领域公知的。
根据本发明的实施方式，最终的金属栅电极102未完全填充沟槽。在一个实施方式中，金属栅电极102可以首先完全填充沟槽，而随后可以使用蚀刻工艺来使金属栅电极102凹入。在另一实施方式中，金属栅电极沉积工艺仅用金属栅电极102部分填充沟槽。在这两个实施方式中，沟槽保持在间隔体108之间最终的金属栅电极102之上。
最后，使用绝缘材料沉积工艺来沉积填充间隔体108之间的沟槽的绝缘材料的均厚层。随后，使用诸如化学机械平坦化工艺等抛光工艺来向下抛光绝缘材料层，并且大体上去除间隔体108外部的任何绝缘材料。该过量绝缘体的去除产生了大体上限制在间隔体108内的绝缘帽层300。如图3A中所示，绝缘帽300也限定在栅极电介质层104的侧壁部分内。
图3B示出了在具有绝缘帽层300的两个MOS晶体管之间正确校准的沟槽接触部200。图3C示出了在具有绝缘帽层300的两个MOS晶体管之间形成的未对准的沟槽接触部200。另外，部分未对准的沟槽接触部200直接位于栅电极102之上。由于使金属栅电极102与未对准的沟槽接触部200电隔离的绝缘帽层300的使用，避免了CTG短路。
图4A至4C示出了图3A的晶体管基础上的细微变型。在图4A中，再次使用置换栅极工艺来形成具有“U”形栅极电介质层104的晶体管。首先，使用与以上针对图3A所详细描述的相同的工艺来形成栅电极层102和栅极电介质层104。与图3A不同，在该实施方式中，在绝缘帽层300的制造之前，使“U”形栅极电介质层104和金属栅电极102两者都凹入。可以使用一种或多种蚀刻工艺来使两种结构都凹入。然后，如图4A中所示，使用与以上针对图3A所描述的相同的工艺来形成绝缘帽300，并且绝缘帽300位于栅电极102和部分栅极电介质层104的顶上。图4B示出了在具有绝缘帽层300的两个MOS晶体管之间正确对准的沟槽接触部200。图4C示出了在具有绝缘帽层300的两个MOS晶体管之间形成的未对准沟槽接触部200。此外，部分未对准沟槽接触部200直接位于栅电极102之上。由于绝缘帽层300的使用，避免了CTG短路，该绝缘帽层300使金属栅电极102与未对准的沟槽接触部200电隔离。
图5A至5F示出了可以与MOS晶体管一起使用的替代的绝缘帽层的制造。首先，图5A示出了包括伪栅电极500和伪栅极电介质层502的两个MOS晶体管。还示出了通常由氮化硅形成的一对间隔体108。
根据本发明的实施方式，执行一种或多种蚀刻工艺，以使伪栅电极层500和间隔体108两者部分地凹入。在图5B中示出了该双凹槽。用于使伪栅电极500凹入的蚀刻化学试剂可以与用于使间隔体108凹入的蚀刻化学试剂不同。所使用的蚀刻工艺可以是湿法蚀刻、干法蚀刻或其组合。当已经使伪栅电极500和间隔体108凹入时，在ILD层110a内形成沟槽503a，其中，伪栅电极500和间隔体108的顶表面形成沟槽的底部。
转向图5C，执行一种或多种蚀刻工艺来完全去除伪栅电极层500和伪栅极电介质502。用于完全去除伪栅电极500和伪栅极电介质层的蚀刻工艺是本领域公知的。此外，这些蚀刻可以是湿法蚀刻、干法蚀刻或其组合。如图5C中所示，沟槽503a现在要深得多，并且沟槽503a的横截面剖面在沟槽503a的顶部相对较宽，而在沟槽503a的底部则相对较窄。完全去除伪栅电极500和伪栅极电介质层502，由此暴露衬底100的顶部。
在图5D中，在沟槽503a中沉积栅极电介质层104和金属栅电极层102。诸如CVD或ALD工艺等共形沉积工艺通常用于栅极电介质层104的沉积，由此产生覆盖沟槽503a的侧壁和底表面的共形电介质层104。金属栅电极层102填充沟槽503a的剩余部分。在本发明的一些实施方式中，金属栅电极层102可以由两层或更多层金属（例如，功函数金属层和填充金属层）构成。
在置换金属栅极工艺流程中，以金属栅极材料来填充窄栅极沟槽是非常有挑战性的，特别是对于具有小于或等于22nm的栅极宽度的晶体管而言。在这里，图5A至5D中所描述的工艺流程通过加宽顶部处的沟槽开口来增强固有的填充特性而不影响底部的窄沟槽宽度。因此，在顶部具有相对较宽的开口的沟槽503a的横截面剖面产生具有较少空隙或其它缺陷的改善的金属栅电极沉积。
接着，如图5E中所示，使金属栅电极层102和栅极电介质层104凹进，以形成沟槽503b。此外，可以使用一种或多种蚀刻工艺（湿法或干法）来使栅电极层102和栅极电介质层104两者凹进。所使用的蚀刻工艺必须对ILD层110a是选择性的。使金属栅电极102凹进直到其顶表面与间隔体108的顶表面相平或者在间隔体108的顶表面以下。虽然在图5D中部分金属栅电极102在间隔体108的顶部上，但重要的是在图5E中，在使金属栅极102凹进之后，金属栅电极102没有保持在间隔体108的顶部之上的部分。这是因为金属栅电极102保持在间隔体108的顶上的任何部分最终都可以形成与未对准的沟槽接触部的CTG短路。
转向图5F，绝缘材料沉积工艺填充沟槽503b，并使用抛光工艺来向下抛光绝缘材料层，并且大体上去除沟槽503b外部的任何绝缘材料。这产生大体上包含在沟槽503b内的绝缘帽层504。由于绝缘帽层504在间隔体108上横向延伸，所以绝缘帽层504具有蘑菇形顶部的外形。绝缘帽层504通过在栅极间隔体108之上延伸来改善接触部到栅极容限（margin）。绝缘帽层504可以由包括但不限于以下材料的材料形成：氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅、其它氮化物材料、其它碳化物材料、氧化铝、其它氧化物材料、其它金属氧化物和低k电介质材料。
图5G示出了覆盖绝缘帽层504并且位于第一ILD层110a顶上的附加ILD层110b的沉积。图5H示出了已经穿过ILD层110a和110b向下制造至扩散区106的沟槽接触部200。已经在相邻晶体管的间隔体108之间正确对准了图5H的沟槽接触部200。
图5I示出了未对准的沟槽接触部200。如图所示，即使沟槽接触部200位于金属栅电极102的顶部上，绝缘帽层504通过使金属栅电极102与未对准的沟槽接触部200电隔离来保护金属栅电极102并且防止CTG短路形成。
由绝缘帽层504所提供的另一优点解决了以上针对图1A所讨论的寄生电容问题。寄生电容问题是由一侧上的沟槽接触部200和扩散区106与另一侧上的栅电极102之间的相对较紧密的间隔所引起的。间隔体108倾向于在沟槽接触部200/扩散区106与栅电极102之间提供分隔的块体，但是诸如氮化硅等常规间隔体材料几乎起不到减小该寄生电容的作用。然而，因为产生用于沟槽接触部200的接触部沟槽开口的蚀刻工艺对氮化硅是选择性的，所以仍使用氮化硅。
根据本发明的该实施方式，可以在间隔体108中使用除了氮化硅以外的材料。在这里，横向延伸的绝缘帽层504在用于制造沟槽接触部200的蚀刻工艺期间保护下面的间隔体108。这些蚀刻工艺通常是各向异性的工艺，因此，蚀刻化学试剂仅需要对绝缘帽层504是选择性的。然后，绝缘帽层504能够保护下面的间隔体108。所以在各向异性工艺的情况下，绝缘帽层504的使用意味着蚀刻化学试剂不一定需要对在间隔体108中使用的材料是选择性的。这去除了对间隔体材料的选择上的任何约束，并且允许使用对于电容而言最优化的材料。例如，诸如氮氧化硅（SiON）、掺杂碳的氮氧化硅（SiOCN）或低k电介质材料等材料可以用在间隔体108中，以减小关于寄生电容的问题。
图6A至6F示出了根据本发明实施方式的、与绝缘帽层结合的阶梯式金属栅电极的形成。首先，图6A示出了包括伪栅电极500和伪栅极电介质层502的两个MOS晶体管。转向图6B，执行一种或多种蚀刻工艺以完全去除伪栅电极500和伪栅极电介质层502。用于完全去除伪栅电极500和伪栅极电介质的蚀刻工艺是本领域公知的。完全去除伪栅电极500与伪栅极电介质502，由此暴露衬底100的顶部。
图6C示出了双金属栅电极层的沉积，双金属栅电极层为共形金属栅电极层102a和可以是共形的或可以是不共形的第二金属层102b。可以使用诸如化学气相沉积或原子层沉积等共形沉积工艺来沉积初始金属栅电极层102a。也可以使用诸如物理气相沉积或溅射等其它工艺。使用诸如化学气相沉积、原子层沉积、物理气相沉积、溅射等常规沉积工艺或甚至诸如电镀或无电镀覆等工艺来沉积第二金属栅电极102b，因为层102b不需要是共形层。
初始的金属栅电极层102a通常是功函数金属层，并且可以使用以上描述的任何功函数金属来形成。第二金属栅电极层102b可以是第二功函数金属层，或者可以是诸如铝、钨或铜等低电阻填充金属层。根据本发明的实施方式，金属栅电极102a中所使用的金属的蚀刻性质与金属栅电极102b中所使用的金属的蚀刻性质不同。
转向图6D，蚀刻双金属栅电极层102a和102b，并使其凹进以形成沟槽600，可以在沟槽600中制造绝缘帽层。根据本发明的实施方式，蚀刻工艺所去除金属层102a的部分大于去除金属层102b的部分。如图6D中所示，这产生了金属栅电极102的阶梯式或子弹式剖面。整个金属栅电极102的中间部分相对厚于整个金属栅电极102的外部边缘部分。也就是说，金属栅电极102的中间部分的高度相对大于金属栅电极102的侧面部分的高度。金属栅电极102的该阶梯式剖面提供了如以下将在图6F中解释的优点。
在一个实施方式中，使用单个蚀刻工艺，该单个蚀刻工艺蚀刻金属栅电极层102a的速率比蚀刻金属栅电极层102b的速率快。换句话说，蚀刻化学试剂对金属栅电极102b更有选择性。在另一实施方式中，可以使用两种蚀刻工艺，一种用于金属层102a，而另一种则用于金属层102b。如果使用两种蚀刻工艺，则相对于金属层102b，必须去除金属层102a更大的部分。因此，在一个实施方式中，两种蚀刻工艺中的第一种可以对金属层102b是选择性的，而两种蚀刻工艺中的第二种可以对金属层102a是选择性的。所使用的蚀刻工艺可以是湿法蚀刻、干法蚀刻或两者的结合。本领域的普通技术人员会理解，对于在金属层102a和102b中所使用的几乎任意金属对而言，可以发现能区分这两种金属的湿法或干法化学蚀刻。
如图6E中所示，绝缘材料沉积工艺填充沟槽600，并且使用抛光工艺来向下抛光绝缘材料层，并且大体上去除沟槽600外部的任何绝缘材料。这产生了大体上包含在沟槽600内的绝缘帽层602。由于金属栅电极102的阶梯式剖面，绝缘帽层602的外部边缘相对较厚，而其中间部分则相对较薄。绝缘帽层602可以由包括但不限于以下材料的材料形成：氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅、其它氮化物材料、其它碳化物材料、氧化铝、其它氧化物材料、其它金属氧化物和低k电介质材料。
图6F示出了未对准的沟槽接触部200。如图所示，即使沟槽接触部200位于金属栅电极102的顶部上，绝缘帽层602通过使金属栅电极102与未对准沟槽接触部200电隔离来保护金属栅电极102并且防止CTG短路形成。金属栅电极102的阶梯式剖面提供至少两个优点。第一，阶梯式剖面使得绝缘帽层602的较厚部分位于金属栅电极102与沟槽接触部200之间，由此提供强的电隔离。第二，阶梯式剖面使得金属栅电极102的中间部分保持较厚，由此通过增加金属栅电极102的金属含量来使其电阻降低。在本发明的各个实施方式中，可以通过设法使金属栅电极102的中间部分的体积或宽度最大化、同时保持金属栅电极102与未对准沟槽接触部200的电隔离来优化阶梯式剖面。在一些实施方式中，这可以通过增加金属栅电极102b的尺寸或厚度来完成。在另一实施方式中，这可以通过以下方式来完成：使用多于两层金属栅电极层，以便更精细地设计阶梯式剖面。
根据本发明的另一实施方式，图7A至7C示出了将图5F的宽绝缘帽层504与图6D至6F的阶梯式剖面金属栅电极102结合的MOS晶体管的制造。从图5C中所示的结构开始，如图7A中所示，沉积双金属栅电极层。一层是共形金属栅电极层102a，而另一层是可以是共形的或可以是不共形的第二金属层102b。初始的金属栅电极层102a通常是功函数金属层，而第二金属栅电极层102b可以是第二功函数金属层或者可以是填充金属层。根据本发明的实施方式，金属栅电极102a中所使用的金属的蚀刻性质与金属栅电极102b中所使用的金属的蚀刻性质不同。
转向图7B，蚀刻双金属栅电极层102a和102b以及栅极电介质层104并且使其凹进。蚀刻工艺对金属栅电极102b是选择性的。如图7B中所示，这产生了金属栅电极102的阶梯式剖面。整个金属栅电极102的中间部分相对厚于整个金属栅电极102的外部边缘部分。
然后，沉积绝缘材料并将其平坦化，以在每个金属栅电极102的顶上形成绝缘帽层700。这在图7C中示出。图7C中还示出了未对准的沟槽接触部200。金属栅电极102的阶梯式剖面允许绝缘帽层700的较厚部分将金属栅电极102与沟槽接触部200电隔离。阶梯式剖面也使得金属栅电极102的中间部分保持较厚，由此减小电阻。在该实施方式中，绝缘帽层700在凹进的间隔体108之上延伸，由此在沟槽接触部200蚀刻工艺期间保护间隔体，并且允许在间隔体108中使用被最优化以减小沟槽接触部200与金属栅电极102之间的寄生电容的材料。
图8A至8F示出了本发明的另一实施方式，其中接触部侧壁间隔体用于减少CTG短路并且用于改善寄生电容问题。图8A示出了已经穿过ILD层110a和110b向下蚀刻至扩散区106的接触部沟槽开口800。如以上所解释的，光刻构图和蚀刻工艺用于形成接触部沟槽开口800。
图8A中还示出了已经形成在接触部沟槽开口800的底部的硅化物层802。为了制造硅化物层802，可以使用诸如溅射沉积工艺或ALD工艺等常规金属沉积工艺来至少沿接触部沟槽开口800的底部形成共形金属层。通常，也会在接触部沟槽开口800的侧壁上沉积金属。该金属可以包括镍、钴、钽、钛、钨、铂、钯、铝、钇、铒、镱或者作为硅化物的良好备选材料的任何其它金属中的一种或多种。随后，可以进行退火工艺以使得金属与扩散区106反应并形成硅化物层802。可以使用已知的工艺来选择性地去除任何未反应的金属。硅化物层802减小了之后形成的沟槽接触部200与扩散区106之间的电阻。
图8B示出了根据本发明实施方式的、沿接触部沟槽开口800的侧壁形成的一对接触部侧壁间隔体804。可以使用与栅极间隔体108的制造相似的沉积和蚀刻工艺来形成接触部侧壁间隔体804。例如，在接触部沟槽开口800内可以沉积绝缘材料的共形层，由此产生了沿接触部沟槽开口800的侧壁和底部表面沉积的绝缘材料。该绝缘材料可以是氧化硅、氮化硅、氮氧化硅（SiON）、掺杂碳的氮氧化硅（SiOCN）、任何其它氧化物、任何其它氮化物或任何低k电介质材料。接着，使用各向异性蚀刻工艺，以从接触部沟槽开口800以及诸如ILD层110b的表面等其它区域去除绝缘材料。这产生了图8B中所示的接触部侧壁间隔体804。
本领域的技术人员将会理解，分离构图工艺可以用于形成向下至金属栅电极102的过孔，以便形成栅极接触部。该分离构图方法通常包括用牺牲的光可限定的光刻胶层涂覆晶片、蚀刻栅极接触部，然后用湿法或干法清洗工艺或其某种组合来去除光刻胶。通常在形成了接触部沟槽开口800后执行该分离的构图工艺，这意味着首先进行光刻胶涂覆，然后湿法或干法清洗化学试剂进入到接触部沟槽开口800，并且能够侵蚀硅化物层802。因此，根据本发明的实施方式，在进行栅极接触部的构图工艺之前，沉积用于形成间隔体804的绝缘材料的共形层。共形层保持在合适的位置，以保护硅化物层802直到栅极接触部已被构图之后。然后可以进行上述的各向异性蚀刻，以蚀刻共形层并形成间隔体804。
应当注意，在接触部侧壁间隔体804的制造之前，即当接触部沟槽开口800处于其最大宽度处时，形成硅化物层802。通过在形成接触部侧壁间隔体804之前形成硅化物层802，能够形成相对较宽的硅化物层802，以提供诸如较低的固有接触部电阻等较好的电阻性质。如果首先形成接触部侧壁间隔体804，则会有较少的扩散区106暴露于硅化物制造工艺，从而产生相对较短的硅化物层。
然后，如在图8C中所示，进行金属沉积工艺，以填充接触部沟槽开口800并形成沟槽接触部200。如以上所注意到的，金属沉积工艺可以是诸如电镀、无电镀覆、化学气相沉积、物理气相沉积、溅射或原子层沉积等任何金属沉积工艺。所使用的金属可以是提供合适的接触性质的任何金属，诸如钨或铜等。通常在诸如钽或氮化钽衬垫等金属之前沉积金属衬垫。CMP工艺用于去除任何过量金属并完成沟槽接触部200的制造。
接触部侧壁间隔体804在栅电极102与沟槽接触部200之间提供附加的保护层。最终的沟槽接触部200的宽度相对窄于使用常规工艺所形成的沟槽接触部200的宽度，由此减小了CTG短路的可能性。并且，栅电极102与沟槽接触部200之间的附加绝缘层减小了寄生电容。
图8D至8F示出了当接触部未对准时的接触部侧壁间隔体804的制造。图8D示出了穿过ILD层110a和110b向下蚀刻至扩散区106的未对准的接触部沟槽开口800。根据本发明的实施方式，绝缘帽层300保护金属栅电极102使其在该蚀刻工艺期间免受暴露。图8D中还示出了已经形成在接触部沟槽开口800的底部的硅化物层802。以上提供了用于硅化物层802的制造工艺。
根据本发明的实施方式，图8E示出了沿的接触部沟槽开口800的侧壁形成的一对接触部侧壁间隔体804。如以上所解释的，通过沉积并蚀刻绝缘材料的共形层，可以形成接触部侧壁间隔体804。
然后，如在图8F中所示，进行金属沉积工艺以填充接触部沟槽开口800并形成沟槽接触部200。另外在这里，接触部侧壁间隔体804在栅电极102与沟槽接触部200之间提供附加的保护层。接触部侧壁间隔体804在最终的沟槽接触部200与金属栅电极102之间提供更多的分隔，由此减少CTG短路的可能性。而且，在栅电极102与沟槽接触部200之间的附加绝缘层减小了寄生电容。
图9A至9D示出了根据本发明实施方式的、用于形成绝缘帽层的另一工艺。图9A示出了具有金属栅电极102和栅极电介质层104的两个MOS晶体管。栅电极层102可以包括两层或更多层（未示出），诸如功函数金属层和填充金属层。虽然所示的栅极电介质层104对应于置换金属栅极工艺，但是以下工艺也可以用于使用先栅极方法所形成的晶体管。
如图9A中所示，在金属栅电极102的顶上形成金属帽900。根据本发明的实施方式，使用选择性沉积工艺来形成金属帽900。一些选择性沉积工艺包括但不限于无电镀覆和化学气相沉积。可以选择性沉积的金属包括但不限于钴、镍、铂、铜、多晶硅、钨、钯、银、金和其它贵金属。本领域的技术人员将会理解，选择使用无电工艺还是选择使用CVD工艺将取决于金属栅电极102的成分以及金属帽900中所使用的具体金属。在一个示例中，如果金属栅电极102的顶部部分由铜金属构成，则钴金属能够无电地沉积在铜上。在另一示例中，钨或多晶硅能够通过CVD沉积在金属栅电极102中所使用的几乎任何金属上。在另一示例中，如果金属栅电极102的顶部部分由贵金属构成，则大多数金属可以使用无电工艺而沉积在贵金属上。本领域的普通技术人员将会理解，通常，对于衬底金属和待沉积的金属两者而言，无电工艺需要贵金属。因此，诸如钴、镍、铜、铂、钯、金和银等金属的组合是可能的。
转向图9B，ILD层902均厚沉积在ILD 110a和金属帽900之上。然后使用CMP工艺来使ILD层902和金属帽900两者平坦化，使得它们的顶表面大体上平坦。在ILD沉积之后完成上述工艺，以暴露金属帽900的顶表面。
接着，如图9C中所示，使用蚀刻工艺来从ILD层902内去除金属帽900。在一个实施方式中，可以应用湿法蚀刻化学试剂，以去除金属帽900。根据本发明的实施方式，所使用的蚀刻化学试剂必须对ILD层902和金属栅电极102两者都是选择性的。这允许在对ILD层902和金属栅电极102产生的影响最小的情况下，去除金属帽900。金属帽900的去除在ILD层902内产生空隙904。
转向图9D，可以沉积诸如氮化硅层等绝缘层并将其平坦化以填充空隙904，由此形成自对准的绝缘帽层906。该绝缘层通常沉积为填充空隙904并且覆盖ILD层902的均厚层。然后，使用平坦化工艺来去除空隙904外部的任何过量材料。这将绝缘材料限制到空隙904，由此形成绝缘帽层906。绝缘帽层906可以由包括但不限于以下材料的材料形成：氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅、其它氮化物材料、其它碳化物材料、氧化铝、其它氧化物材料、其它金属氧化物和低k电介质材料。唯一的约束是绝缘帽层906中所使用的材料与ILD层902中所使用的材料不同。
图10A至10G示出了根据本发明实施方式的、用于形成沟槽接触部200顶上的自对准的金属螺栓和绝缘间隔体对的工艺，该绝缘间隔体对进一步使金属螺栓与金属栅电极102绝缘。图10A示出了具有金属栅电极102和栅极电介质层104的两个MOS晶体管。在两个MOS晶体管之间形成沟槽接触部200。
如图10A中所示，金属帽900形成在沟槽接触部200的顶上。根据本发明的实施方式，使用选择性沉积工艺来形成金属帽900。如以上所注意到的，选择性沉积工艺包括但不限于无电镀覆和化学气相沉积。以上描述的用于金属栅电极102的相同金属和工艺在这里也可以用于沟槽接触部200。金属帽900中所使用的金属和所使用的选择性沉积工艺将取决于沟槽接触部200中所使用的金属。
根据本发明的实施方式，选择仅在沟槽接触部200上沉积金属并且不在金属栅电极102上沉积金属的选择性沉积工艺。这能够通过在沟槽接触部200和金属栅电极102中使用不同类型的金属来实现。例如，如果在金属栅电极102中使用铝并且在沟槽接触部200中使用贵金属，则选择性沉积工艺可以用于仅在沟槽接触部200中的贵金属上沉积金属帽900。在这里，上述贵金属的相同组合也同样行得通。在本发明的一些实施方式中，当在金属栅电极102中使用诸如铝、钨、钼、钛、钽、氮化钛或多晶硅等活性金属时，可以在沟槽接触部200中使用诸如钴、镍、铜、铂、钯、金和银等贵金属。
转向图10B，在ILD 110a和金属帽900之上均厚沉积ILD层902。然后，使用CMP工艺来使ILD层902和金属帽900两者平坦化，并且使它们的顶表面大体上相平。在ILD沉积之后完成以上工艺，以暴露金属帽900的顶表面。
接着，如图10C中所示，使用蚀刻工艺来从ILD层902内刚好去除金属帽900。所使用的蚀刻化学试剂必须对ILD层902和沟槽接触部200两者都是选择性的。这允许在对ILD层902和沟槽接触部200产生的影响最小的情况下，去除金属帽900。金属帽900的去除在ILD层902内产生空隙904。
转向图10D，可以在ILD层902之上和空隙904内均厚沉积绝缘层906。绝缘层906可以由包括但不限于以下材料的材料形成：氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅、其它氮化物材料、其它碳化物材料、氧化铝、其它氧化物材料、其它金属氧化物和低k电介质材料（包括与ILD层902中所使用的材料相同或相似的材料）。
接着，应用诸如各向异性蚀刻工艺等蚀刻工艺，以向下蚀刻绝缘层906并形成间隔体1000。这在图10E中示出。蚀刻工艺也在两个间隔体1000之间产生沟槽1002。
转向图10F，金属沉积工艺用于在间隔体1000之间和沟槽接触部200的顶上的沟槽1002中沉积自对准的金属螺栓1004。在一些实施方式中，该金属沉积工艺可以是另一选择性沉积工艺，而在其它实施方式中，该金属沉积工艺无需是选择性工艺。最后，如图10G中所示，可以沉积绝缘层并对其进行平坦化，以形成ILD层1006。也将金属螺栓1004的顶部平坦化，使其与ILD层1006相平。根据本发明的实施方式，防止自对准的金属螺栓1004通过间隔体1000而与栅极短路。
因此，这里描述的本发明的实施方式形成了与栅极自对准的蚀刻停止结构，从而防止接触部蚀刻使栅电极暴露从而引起栅极与接触部之间的短路。甚至在接触部图案覆盖栅电极的情况下，也防止了接触部到栅极短路。本发明的实施方式也解决了诸如在沟槽接触部与栅电极之间的寄生电容、从接触部到栅极的电介质层击穿或直接短路、以及在栅极接触部构图期间的对接触部硅化物的侵蚀。
因此，绝缘帽层的使用使接触部能够自对准，这提供了鲁棒的可制造工艺。本发明允许对较宽的接触部进行初始构图，其中较宽的接触部对构图限制更加鲁棒。对硅化物-穿透-接触部工艺流程而言，也期望较宽的接触部。这不仅消除了接触部到栅极短路这一主要成品率限制因素，而且也缓和了对接触部构图的主要限制，并且允许更大的可变性。从光刻的观点来看，绝缘帽层的使用增大了定位窗口并且允许更大的临界尺寸可变性。从蚀刻观点来看，绝缘帽层的使用使MOS晶体管的制造工艺对不同剖面、不同临界尺寸和沟槽接触部形成期间的ILD的过度蚀刻有更大的耐受性。
包括摘要中所描述的内容的、本发明的说明性的实施方式的以上描述不意在穷举或将本发明限制于所公开的精确形式。本领域技术人员将会认识到，这里描述的本发明的特定实施方式和示例是出于说明性的目的，可以在本发明的范围内进行各种等同修改。
根据以上的详细描述，可以对本发明作出这些修改。不应当将以下权利要求中所使用的术语理解为将本发明限制于本说明书和权利要求中所公开的具体实施方式。相反，本发明的范围完全由以下权利要求确定，并且根据已建立的权利要求解释原则来解释以下权利要求。

Claims (52)

1.一种晶体管，包括：
衬底；
在所述衬底上的间隔体对；
在所述衬底上且在所述间隔体对之间的栅极电介质层；
在所述栅极电介质层上且在所述间隔体对之间的栅电极层；
在所述栅电极层上并且在所述间隔体对之间的绝缘帽层；以及
邻近所述间隔体对的扩散区对。
2.根据权利要求1所述的晶体管，其中所述栅极电介质层、所述栅电极层和所述绝缘帽层的组合的高度不超过所述间隔体对的高度。
3.根据权利要求1所述的晶体管，其中沿所述衬底的表面并且沿所述间隔体对的侧壁形成所述栅极电介质层。
4.根据权利要求1所述的晶体管，其中所述绝缘帽层包括氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅或氧化铝。
5.根据权利要求1所述的晶体管，其中所述绝缘帽层包括氮化物材料、碳化物材料、氧化物材料、金属氧化物材料或低k电介质材料。
6.根据权利要求1所述的晶体管，其中所述绝缘帽层包括氮化硼或碳化硼。
7.根据权利要求1所述的晶体管，其中所述绝缘帽层包括掺杂有碳、氮和氢中的一种或多种的低k电介质材料。
8.一种形成晶体管的方法，包括：
在衬底上形成栅极电介质层；
在所述栅极电介质层上形成栅电极层；
在所述栅极电介质层和所述栅电极层的相对侧上形成间隔体对；
邻近所述间隔体对形成扩散区对；
使所述栅电极层凹进；以及
在所述间隔体对内的凹进的栅电极层上形成绝缘帽层。
9.根据权利要求8所述的方法，其中所述绝缘帽层的形成包括：
在所述凹进的栅电极层之上沉积绝缘材料的均厚层；以及
使所述绝缘材料层平坦化，以形成所述绝缘帽层。
10.根据权利要求8所述的方法，还包括：
在形成所述扩散区之后，去除所述栅电极层和所述栅极电介质层，由此在所述间隔体对之间形成沟槽；
沿所述间隔体之间的所述沟槽的侧壁和底表面沉积共形的低k栅极电介质层；以及
在使所述金属栅电极凹进之前在所述低k栅极电介质层上沉积金属栅电极层。
11.根据权利要求8所述的方法，其中所述绝缘帽层包括氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅或氧化铝。
12.根据权利要求8所述的方法，其中所述绝缘帽层包括氮化物材料、碳化物材料、氧化物材料、金属氧化物材料或低k电介质材料。
13.根据权利要求8所述的方法，其中所述绝缘帽层包括氮化硼或碳化硼。
14.根据权利要求8所述的方法，其中所述绝缘帽层包括掺杂有碳、氮和氢中的一种或多种的低k电介质材料。
15.一种形成晶体管的方法，包括：
在衬底上形成栅极叠置体，所述栅极叠置体包括栅极电介质层、在所述栅极电介质层上的栅电极层和在所述栅电极层上的绝缘帽层；
在所述栅极叠置体的相对侧上形成间隔体对；以及
邻近所述间隔体对形成扩散区对。
16.根据权利要求15所述的方法，其中所述绝缘帽层包括氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅或氧化铝。
17.根据权利要求15所述的方法，其中所述绝缘帽层包括氮化物材料、碳化物材料、氧化物材料、金属氧化物材料或低k电介质材料。
18.根据权利要求15所述的方法，其中所述绝缘帽层包括氮化硼或碳化硼。
19.根据权利要求15所述的方法，其中所述绝缘帽层包括掺杂有碳、氮和氢中的一种或多种的低k电介质材料。
20.一种晶体管，包括：
衬底；
在所述衬底上的间隔体对；
在所述衬底上且在所述间隔体对之间的栅极电介质层；
在所述栅极电介质层上且在所述间隔体对之间的栅电极层；
位于所述栅电极层的顶上的绝缘帽层，所述绝缘帽层在所述间隔体对的顶表面之上横向延伸；以及
邻近所述间隔体对的扩散区对。
21.根据权利要求20所述的晶体管，其中沿所述衬底的表面并且沿所述间隔体对的侧壁形成所述栅极电介质层。
22.根据权利要求20所述的晶体管，其中所述绝缘帽层包括氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅或氧化铝。
23.根据权利要求20所述的晶体管，其中所述绝缘帽层包括氮化物材料、碳化物材料、氧化物材料、金属氧化物材料或低k电介质材料。
24.根据权利要求20所述的晶体管，其中所述绝缘帽层包括氮化硼或碳化硼。
25.根据权利要求20所述的晶体管，其中所述绝缘帽层包括掺杂有碳、氮和氢中的一种或多种的低k电介质材料。
26.根据权利要求20所述的晶体管，其中所述间隔体对包括氮氧化硅、掺杂碳的氮氧化硅或低k电介质材料。
27.一种形成晶体管的方法，包括：
在衬底上形成栅极电介质层；
在所述栅极电介质层上形成栅电极层；
在所述栅极电介质层和所述栅电极层的相对侧上形成间隔体对；
邻近所述间隔体对形成扩散区对；
使所述栅电极层凹进；
使所述间隔体对凹进；以及
在凹进的栅电极层上形成绝缘帽层，所述绝缘帽层在凹进的间隔体对的顶表面之上横向延伸。
28.根据权利要求27所述的方法，还包括：
在使所述间隔体凹进之后，去除所述凹进的栅电极层和所述栅极电介质层，由此在所述凹进的间隔体对之间形成沟槽；
沿所述凹进的间隔体对之间的所述沟槽的侧壁和底表面沉积共形的低k栅极电介质层；
在所述低k栅极电介质层上沉积金属栅电极层；以及
使所述金属栅电极凹进，使得凹进的金属栅电极的高度与形成所述绝缘帽层之前的所述凹进的间隔体对的高度相似。
29.根据权利要求27所述的方法，其中所述绝缘帽层的形成包括：
在所述凹进的栅电极层和所述凹进的间隔体对之上沉积绝缘材料的均厚层；以及
使所述绝缘材料层平坦化，以形成所述绝缘帽层。
30.根据权利要求27所述的方法，其中所述凹进的间隔体对的高度与所述凹进的栅电极的高度大体上相同。
31.根据权利要求27所述的方法，其中所述间隔体对包括氮氧化硅（SiON）、掺杂碳的氮氧化硅（SiOCN）或低k电介质材料。
32.一种晶体管，包括：
衬底；
在所述衬底上的间隔体对；
在所述衬底上且在所述间隔体对之间的栅极电介质层；
在所述栅极电介质层上、具有阶梯式剖面的栅电极层，其中所述栅电极层的中间部分的高度相对大于所述栅电极层的侧面部分的高度；
在所述栅电极层上且在所述间隔体对之间的绝缘帽层；以及
邻近所述间隔体对的扩散区对。
33.根据权利要求32所述的晶体管，其中所述绝缘帽层包括氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅或氧化铝。
34.根据权利要求32所述的晶体管，其中所述绝缘帽层包括氮化物材料、碳化物材料、氧化物材料、金属氧化物材料或低k电介质材料。
35.根据权利要求32所述的晶体管，其中所述绝缘帽层包括氮化硼或碳化硼。
36.根据权利要求32所述的晶体管，其中所述绝缘帽层包括掺杂有碳、氮和氢中的一种或多种的低k电介质材料。
37.根据权利要求32所述的晶体管，其中所述栅电极包括两层金属层，其中第一金属层包括所述栅电极的具有相对较大的高度的所述中间部分，而第二金属层包括所述栅电极的所述侧面部分。
38.一种形成晶体管的方法，包括：
在衬底上形成栅极电介质层；
在所述栅极电介质层上形成栅电极层；
在所述栅极电介质层和所述栅电极层的相对侧上形成间隔体对；
邻近所述间隔体对形成扩散区对；
去除所述栅电极层和所述栅极电介质层，由此在所述间隔体对之间形成沟槽；
在所述沟槽内沉积共形的第一金属层；
在所述第一金属层上沉积第二金属层；
使所述第一金属层和所述第二金属层凹进，其中所述第一金属层凹进的程度比所述第二金属层凹进的程度大；以及
在凹进的第一金属层和凹进的第二金属层上形成绝缘帽层。
39.根据权利要求38所述的方法，其中所述第一金属层和所述第二金属层的凹进包括：
将蚀刻化学试剂施加到所述第一金属层和所述第二金属层，所述蚀刻化学试剂对所述第二金属层是选择性的。
40.根据权利要求38所述的方法，其中所述第一金属层和所述第二金属层的凹进包括：
施加第一蚀刻化学试剂，以使所述第一金属层凹进；以及
施加第二蚀刻化学试剂，以使所述第二金属层凹进，
其中所述第一蚀刻化学试剂和所述第二蚀刻化学试剂使所述第一金属层凹进的程度比使所述第二金属层凹进的程度大。
41.根据权利要求40所述的方法，其中所述第二蚀刻化学试剂还使所述第一金属层凹进。
42.根据权利要求38所述的方法，其中所述绝缘帽层的形成包括：
在所述凹进的第一金属层和所述凹进的第二金属层之上沉积绝缘材料的均厚层；以及
使所述绝缘材料层平坦化，以形成所述绝缘帽层。
43.根据权利要求38所述的方法，其中所述绝缘帽层包括氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅或氧化铝。
44.根据权利要求38所述的方法，其中所述绝缘帽层包括氮化物材料、碳化物材料、氧化物材料、金属氧化物材料或低k电介质材料。
45.根据权利要求38所述的方法，其中所述绝缘帽层包括氮化硼或碳化硼。
46.根据权利要求38所述的方法，其中所述绝缘帽层包括掺杂有碳、氮和氢中的一种或多种的低k电介质材料。
47.一种晶体管，包括：
衬底；
在所述衬底上的间隔体对；
在所述衬底上并且在所述间隔体对之间的栅极电介质层；
在所述栅极电介质层上、具有阶梯式剖面的栅电极层，其中所述栅电极层的中间部分的高度相对大于所述栅电极层的侧面部分的高度；
位于所述栅电极层的顶上的绝缘帽层，所述绝缘帽层在所述间隔体对的顶表面之上横向延伸；以及
邻近所述间隔体对的扩散区对。
48.根据权利要求47所述的晶体管，其中所述绝缘帽层包括氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅、氮氧化硅或氧化铝。
49.根据权利要求47所述的晶体管，其中所述绝缘帽层包括氮化物材料、碳化物材料、氧化物材料、金属氧化物材料或低k电介质材料。
50.根据权利要求47所述的晶体管，其中所述绝缘帽层包括氮化硼或碳化硼。
51.根据权利要求47所述的晶体管，其中所述绝缘帽层包括掺杂有碳、氮和氢中的一种或多种的低k电介质材料。
52.根据权利要求47所述的晶体管，其中所述栅电极包括两层金属层，其中第一金属层包括所述栅电极的具有相对较大的高度的所述中间部分，而第二金属层包括所述栅电极的所述侧面部分。
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Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594349A (zh) * 2012-08-17 2014-02-19 格罗方德半导体公司 形成具有栅极电极的替换栅极结构的方法
CN103811551A (zh) * 2012-11-05 2014-05-21 意法半导体公司 包括用于栅极电极的低k电介质帽层的半导体器件及相关方法
CN103871857A (zh) * 2012-12-18 2014-06-18 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN104051343A (zh) * 2013-03-14 2014-09-17 德克萨斯仪器股份有限公司 具有通过栅植入的深n阱的晶体管
CN104124173A (zh) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN104143515A (zh) * 2013-05-09 2014-11-12 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN104576370A (zh) * 2013-10-18 2015-04-29 国际商业机器公司 形成晶体管的方法
CN104681488A (zh) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN104716182A (zh) * 2013-12-12 2015-06-17 德州仪器公司 自对准作用沟槽触点
CN104835838A (zh) * 2014-02-12 2015-08-12 台湾积体电路制造股份有限公司 具有不同宽度的栅极结构及其制造方法
CN105990405A (zh) * 2015-03-16 2016-10-05 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN106206270A (zh) * 2015-03-26 2016-12-07 联华电子股份有限公司 半导体器件及其制作方法
CN106558501A (zh) * 2015-09-30 2017-04-05 台湾积体电路制造股份有限公司 元件的金属栅极方案及形成所述金属栅极方案的方法
CN106920750A (zh) * 2015-12-28 2017-07-04 中芯国际集成电路制造(上海)有限公司 金属栅晶体管源漏区接触塞的制作方法
CN106920771A (zh) * 2015-12-28 2017-07-04 中芯国际集成电路制造(北京)有限公司 金属栅晶体管源漏区接触塞的制作方法
CN107026127A (zh) * 2015-12-09 2017-08-08 格罗方德半导体公司 Fdsoi技术的外延分面高度一致性改进
CN107170824A (zh) * 2016-03-07 2017-09-15 台湾积体电路制造股份有限公司 半导体装置
CN107452797A (zh) * 2016-04-28 2017-12-08 三星电子株式会社 半导体器件
CN107591366A (zh) * 2016-07-06 2018-01-16 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
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CN109411405A (zh) * 2017-08-17 2019-03-01 联华电子股份有限公司 半导体结构及其制作方法
CN110246895A (zh) * 2018-03-09 2019-09-17 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN110892523A (zh) * 2017-07-20 2020-03-17 国际商业机器公司 形成自对准触点
CN112309861A (zh) * 2019-07-30 2021-02-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、晶体管
CN113327980A (zh) * 2020-02-28 2021-08-31 中芯国际集成电路制造（天津）有限公司 半导体结构及其形成方法

Families Citing this family (220)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8436404B2 (en) 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US8946828B2 (en) 2010-02-09 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having elevated structure and method of manufacturing the same
KR101675373B1 (ko) * 2010-03-24 2016-11-11 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR101615654B1 (ko) * 2010-05-14 2016-05-12 삼성전자주식회사 반도체 소자의 형성방법
US8860107B2 (en) * 2010-06-03 2014-10-14 International Business Machines Corporation FinFET-compatible metal-insulator-metal capacitor
US8421077B2 (en) * 2010-06-08 2013-04-16 International Business Machines Corporation Replacement gate MOSFET with self-aligned diffusion contact
JP5569243B2 (ja) * 2010-08-09 2014-08-13 ソニー株式会社 半導体装置及びその製造方法
KR101692309B1 (ko) * 2010-08-25 2017-01-04 삼성전자 주식회사 반도체 장치의 제조방법
US8592266B2 (en) * 2010-10-27 2013-11-26 International Business Machines Corporation Replacement gate MOSFET with a high performance gate electrode
US8946006B2 (en) * 2010-10-28 2015-02-03 International Business Machines Corporation Replacement gate MOSFET with raised source and drain
US8232607B2 (en) * 2010-11-23 2012-07-31 International Business Machines Corporation Borderless contact for replacement gate employing selective deposition
US8536656B2 (en) * 2011-01-10 2013-09-17 International Business Machines Corporation Self-aligned contacts for high k/metal gate process flow
DE102011004323B4 (de) * 2011-02-17 2016-02-25 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement mit selbstjustierten Kontaktelementen und Verfahren zu seiner Herstellung
CN102779754B (zh) * 2011-05-12 2015-04-08 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
US8872286B2 (en) * 2011-08-22 2014-10-28 United Microelectronics Corp. Metal gate structure and fabrication method thereof
US9190261B2 (en) 2011-08-25 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Layer alignment in FinFET fabrication
US8822283B2 (en) * 2011-09-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned insulated film for high-k metal gate device
US8877645B2 (en) * 2011-09-15 2014-11-04 International Business Machines Corporation Integrated circuit structure having selectively formed metal cap
KR20140049075A (ko) 2011-09-30 2014-04-24 인텔 코오퍼레이션 트랜지스터 게이트용 캡핑 유전체 구조
US9580776B2 (en) 2011-09-30 2017-02-28 Intel Corporation Tungsten gates for non-planar transistors
KR101780916B1 (ko) * 2011-09-30 2017-09-21 인텔 코포레이션 집적회로 구조 및 집적회로 구조의 제조 방법
US8981435B2 (en) * 2011-10-01 2015-03-17 Intel Corporation Source/drain contacts for non-planar transistors
US8614123B2 (en) * 2011-11-28 2013-12-24 Globalfoundries Inc. Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures
US9087915B2 (en) 2011-12-06 2015-07-21 Intel Corporation Interlayer dielectric for non-planar transistors
KR20180104195A (ko) 2011-12-22 2018-09-19 인텔 코포레이션 반도체 구조
US20130175619A1 (en) * 2012-01-06 2013-07-11 International Business Machines Corporation Silicon-on-insulator transistor with self-aligned borderless source/drain contacts
US8772168B2 (en) * 2012-01-19 2014-07-08 Globalfoundries Singapore Pte. Ltd. Formation of the dielectric cap layer for a replacement gate structure
US8927407B2 (en) 2012-01-20 2015-01-06 Globalfoundries Inc. Method of forming self-aligned contacts for a semiconductor device
US20130187236A1 (en) * 2012-01-20 2013-07-25 Globalfoundries Inc. Methods of Forming Replacement Gate Structures for Semiconductor Devices
US8580628B2 (en) * 2012-02-02 2013-11-12 GlobalFoundries, Inc. Integrated circuit contact structure and method
KR101853316B1 (ko) * 2012-03-29 2018-04-30 삼성전자주식회사 반도체 소자
US8946049B2 (en) 2012-04-11 2015-02-03 International Business Machines Corporation Replacement gate structures and methods of manufacturing
JP6100589B2 (ja) * 2012-04-13 2017-03-22 ルネサスエレクトロニクス株式会社 自己整合型ソース・ドレインコンタクトを有する半導体装置およびその製造方法
US8759172B2 (en) * 2012-04-18 2014-06-24 International Business Machines Corporation Etch stop layer formation in metal gate process
US20130309856A1 (en) * 2012-05-15 2013-11-21 International Business Machines Corporation Etch resistant barrier for replacement gate integration
US8779515B2 (en) 2012-05-21 2014-07-15 International Business Machines Corporation Semiconductor structure containing an aluminum-containing replacement gate electrode
US9130023B2 (en) * 2012-06-05 2015-09-08 Kabushiki Kaisha Toshiba Isolated insulating gate structure
US8679909B2 (en) 2012-06-08 2014-03-25 Globalfoundries Singapore Pte. Ltd. Recessing and capping of gate structures with varying metal compositions
US8883583B2 (en) * 2012-06-26 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, transistors, and methods of manufacture thereof
US8937006B2 (en) 2012-07-30 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US8877621B2 (en) * 2012-09-05 2014-11-04 Globalfoundries Inc. Low resistivity gate conductor
US8896030B2 (en) 2012-09-07 2014-11-25 Intel Corporation Integrated circuits with selective gate electrode recess
US8753970B2 (en) * 2012-09-12 2014-06-17 Globalfoundries Inc. Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
US9034703B2 (en) * 2012-09-13 2015-05-19 International Business Machines Corporation Self aligned contact with improved robustness
US9461143B2 (en) * 2012-09-19 2016-10-04 Intel Corporation Gate contact structure over active gate and method to fabricate same
US9299802B2 (en) 2012-10-28 2016-03-29 International Business Machines Corporation Method to improve reliability of high-K metal gate stacks
US8765590B2 (en) 2012-10-31 2014-07-01 International Business Machines Corporation Insulative cap for borderless self-aligning contact in semiconductor device
US8928090B2 (en) * 2012-10-31 2015-01-06 International Business Machines Corporation Self-aligned contact structure for replacement metal gate
US8890262B2 (en) 2012-11-29 2014-11-18 Globalfoundries Inc. Semiconductor device having a metal gate recess
US8778789B2 (en) * 2012-11-30 2014-07-15 GlobalFoundries, Inc. Methods for fabricating integrated circuits having low resistance metal gate structures
US8785283B2 (en) * 2012-12-05 2014-07-22 United Microelectronics Corp. Method for forming semiconductor structure having metal connection
US8728927B1 (en) * 2012-12-10 2014-05-20 International Business Machines Corporation Borderless contacts for semiconductor transistors
US8928048B2 (en) * 2013-01-17 2015-01-06 Globalfoundries Inc. Methods of forming semiconductor device with self-aligned contact elements and the resulting device
US8940633B2 (en) * 2013-03-05 2015-01-27 Globalfoundries Inc. Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
US8946075B2 (en) * 2013-03-05 2015-02-03 Globalfoundries Inc. Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
US8884344B2 (en) 2013-03-08 2014-11-11 International Business Machines Corporation Self-aligned contacts for replacement metal gate transistors
US9263275B2 (en) * 2013-03-12 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Interface for metal gate integration
US9006072B2 (en) * 2013-03-14 2015-04-14 United Microelectronics Corp. Method of forming metal silicide layer
TWI581316B (zh) * 2013-03-15 2017-05-01 聯華電子股份有限公司 形成金屬矽化物層的方法
US20140264640A1 (en) * 2013-03-18 2014-09-18 Nanya Technology Corp. Semiconductor device and method for fabricating the same
US20140342553A1 (en) * 2013-05-14 2014-11-20 United Microelectronics Corp. Method for Forming Semiconductor Structure Having Opening
KR102050779B1 (ko) * 2013-06-13 2019-12-02 삼성전자 주식회사 반도체 소자 및 이의 제조 방법
KR20150000546A (ko) * 2013-06-24 2015-01-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US20150024584A1 (en) * 2013-07-17 2015-01-22 Global Foundries, Inc. Methods for forming integrated circuits with reduced replacement metal gate height variability
US9153498B2 (en) * 2013-07-22 2015-10-06 Globalfoundries Inc. Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
US9257348B2 (en) 2013-08-06 2016-02-09 Globalfoundries Inc. Methods of forming replacement gate structures for transistors and the resulting devices
US9324709B2 (en) * 2013-08-19 2016-04-26 Globalfoundries Inc. Self-aligned gate contact structure
US9105497B2 (en) * 2013-09-04 2015-08-11 Globalfoundries Inc. Methods of forming gate structures for transistor devices for CMOS applications
JP6120738B2 (ja) * 2013-09-17 2017-04-26 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US9564332B2 (en) 2013-09-26 2017-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanism for forming metal gate structure
FR3011382B1 (fr) 2013-09-27 2019-03-29 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'un circuit integre
US9018711B1 (en) * 2013-10-17 2015-04-28 Globalfoundries Inc. Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
US9059164B2 (en) 2013-10-22 2015-06-16 International Business Machines Corporation Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors
US20150118836A1 (en) * 2013-10-28 2015-04-30 United Microelectronics Corp. Method of fabricating semiconductor device
US9153483B2 (en) * 2013-10-30 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US10158000B2 (en) * 2013-11-26 2018-12-18 Taiwan Semiconductor Manufacturing Company Limited Low-K dielectric sidewall spacer treatment
US9331072B2 (en) * 2014-01-28 2016-05-03 Samsung Electronics Co., Ltd. Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing the same
US9660035B2 (en) * 2014-01-29 2017-05-23 International Business Machines Corporation Semiconductor device including superlattice SiGe/Si fin structure
US9093467B1 (en) 2014-02-04 2015-07-28 Globalfoundries Inc. Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
KR20150091895A (ko) * 2014-02-04 2015-08-12 에스케이하이닉스 주식회사 반도체 장치 및 그 동작방법
US9252243B2 (en) 2014-02-07 2016-02-02 International Business Machines Corporation Gate structure integration scheme for fin field effect transistors
US20150228546A1 (en) * 2014-02-11 2015-08-13 United Microelectronics Corp. Semiconductor device and method of removing spacers on semiconductor device
US9236437B2 (en) 2014-02-20 2016-01-12 Globalfoundries Inc. Method for creating self-aligned transistor contacts
US9293557B2 (en) * 2014-02-20 2016-03-22 International Business Machines Corporation Low temperature spacer for advanced semiconductor devices
US9231063B2 (en) 2014-02-24 2016-01-05 International Business Machines Corporation Boron rich nitride cap for total ionizing dose mitigation in SOI devices
US9159822B2 (en) 2014-02-24 2015-10-13 International Business Machines Corporation III-V semiconductor device having self-aligned contacts
US9231067B2 (en) 2014-02-26 2016-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabricating method thereof
US9293576B2 (en) 2014-03-05 2016-03-22 International Business Machines Corporation Semiconductor device with low-k gate cap and self-aligned contact
US9257529B2 (en) 2014-03-11 2016-02-09 Tokyo Electron Limited Method of forming self-aligned contacts using a replacement metal gate process in a semiconductor device
US9324830B2 (en) 2014-03-27 2016-04-26 International Business Machines Corporation Self-aligned contact process enabled by low temperature
US9711646B2 (en) 2014-03-31 2017-07-18 United Microelectronics Corp. Semiconductor structure and manufacturing method for the same
US9484205B2 (en) * 2014-04-07 2016-11-01 International Business Machines Corporation Semiconductor device having self-aligned gate contacts
US9236258B2 (en) * 2014-04-23 2016-01-12 Globalfoundries Inc. Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
US9147748B1 (en) 2014-05-01 2015-09-29 Globalfoundries Inc. Methods of forming replacement spacer structures on semiconductor devices
US9608086B2 (en) * 2014-05-20 2017-03-28 Global Foundries Inc. Metal gate structure and method of formation
US9385235B2 (en) 2014-05-30 2016-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9570319B2 (en) * 2014-05-30 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device
TWI612563B (zh) 2014-07-07 2018-01-21 聯華電子股份有限公司 金屬閘極結構與其製作方法
CN105280486B (zh) 2014-07-23 2020-09-22 联华电子股份有限公司 金属栅极结构的制作方法
KR102276642B1 (ko) 2014-07-28 2021-07-15 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10176996B2 (en) * 2014-08-06 2019-01-08 Globalfoundries Inc. Replacement metal gate and fabrication process with reduced lithography steps
KR102251363B1 (ko) * 2014-08-08 2021-05-14 삼성전자주식회사 반도체 소자
US9812577B2 (en) 2014-09-05 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US10134861B2 (en) * 2014-10-08 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US20160126336A1 (en) * 2014-10-29 2016-05-05 Globalfoundries Inc. Method of improved ca/cb contact and device thereof
US9876114B2 (en) 2014-12-30 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D FinFET metal gate
US9391204B1 (en) * 2015-03-12 2016-07-12 International Business Machines Corporation Asymmetric FET
US9698232B2 (en) 2015-03-18 2017-07-04 Qualcomm Incorporated Conductive cap for metal-gate transistor
US9685532B2 (en) 2015-03-24 2017-06-20 International Business Machines Corporation Replacement metal gate structures
US9799560B2 (en) * 2015-03-31 2017-10-24 Qualcomm Incorporated Self-aligned structure
TWI650833B (zh) 2015-04-01 2019-02-11 聯華電子股份有限公司 具有金屬閘極之半導體元件及其製作方法
US9443853B1 (en) 2015-04-07 2016-09-13 International Business Machines Corporation Minimizing shorting between FinFET epitaxial regions
KR102290538B1 (ko) 2015-04-16 2021-08-19 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR102342847B1 (ko) 2015-04-17 2021-12-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9431235B1 (en) * 2015-04-24 2016-08-30 International Business Machines Corporation Multilayer dielectric structures with graded composition for nano-scale semiconductor devices
US9941376B2 (en) 2015-04-30 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate scheme for device and methods of forming
US20160322473A1 (en) * 2015-04-30 2016-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer Layer on Gate and Methods of Forming the Same
US9647091B2 (en) 2015-05-01 2017-05-09 International Business Machines Corporation Annealed metal source drain overlapping the gate
US10199230B2 (en) * 2015-05-01 2019-02-05 Applied Materials, Inc. Methods for selective deposition of metal silicides via atomic layer deposition cycles
US9876074B2 (en) * 2015-05-22 2018-01-23 International Business Machines Corporation Structure and process to tuck fin tips self-aligned to gates
US10411113B2 (en) * 2015-05-22 2019-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US10062763B2 (en) 2015-05-27 2018-08-28 Qualcomm Incorporated Method and apparatus for selectively forming nitride caps on metal gate
US9722043B2 (en) 2015-06-15 2017-08-01 International Business Machines Corporation Self-aligned trench silicide process for preventing gate contact to silicide shorts
KR102396111B1 (ko) 2015-06-18 2022-05-10 삼성전자주식회사 반도체 소자 및 그 제조 방법
US10090396B2 (en) * 2015-07-20 2018-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating metal gate devices and resulting structures
KR102321373B1 (ko) 2015-08-19 2021-11-02 삼성전자주식회사 반도체 장치의 제조 방법
US9831090B2 (en) * 2015-08-19 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for semiconductor device having gate spacer protection layer
CN106531776B (zh) * 2015-09-11 2021-06-29 联华电子股份有限公司 半导体结构
US9768272B2 (en) 2015-09-30 2017-09-19 International Business Machines Corporation Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity
US9673101B2 (en) 2015-09-30 2017-06-06 International Business Machines Corporation Minimize middle-of-line contact line shorts
US9627484B1 (en) 2015-10-12 2017-04-18 International Business Machines Corporation Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer
CN106684041B (zh) * 2015-11-10 2020-12-08 联华电子股份有限公司 半导体元件及其制作方法
US9570450B1 (en) 2015-11-19 2017-02-14 International Business Machines Corporation Hybrid logic and SRAM contacts
US9660050B1 (en) 2015-11-25 2017-05-23 International Business Machines Corporation Replacement low-k spacer
US20170162444A1 (en) * 2015-12-02 2017-06-08 International Business Machines Corporation Contact resistance reduction for advanced technology nodes
US9627510B1 (en) 2015-12-02 2017-04-18 International Business Machines Corporation Structure and method for replacement gate integration with self-aligned contacts
US9437714B1 (en) 2015-12-09 2016-09-06 International Business Machines Corporation Selective gate contact fill metallization
US10867852B2 (en) * 2015-12-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US9865703B2 (en) * 2015-12-31 2018-01-09 International Business Machines Corporation High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process
US9450095B1 (en) * 2016-02-04 2016-09-20 International Business Machines Corporation Single spacer for complementary metal oxide semiconductor process flow
US9824920B2 (en) * 2016-04-04 2017-11-21 Globalfoundries Inc. Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices
CN107275214A (zh) * 2016-04-08 2017-10-20 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10510599B2 (en) * 2016-04-13 2019-12-17 Taiwan Semiconductor Manufacturing Company Limited FinFET switch
US9793267B1 (en) 2016-04-22 2017-10-17 United Microelectronics Corp. Semiconductor device having gate structure with reduced threshold voltage and method for manufacturing the same
CN109564934B (zh) 2016-04-25 2023-02-21 应用材料公司 水平环绕式栅极元件纳米线气隙间隔的形成
US9991361B2 (en) * 2016-05-26 2018-06-05 Globalfoundries Inc. Methods for performing a gate cut last scheme for FinFET semiconductor devices
US9837351B1 (en) 2016-06-07 2017-12-05 International Business Machines Corporation Avoiding gate metal via shorting to source or drain contacts
US10164032B2 (en) 2016-06-17 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned contact and manufacturing method thereof
WO2018004680A1 (en) * 2016-07-01 2018-01-04 Intel Corporation Self-aligned gate edge trigate and finfet devices
US9847398B1 (en) * 2016-07-13 2017-12-19 United Microelectronics Corp. Semiconductor device with gate structure having dielectric layer on one side and contact plug on the other side
US9929046B2 (en) * 2016-07-21 2018-03-27 International Business Machines Corporation Self-aligned contact cap
US9929271B2 (en) 2016-08-03 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9704754B1 (en) * 2016-09-22 2017-07-11 International Business Machines Corporation Self-aligned spacer for cut-last transistor fabrication
KR20180034798A (ko) * 2016-09-28 2018-04-05 삼성전자주식회사 유전막 형성 방법 및 반도체 장치의 제조 방법
US9704991B1 (en) 2016-10-31 2017-07-11 International Business Machines Corporation Gate height and spacer uniformity
US10522359B2 (en) * 2016-11-29 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming
US10008416B2 (en) * 2016-11-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Forming a protective layer to prevent formation of leakage paths
US20180158821A1 (en) * 2016-12-06 2018-06-07 Globalfoundries Inc. Gate structures with low resistance
US10707316B2 (en) * 2016-12-09 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with gate structure
US10079290B2 (en) * 2016-12-30 2018-09-18 United Microelectronics Corp. Semiconductor device having asymmetric spacer structures
EP3567005A4 (en) * 2017-01-06 2020-07-29 Japan Science and Technology Agency HEXAGONAL BORON NITRIDE THIN FILM AND ITS MANUFACTURING METHOD
US10242918B2 (en) 2017-02-08 2019-03-26 International Business Machines Corporation Shallow trench isolation structures and contact patterning
US10103237B2 (en) * 2017-02-28 2018-10-16 International Business Machines Corporation Inverted MOSFET with scaling advantage
US10062784B1 (en) * 2017-04-20 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned gate hard mask and method forming same
US10186456B2 (en) * 2017-04-20 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming contact plugs with reduced corrosion
US10141225B2 (en) 2017-04-28 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity
TWI729128B (zh) 2017-05-10 2021-06-01 聯華電子股份有限公司 半導體結構及其製作方法
US10522392B2 (en) * 2017-05-31 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
TWI730119B (zh) 2017-06-09 2021-06-11 聯華電子股份有限公司 具有金屬閘極之半導體元件之製作方法
US10304735B2 (en) 2017-06-22 2019-05-28 Globalfoundries Inc. Mechanically stable cobalt contacts
US10181421B1 (en) * 2017-07-12 2019-01-15 Globalfoundries Inc. Liner recess for fully aligned via
US10014180B1 (en) 2017-08-21 2018-07-03 Globalfoundries Inc. Tungsten gate and method for forming
US10804148B2 (en) * 2017-08-25 2020-10-13 International Business Machines Corporation Buried contact to provide reduced VFET feature-to-feature tolerance requirements
US10763338B2 (en) * 2017-08-30 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Silicide implants
US10374058B2 (en) 2017-09-15 2019-08-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
US10504782B2 (en) * 2017-09-29 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Fin Field-Effect Transistor device and method of forming the same
US10651284B2 (en) 2017-10-24 2020-05-12 Globalfoundries Inc. Methods of forming gate contact structures and cross-coupled contact structures for transistor devices
US10236215B1 (en) * 2017-10-24 2019-03-19 Globalfoundries Inc. Methods of forming gate contact structures and cross-coupled contact structures for transistor devices
KR102291538B1 (ko) 2017-11-10 2021-08-18 삼성전자주식회사 반도체 장치
US10418453B2 (en) * 2017-11-22 2019-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Forming metal contacts on metal gates
CN111194482A (zh) 2017-11-30 2020-05-22 英特尔公司 用于高级集成电路结构制造的鳍状物图案化
US10403547B2 (en) * 2017-12-12 2019-09-03 Varian Semiconductor Equipment Associates, Inc. Structure and method of forming self aligned contacts in semiconductor device
US10468409B2 (en) * 2018-03-14 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with oxidation-resist STI liner structure
US11217456B2 (en) * 2018-03-26 2022-01-04 Intel Corporation Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication
US10249533B1 (en) 2018-04-12 2019-04-02 International Business Machines Corporation Method and structure for forming a replacement contact
US10665505B2 (en) 2018-05-22 2020-05-26 International Business Machines Corporation Self-aligned gate contact isolation
US10685872B2 (en) 2018-05-30 2020-06-16 International Business Machines Corporation Electrically isolated contacts in an active region of a semiconductor device
US10522644B1 (en) 2018-06-21 2019-12-31 Globalfoundries Inc. Different upper and lower spacers for contact
US11107902B2 (en) * 2018-06-25 2021-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric spacer to prevent contacting shorting
US10818557B2 (en) 2018-07-03 2020-10-27 Globalfoundries Inc. Integrated circuit structure to reduce soft-fail incidence and method of forming same
US10553486B1 (en) 2018-07-27 2020-02-04 Globalfoundries Inc. Field effect transistors with self-aligned metal plugs and methods
CN110875396B (zh) * 2018-08-31 2023-08-15 力智电子股份有限公司 沟槽式栅极金氧半场效晶体管及其制造方法
US11195753B2 (en) 2018-09-18 2021-12-07 International Business Machines Corporation Tiered-profile contact for semiconductor
US11195754B2 (en) 2018-10-09 2021-12-07 International Business Machines Corporation Transistor with reduced gate resistance and improved process margin of forming self-aligned contact
US10978571B2 (en) 2018-10-24 2021-04-13 International Business Machines Corporation Self-aligned contact with metal-insulator transition materials
US10892338B2 (en) * 2018-10-24 2021-01-12 Globalfoundries Inc. Scaled gate contact and source/drain cap
US10943990B2 (en) 2018-10-25 2021-03-09 International Business Machines Corporation Gate contact over active enabled by alternative spacer scheme and claw-shaped cap
US11062946B2 (en) * 2018-11-08 2021-07-13 International Business Machines Corporation Self-aligned contact on a semiconductor device
KR20200066959A (ko) * 2018-12-03 2020-06-11 엘지디스플레이 주식회사 투명표시장치
US11152307B2 (en) * 2018-12-18 2021-10-19 International Business Machines Corporation Buried local interconnect
US10770562B1 (en) 2019-03-01 2020-09-08 International Business Machines Corporation Interlayer dielectric replacement techniques with protection for source/drain contacts
US10892164B2 (en) 2019-04-16 2021-01-12 International Business Machines Corporation Dual hard mask replacement gate
US11139306B2 (en) * 2019-05-28 2021-10-05 Winbond Electronics Corp. Memory device and method for fabricating the same
US10818548B1 (en) * 2019-05-30 2020-10-27 International Business Machines Corporation Method and structure for cost effective enhanced self-aligned contacts
CN112103249B (zh) * 2019-06-18 2024-03-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10832964B1 (en) 2019-07-15 2020-11-10 International Business Machines Corporatior Replacement contact formation for gate contact over active region with selective metal growth
KR20210024384A (ko) * 2019-08-23 2021-03-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11328990B2 (en) * 2019-09-27 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Via structure having a metal hump for low interface resistance
US11522083B2 (en) 2019-10-18 2022-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same
US11264419B2 (en) * 2019-12-30 2022-03-01 Omnivision Technologies, Inc. Image sensor with fully depleted silicon on insulator substrate
US11302577B2 (en) 2020-01-17 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Self aligned contact scheme
KR20210104260A (ko) 2020-02-17 2021-08-25 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US11211462B2 (en) * 2020-03-05 2021-12-28 International Business Machines Corporation Using selectively formed cap layers to form self-aligned contacts to source/drain regions
DE102020126070A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Kontaktbildungsverfahren und entsprechende struktur
US11682707B2 (en) 2020-03-31 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Contact formation method and related structure
US11508572B2 (en) * 2020-04-01 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11257926B2 (en) * 2020-06-08 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned contact structures
US11264481B2 (en) 2020-07-01 2022-03-01 International Business Machines Corporation Self-aligned source and drain contacts
TW202236453A (zh) * 2021-03-10 2022-09-16 新加坡商發明與合作實驗室有限公司 內連線結構及其製造方法
US11935929B2 (en) * 2021-10-21 2024-03-19 International Business Machines Corporation High aspect ratio shared contacts

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310367B1 (en) * 1999-02-22 2001-10-30 Kabushiki Kaisha Toshiba MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US20020192911A1 (en) * 2000-08-29 2002-12-19 Parke Stephen A. Damascene double gated transistors and related manufacturing methods
US20030156380A1 (en) * 1993-04-02 2003-08-21 Micron Technology, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
US20070104862A1 (en) * 2005-11-09 2007-05-10 Su-Chen Lai Gate structure and fabricating method thereof
US20080001236A1 (en) * 2006-06-28 2008-01-03 Change Peter L D Method of forming a transistor having gate protection and transistor formed according to the method
US20080166841A1 (en) * 2007-01-10 2008-07-10 Chao-Ching Hsieh Method of fabricating a strained silicon channel metal oxide semiconductor transistor
US20090026552A1 (en) * 2007-07-27 2009-01-29 Da Zhang Method for forming a transistor having gate dielectric protection and structure
US20090289334A1 (en) * 2008-05-21 2009-11-26 Willy Rachmady Metal gate structure and method of manufacturing same

Family Cites Families (149)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210435A (en) * 1990-10-12 1993-05-11 Motorola, Inc. ITLDD transistor having a variable work function
JP3104193B2 (ja) * 1991-06-28 2000-10-30 ソニー株式会社 半導体装置の接続構造形成方法
US5381302A (en) * 1993-04-02 1995-01-10 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5385866A (en) * 1994-06-22 1995-01-31 International Business Machines Corporation Polish planarizing using oxidized boron nitride as a polish stop
JPH0936319A (ja) * 1995-07-18 1997-02-07 Toshiba Corp 半導体装置の製造方法
JP3703885B2 (ja) 1995-09-29 2005-10-05 株式会社東芝 半導体記憶装置とその製造方法
US5792703A (en) 1996-03-20 1998-08-11 International Business Machines Corporation Self-aligned contact wiring process for SI devices
JP4064496B2 (ja) * 1996-07-12 2008-03-19 株式会社東芝 半導体装置及びその製造方法
JP3520697B2 (ja) * 1996-11-07 2004-04-19 富士通株式会社 半導体装置及びその製造方法
JPH10144781A (ja) 1996-11-12 1998-05-29 Fujitsu Ltd 半導体装置の製造方法
JP3232043B2 (ja) * 1997-06-30 2001-11-26 株式会社東芝 半導体装置の製造方法
US6054355A (en) * 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JP2008153687A (ja) * 1997-06-30 2008-07-03 Toshiba Corp 半導体装置の製造方法
JP4160167B2 (ja) * 1997-06-30 2008-10-01 株式会社東芝 半導体装置の製造方法
US5807779A (en) * 1997-07-30 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process
KR100245271B1 (ko) * 1997-10-01 2000-02-15 윤종용 반도체 장치 및 그의 제조 방법
JPH11135745A (ja) * 1997-10-29 1999-05-21 Toshiba Corp 半導体装置及びその製造方法
US5907781A (en) 1998-03-27 1999-05-25 Advanced Micro Devices, Inc. Process for fabricating an integrated circuit with a self-aligned contact
JPH11307473A (ja) * 1998-04-24 1999-11-05 Sony Corp 半導体装置およびその製造方法
JP3025478B2 (ja) * 1998-07-13 2000-03-27 松下電器産業株式会社 半導体装置およびその製造方法
JP3380172B2 (ja) 1998-07-29 2003-02-24 松下電器産業株式会社 半導体装置の製造方法
US6383951B1 (en) * 1998-09-03 2002-05-07 Micron Technology, Inc. Low dielectric constant material for integrated circuit fabrication
US6184129B1 (en) * 1998-09-29 2001-02-06 Texas Instruments Incorporated Low resistivity poly-silicon gate produced by selective metal growth
US20020008257A1 (en) * 1998-09-30 2002-01-24 John P. Barnak Mosfet gate electrodes having performance tuned work functions and methods of making same
JP3439135B2 (ja) * 1998-10-05 2003-08-25 沖電気工業株式会社 半導体装置の製造方法及び半導体装置
US6207514B1 (en) * 1999-01-04 2001-03-27 International Business Machines Corporation Method for forming borderless gate structures and apparatus formed thereby
TW404009B (en) * 1999-01-27 2000-09-01 United Microelectronics Corp The method of manufacturing self-aligned contact (SAC)
JP2000223703A (ja) * 1999-01-29 2000-08-11 Toshiba Corp 半導体装置及びその製造方法
US6235593B1 (en) * 1999-02-18 2001-05-22 Taiwan Semiconductor Manufacturing Company Self aligned contact using spacers on the ILD layer sidewalls
US6274426B1 (en) * 1999-02-25 2001-08-14 Taiwan Semiconductor Manufacturing Company Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure
US6348709B1 (en) * 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
US6573132B1 (en) * 1999-03-25 2003-06-03 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor device having contacts self-aligned with a gate electrode thereof
KR100397153B1 (ko) 1999-07-27 2003-09-06 한국전기초자 주식회사 유리튜브절단용 버너
US6033963A (en) * 1999-08-30 2000-03-07 Taiwan Semiconductor Manufacturing Company Method of forming a metal gate for CMOS devices using a replacement gate process
US6265319B1 (en) 1999-09-01 2001-07-24 Taiwan Semiconductor Manufacturing Company Dual damascene method employing spin-on polymer (SOP) etch stop layer
US6294449B1 (en) * 1999-11-23 2001-09-25 International Business Machines Corporation Self-aligned contact for closely spaced transistors
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
TW506079B (en) * 2000-02-17 2002-10-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
KR100350056B1 (ko) 2000-03-09 2002-08-24 삼성전자 주식회사 다마신 게이트 공정에서 자기정렬콘택패드 형성 방법
JP2001284467A (ja) * 2000-03-30 2001-10-12 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6607950B2 (en) * 2000-03-30 2003-08-19 Interuniversitair Microelektronic Centrum (Imec) MIS transistors with a metal gate and high-k dielectric and method of forming
JP2001308323A (ja) * 2000-04-26 2001-11-02 Hitachi Ltd 半導体装置の製造方法
JP2001345443A (ja) * 2000-06-01 2001-12-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
FR2810157B1 (fr) * 2000-06-09 2002-08-16 Commissariat Energie Atomique Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene
KR100333372B1 (ko) 2000-06-21 2002-04-19 박종섭 금속 게이트 모스팻 소자의 제조방법
JP2002110966A (ja) * 2000-09-26 2002-04-12 Seiko Epson Corp 半導体装置の製造方法および半導体装置
US6306713B1 (en) * 2000-10-10 2001-10-23 Advanced Micro Devices, Inc. Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
JP2002141420A (ja) 2000-10-31 2002-05-17 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
JP2002170821A (ja) * 2000-11-30 2002-06-14 Sony Corp 膜の形成方法
KR100649821B1 (ko) * 2000-12-26 2006-11-24 주식회사 하이닉스반도체 반도체소자의 트랜지스터 제조방법
KR100363701B1 (ko) * 2000-12-29 2002-12-05 주식회사 하이닉스반도체 반도체 소자의 비트 라인 콘택 형성 방법
KR100365414B1 (en) 2001-04-30 2002-12-18 Hynix Semiconductor Inc Method for forming ultra-shallow junction using laser annealing process
JP2003007850A (ja) * 2001-06-18 2003-01-10 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR100394524B1 (ko) * 2001-12-21 2003-08-14 동부전자 주식회사 반도체소자의 제조방법
KR100434505B1 (ko) * 2002-06-19 2004-06-05 삼성전자주식회사 다마신 배선을 이용한 반도체 소자의 제조방법
JP2004071959A (ja) * 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置
US7902029B2 (en) * 2002-08-12 2011-03-08 Acorn Technologies, Inc. Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
US6624024B1 (en) * 2002-08-29 2003-09-23 Micron Technology, Inc. Method and apparatus for a flash memory device comprising a source local interconnect
US6909152B2 (en) * 2002-11-14 2005-06-21 Infineon Technologies, Ag High density DRAM with reduced peripheral device area and method of manufacture
KR20040060335A (ko) * 2002-12-30 2004-07-06 주식회사 하이닉스반도체 반도체소자의 자기정렬적인 콘택 형성방법
KR100503519B1 (ko) * 2003-01-22 2005-07-22 삼성전자주식회사 반도체 장치 및 그 제조방법
KR100505062B1 (ko) * 2003-02-22 2005-07-29 삼성전자주식회사 반도체 소자의 제조방법
US6891192B2 (en) 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
TWI304633B (en) * 2003-08-25 2008-12-21 Promos Technologies Inc Semiconductor device and fabricating method thereof
KR20050024667A (ko) * 2003-09-01 2005-03-11 삼성전자주식회사 반도체소자의 버팅컨택 형성방법
US6906360B2 (en) 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US20050085072A1 (en) * 2003-10-20 2005-04-21 Kim Hyun T. Formation of self-aligned contact plugs
US7056794B2 (en) 2004-01-09 2006-06-06 International Business Machines Corporation FET gate structure with metal gate electrode and silicide contact
TWI227917B (en) * 2004-01-29 2005-02-11 Nanya Technology Corp A word line structure with single-sided partially recessed gate and method for forming the same
US7285829B2 (en) * 2004-03-31 2007-10-23 Intel Corporation Semiconductor device having a laterally modulated gate workfunction and method of fabrication
US7253125B1 (en) * 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US7153784B2 (en) 2004-04-20 2006-12-26 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US6884715B1 (en) * 2004-06-04 2005-04-26 International Business Machines Corporation Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby
US7148548B2 (en) * 2004-07-20 2006-12-12 Intel Corporation Semiconductor device with a high-k gate dielectric and a metal gate electrode
US7074666B2 (en) * 2004-07-28 2006-07-11 International Business Machines Corporation Borderless contact structures
US6979622B1 (en) 2004-08-24 2005-12-27 Freescale Semiconductor, Inc. Semiconductor transistor having structural elements of differing materials and method of formation
US7026689B2 (en) * 2004-08-27 2006-04-11 Taiwan Semiconductor Manufacturing Company Metal gate structure for MOS devices
US7126199B2 (en) * 2004-09-27 2006-10-24 Intel Corporation Multilayer metal gate electrode
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
KR100611776B1 (ko) * 2004-10-06 2006-08-10 주식회사 하이닉스반도체 반도체 소자 제조 방법
US6949768B1 (en) * 2004-10-18 2005-09-27 International Business Machines Corporation Planar substrate devices integrated with finfets and method of manufacture
US7037774B1 (en) * 2004-10-21 2006-05-02 Integrated Device Technology, Inc. Self-aligned contact structure and process for forming self-aligned contact structure
US7230296B2 (en) * 2004-11-08 2007-06-12 International Business Machines Corporation Self-aligned low-k gate cap
US7138308B2 (en) * 2004-12-14 2006-11-21 International Business Machines Corporation Replacement gate with TERA cap
KR100719342B1 (ko) 2005-02-01 2007-05-17 삼성전자주식회사 듀얼 게이트 전극을 갖는 반도체 소자 및 그 형성 방법
KR100585178B1 (ko) * 2005-02-05 2006-05-30 삼성전자주식회사 금속 게이트 전극을 가지는 ＦｉｎＦＥＴ을 포함하는반도체 소자 및 그 제조방법
US7294890B2 (en) * 2005-03-03 2007-11-13 Agency For Science, Technology And Research Fully salicided (FUSA) MOSFET structure
JP2006253461A (ja) * 2005-03-11 2006-09-21 Toshiba Corp 半導体集積回路装置およびその製造方法
US7563701B2 (en) * 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
US7354854B2 (en) 2005-05-24 2008-04-08 Texas Instruments Incorporated Nickel silicide method and structure
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
KR100618908B1 (ko) * 2005-08-12 2006-09-05 삼성전자주식회사 게이트 저항을 개선한 반도체 소자 및 제조 방법
US20070063277A1 (en) * 2005-09-22 2007-03-22 International Business Machines Corporation Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current
JP2007103694A (ja) 2005-10-05 2007-04-19 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7183613B1 (en) 2005-11-15 2007-02-27 International Business Machines Corporation Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film
US20070141798A1 (en) * 2005-12-20 2007-06-21 Intel Corporation Silicide layers in contacts for high-k/metal gate transistors
JP2007220701A (ja) 2006-02-14 2007-08-30 Elpida Memory Inc 半導体装置の製造方法、半導体記憶装置の製造方法
US20070241411A1 (en) * 2006-04-12 2007-10-18 International Business Machines Corporation Structures and methods for forming sram cells with self-aligned contacts
US20070249156A1 (en) * 2006-04-20 2007-10-25 Griselda Bonilla Method for enabling hard mask free integration of ultra low-k materials and structures produced thereby
US8193641B2 (en) * 2006-05-09 2012-06-05 Intel Corporation Recessed workfunction metal in CMOS transistor gates
JP4920310B2 (ja) 2006-05-30 2012-04-18 株式会社東芝 半導体装置およびその製造方法
US7541239B2 (en) * 2006-06-30 2009-06-02 Intel Corporation Selective spacer formation on transistors of different classes on the same device
WO2008041301A1 (fr) * 2006-09-29 2008-04-10 Fujitsu Microelectronics Limited DISPOSITIF SEMI-CONDUCTEUR ET Son procÉDÉ de FABRICATION
KR100760926B1 (ko) * 2006-10-11 2007-09-21 동부일렉트로닉스 주식회사 다중 비트셀을 구현하는 비휘발성 반도체 메모리 장치 및그 제조방법
JP4501965B2 (ja) * 2006-10-16 2010-07-14 ソニー株式会社 半導体装置の製造方法
US8304342B2 (en) * 2006-10-31 2012-11-06 Texas Instruments Incorporated Sacrificial CMP etch stop layer
JP2008130797A (ja) 2006-11-21 2008-06-05 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2008130979A (ja) 2006-11-24 2008-06-05 Takenaka Komuten Co Ltd 電磁波シールド構造体
US8120114B2 (en) * 2006-12-27 2012-02-21 Intel Corporation Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate
US7682891B2 (en) 2006-12-28 2010-03-23 Intel Corporation Tunable gate electrode work function material for transistor applications
JP4367523B2 (ja) 2007-02-06 2009-11-18 ソニー株式会社 絶縁ゲート電界効果トランジスタ及びその製造方法
US20080190760A1 (en) * 2007-02-08 2008-08-14 Applied Materials, Inc. Resputtered copper seed layer
US8129235B2 (en) * 2007-03-15 2012-03-06 United Microelectronics Corp. Method of fabricating two-step self-aligned contact
US7566651B2 (en) * 2007-03-28 2009-07-28 International Business Machines Corporation Low contact resistance metal contact
US20080272410A1 (en) * 2007-05-02 2008-11-06 Chung-Te Lin Self-Aligned Spacer Contact
JP2008282901A (ja) * 2007-05-09 2008-11-20 Sony Corp 半導体装置および半導体装置の製造方法
US8450165B2 (en) * 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
KR101244456B1 (ko) * 2007-07-10 2013-03-18 삼성전자주식회사 콘택 스페이서를 구비하는 콘택 구조체의 형성 방법 및이를 이용한 반도체 소자의 제조 방법
DE102007041207B4 (de) * 2007-08-31 2015-05-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg CMOS-Bauelement mit Gateisolationsschichten mit unterschiedlicher Art und Dicke und Verfahren zur Herstellung
US7659171B2 (en) * 2007-09-05 2010-02-09 International Business Machines Corporation Methods and structure for forming self-aligned borderless contacts for strain engineered logic devices
KR20090025778A (ko) * 2007-09-07 2009-03-11 주식회사 하이닉스반도체 반도체 소자의 콘택홀 형성 방법
US20090085131A1 (en) * 2007-09-28 2009-04-02 Nec Electronics Corporation Semiconductor device and manufacturing method thereof
US7939889B2 (en) * 2007-10-16 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing resistance in source and drain regions of FinFETs
KR20090038972A (ko) * 2007-10-17 2009-04-22 삼성전자주식회사 콘택홀 형성방법 및 그를 이용한 반도체 메모리소자의제조방법
US20090108359A1 (en) * 2007-10-31 2009-04-30 Agere Systems Inc. A semiconductor device and method of manufacture therefor
US8354347B2 (en) * 2007-12-11 2013-01-15 Globalfoundries Singapore Pte. Ltd. Method of forming high-k dielectric stop layer for contact hole opening
JP2009158591A (ja) 2007-12-25 2009-07-16 Nec Electronics Corp 半導体装置およびその製造方法
KR101374323B1 (ko) * 2008-01-07 2014-03-17 삼성전자주식회사 반도체 소자 및 그 제조방법
JP2009231592A (ja) * 2008-03-24 2009-10-08 Nec Electronics Corp 半導体装置の製造方法
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US20090275182A1 (en) * 2008-05-01 2009-11-05 International Business Machines Corporation Method for fabricating a metal high dielectric constant transistor with reverse-t gate
US7838913B2 (en) * 2008-05-28 2010-11-23 International Business Machines Corporation Hybrid FET incorporating a finFET and a planar FET
KR101479997B1 (ko) * 2008-06-20 2015-01-07 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법
JP2010010218A (ja) 2008-06-24 2010-01-14 Fujitsu Microelectronics Ltd 半導体装置とその製造方法
US7902009B2 (en) * 2008-12-11 2011-03-08 Intel Corporation Graded high germanium compound films for strained semiconductor devices
US8227867B2 (en) * 2008-12-23 2012-07-24 International Business Machines Corporation Body contacted hybrid surface semiconductor-on-insulator devices
US8202776B2 (en) * 2009-04-22 2012-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for protecting a gate structure during contact formation
WO2011000020A1 (en) 2009-06-12 2011-01-06 Sbc Research Pty Ltd Enhanced method of detection
US8530971B2 (en) * 2009-11-12 2013-09-10 International Business Machines Corporation Borderless contacts for semiconductor devices
US8436404B2 (en) 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US8373239B2 (en) * 2010-06-08 2013-02-12 International Business Machines Corporation Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric
US8421077B2 (en) * 2010-06-08 2013-04-16 International Business Machines Corporation Replacement gate MOSFET with self-aligned diffusion contact
US8232607B2 (en) * 2010-11-23 2012-07-31 International Business Machines Corporation Borderless contact for replacement gate employing selective deposition
KR20120057818A (ko) * 2010-11-29 2012-06-07 삼성전자주식회사 반도체 장치 제조 방법
US8637359B2 (en) * 2011-06-10 2014-01-28 International Business Machines Corporation Fin-last replacement metal gate FinFET process
US20140179093A1 (en) * 2012-12-20 2014-06-26 GlobalFoundries, Inc. Gate structure formation processes
US9147748B1 (en) * 2014-05-01 2015-09-29 Globalfoundries Inc. Methods of forming replacement spacer structures on semiconductor devices
US9728505B2 (en) * 2015-11-16 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structrues of novel contact feature

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030156380A1 (en) * 1993-04-02 2003-08-21 Micron Technology, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
US6310367B1 (en) * 1999-02-22 2001-10-30 Kabushiki Kaisha Toshiba MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US20020192911A1 (en) * 2000-08-29 2002-12-19 Parke Stephen A. Damascene double gated transistors and related manufacturing methods
US20070104862A1 (en) * 2005-11-09 2007-05-10 Su-Chen Lai Gate structure and fabricating method thereof
US20080001236A1 (en) * 2006-06-28 2008-01-03 Change Peter L D Method of forming a transistor having gate protection and transistor formed according to the method
US20080166841A1 (en) * 2007-01-10 2008-07-10 Chao-Ching Hsieh Method of fabricating a strained silicon channel metal oxide semiconductor transistor
US20090026552A1 (en) * 2007-07-27 2009-01-29 Da Zhang Method for forming a transistor having gate dielectric protection and structure
US20090289334A1 (en) * 2008-05-21 2009-11-26 Willy Rachmady Metal gate structure and method of manufacturing same

Cited By (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594349A (zh) * 2012-08-17 2014-02-19 格罗方德半导体公司 形成具有栅极电极的替换栅极结构的方法
CN103594349B (zh) * 2012-08-17 2017-03-01 格罗方德半导体公司 形成具有栅极电极的替换栅极结构的方法
CN103811551A (zh) * 2012-11-05 2014-05-21 意法半导体公司 包括用于栅极电极的低k电介质帽层的半导体器件及相关方法
CN103811551B (zh) * 2012-11-05 2017-01-04 意法半导体公司 包括用于栅极电极的低k电介质帽层的半导体器件及相关方法
CN103871857A (zh) * 2012-12-18 2014-06-18 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN103871857B (zh) * 2012-12-18 2017-09-26 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN104051343B (zh) * 2013-03-14 2019-10-08 德克萨斯仪器股份有限公司 具有通过栅植入的深n阱的晶体管
CN104051343A (zh) * 2013-03-14 2014-09-17 德克萨斯仪器股份有限公司 具有通过栅植入的深n阱的晶体管
CN104124173A (zh) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN104143515A (zh) * 2013-05-09 2014-11-12 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN104143515B (zh) * 2013-05-09 2017-12-01 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN104576370A (zh) * 2013-10-18 2015-04-29 国际商业机器公司 形成晶体管的方法
CN104576370B (zh) * 2013-10-18 2018-03-27 国际商业机器公司 形成晶体管的方法
CN104681488B (zh) * 2013-11-26 2018-05-01 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN104681488A (zh) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN104716182B (zh) * 2013-12-12 2020-02-07 德州仪器公司 自对准作用沟槽触点
CN104716182A (zh) * 2013-12-12 2015-06-17 德州仪器公司 自对准作用沟槽触点
US9899265B2 (en) 2014-02-12 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures with various widths and method for forming the same
CN104835838A (zh) * 2014-02-12 2015-08-12 台湾积体电路制造股份有限公司 具有不同宽度的栅极结构及其制造方法
US10522412B2 (en) 2014-02-12 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures with various widths and method for forming the same
CN104835838B (zh) * 2014-02-12 2018-07-10 台湾积体电路制造股份有限公司 具有不同宽度的栅极结构及其制造方法
US10312092B2 (en) 2015-03-16 2019-06-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN105990405B (zh) * 2015-03-16 2019-12-13 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN105990405A (zh) * 2015-03-16 2016-10-05 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN106206270B (zh) * 2015-03-26 2020-06-23 联华电子股份有限公司 半导体器件及其制作方法
CN106206270A (zh) * 2015-03-26 2016-12-07 联华电子股份有限公司 半导体器件及其制作方法
US11127836B2 (en) 2015-09-30 2021-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate scheme for device and methods of forming
CN106558501B (zh) * 2015-09-30 2020-03-13 台湾积体电路制造股份有限公司 元件的金属栅极方案及形成所述金属栅极方案的方法
CN106558501A (zh) * 2015-09-30 2017-04-05 台湾积体电路制造股份有限公司 元件的金属栅极方案及形成所述金属栅极方案的方法
CN107026127A (zh) * 2015-12-09 2017-08-08 格罗方德半导体公司 Fdsoi技术的外延分面高度一致性改进
CN106920750B (zh) * 2015-12-28 2019-11-05 中芯国际集成电路制造(上海)有限公司 金属栅晶体管源漏区接触塞的制作方法
CN106920771A (zh) * 2015-12-28 2017-07-04 中芯国际集成电路制造(北京)有限公司 金属栅晶体管源漏区接触塞的制作方法
CN106920750A (zh) * 2015-12-28 2017-07-04 中芯国际集成电路制造(上海)有限公司 金属栅晶体管源漏区接触塞的制作方法
CN106920771B (zh) * 2015-12-28 2020-03-10 中芯国际集成电路制造(北京)有限公司 金属栅晶体管源漏区接触塞的制作方法
CN107170824B (zh) * 2016-03-07 2022-08-30 台湾积体电路制造股份有限公司 半导体装置
CN107170824A (zh) * 2016-03-07 2017-09-15 台湾积体电路制造股份有限公司 半导体装置
CN107452797A (zh) * 2016-04-28 2017-12-08 三星电子株式会社 半导体器件
CN107591366B (zh) * 2016-07-06 2020-06-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN107591366A (zh) * 2016-07-06 2018-01-16 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN107785259A (zh) * 2016-08-24 2018-03-09 中芯国际集成电路制造(北京)有限公司 一种半导体器件及制备方法、电子装置
CN107887438A (zh) * 2016-09-30 2018-04-06 台湾积体电路制造股份有限公司 半导体器件及其制造方法
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CN112309861A (zh) * 2019-07-30 2021-02-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、晶体管
CN112309861B (zh) * 2019-07-30 2023-10-13 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、晶体管
CN113327980A (zh) * 2020-02-28 2021-08-31 中芯国际集成电路制造（天津）有限公司 半导体结构及其形成方法
CN113327980B (zh) * 2020-02-28 2023-03-28 中芯国际集成电路制造（天津）有限公司 半导体结构及其形成方法

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