CN102736074A - Signal processor of laser Doppler radar based on FPGA (field programmable gate array) and processing method - Google Patents

Abstract

The invention discloses a signal processor of a laser Doppler radar based on an FPGA (field programmable gate array), and relates to the field of radar signal processing. The signal processor comprises an ADC (analog to digital converter) sampling unit, a storage unit and an FPGA processing unit, wherein the FPGA processing unit comprises an ADC configuration module, a storage interface module, a sampled data receiving module, a data input module, an intermediate frequency wave trap module, a diploid down sampling module, an FFT (fast Fourier transform) module, a pulse accumulating module, a peak extracting and Doppler frequency output module and a control module. After electrification, the FPGA configures an ADC and waits an external trigger signal; after the signal is effective, the FPGA begins receiving data sampled by the ADC; and the sampled data are all stored in the storage unit for caching through the FPGA, and then are read in the FPGA from the storage unit to be subjected to processing. By using the signal processor, the characteristics of the FPGA are adequately utilized; the processing speed is quick; the structure is simple; the problems of intermediate frequency interference, large data size and the like when the laser Doppler radar is used for speed measurement are solved; and the cost and the complexity of the laser Doppler radar are controlled beneficially.

Description

Laser Doppler radar signal processor and disposal route based on FPGA

Technical field

The present invention relates to radar signal processing field, be specifically related to a kind of signal processor and disposal route of the laser Doppler radar based on FPGA.

Background technology

Radar Doppler is to utilize the radar of because of the Doppler effect of caused by relative motion target being surveyed between radar and target, and what laser Doppler radar was launched is laser signal.Compare with microwave radar, characteristics such as it is shorter that the laser Doppler radar radar has operation wavelength, and the wave beam angle of divergence is little have high angle resoluting ability, distance resolution and Doppler range rate measurement resolution.Utilize the accurately movement velocity of measurement target object of laser Doppler radar: pulse signal of radar emission, signal has Doppler shift after target is returned, from echo, extract Doppler frequency and can calculate target velocity.Can extract the performance that Doppler frequency depends on the Radar Signal Processing device real-time and accurately.

Characteristics of laser Doppler radar signal Processing are big data quantities, because SF is often higher, and data sudden very strong, static memory is difficult to realize data storage so at a high speed, though and dynamic storage can be realized using complicated.Therefore how preserving the echo data with such characteristics in real time is the problem that the laser Doppler radar signal Processing faces.

Measure the occasion of negative velocity for needs, i.e. target and radar opposite-oriented movement, Doppler frequency at this moment is a negative value.The photodetector of radar front end can't obtain the output of negative frequency signal; Therefore transmitted wave need add an IF-FRE; Echo is not actually Doppler frequency and adds IF-FRE with adding the frequency values that obtains after the local oscillation signal mixing of intermediate frequency like this, can negative Doppler frequency be moved the positive frequency place.Because emission light leaks into the influence of receiving light path etc.; Can make the signal after the demodulation contain middle frequency interference signal; The amplitude of this IF-FRE makes dynamic range of signals very big much larger than the amplitude at Doppler frequency place, is unfavorable for follow-up processing and saves calculation resources.This is another problem that the laser Doppler radar signal Processing faces.

Speed dynamic range, rate accuracy and the real-time of laser Doppler radar institute energy measurement are its important indicators, and the speed dynamic range of institute's energy measurement is big more, and the usable range of expression radar is wide more; Rate accuracy is high more, and its result is reliable more; The speed refresh rate is high more, and radar can be got over and draw the result that tests the speed apace, and the range rate error that the while acceleration brings is more little.Big speed dynamic range means big Doppler frequency scope, also just means that the echoed signal after the demodulation has big bandwidth, and this need use the analog to digital converter (ADC) of higher SF, and is many thereby number of data points becomes; Rate accuracy is high, representes the just bigger bit wide of needs usefulness of each data point.Therefore, what the raising of these two indexs brought is the increase of data volume, and real-time requires to need in the short time to handle a large amount of echo datas.This is the 3rd problem that the laser Doppler radar signal Processing faces.

The operating distance of radar representes radar can be surveyed the target in how many distance ranges.Under the constant situation of front end hardware condition and surrounding environment, target range is far away more, useful signal intensity more a little less than, signal to noise ratio (S/N ratio) is low more.Therefore how from afar detecting useful signal in the echo of target is the 4th problem that the laser Doppler radar signal Processing faces.

Along with the development of computing machine and large scale integrated circuit technology, Digital Signal Processing becomes the core of Radar Signal Processing.The echo that laser Doppler radar receives utilizes ADC to analog signal sampling after nursing one's health through preliminary mimic channel, converts thereof into digital signal, utilizes the method for digital signal processing to obtain required target information then.

In the digital signal processing hardware of radar was realized, prior art mainly was to adopt digital signal processor (DSP), is responsible for all calculation tasks such as pre-service, FFT and frequency extraction.The deficiency of prior art is, under the certain situation of clock frequency, the arithmetic speed of DSP mainly depends on the number of multiplicaton addition unit, and its multiplicaton addition unit number is extremely limited, and this has limited the speed of DSP when filtering etc. needs a large amount of multiply-add operation.For example the TMS320C64x of TI series fixed DSP has two multipliers, can carry out 4 16 * 16bit computings simultaneously a clock period.Use the FIR wave filter of this series clock speed as 100 coefficients of a DSP realization of 800MHz, its Filtering Processing speed is merely 32MHz.As previously mentioned, the data volume of laser Doppler radar is big, and real-time requires high, can only utilize multi-disc DSP to carry out parallel processing so, and complexity and power consumption that this has increased system have reduced stability, also are unfavorable for controlling cost.

Therefore, laser Doppler radar needs the signal processor that a kind of speed is fast, precision is high, simple in structure.

Summary of the invention

The problem that faces to the laser Doppler radar signal Processing of above analysis and all deficiencies of current techniques the purpose of this invention is to provide a kind of signal processor and disposal route of the laser Doppler radar based on field programmable gate array (FPGA).The technical matters that the present invention will solve is: the buffer memory of Radar Signal Processing high speed, mass data and handling problem in real time, the intermediate frequency interference of laser Doppler radar and the low signal-to-noise ratio problem of long-range detection.The present invention makes full use of the characteristics of FPGA, cooperates ADC and static memory (SRAM), accomplishes whole work of laser Doppler radar signal Processing in real time.

For this reason, the invention provides a kind of signal processor of the laser Doppler radar of realizing with FPGA, referring to Fig. 1, the primary structure of this signal processor comprises:

Described ADC sampling unit is made up of a slice ADC, and model is the ADC12D1000 of National Semiconductor, and the simulating signal of input is carried out analog to digital conversion, and the output digital signal is to the FPGA processing unit; This model ADC has ten configuration pin: PDI, PDQ, ECE, DES, TPM, NDM, FSR, CALDLY, CAL, DDRPHASE; These ten pins all are connected to FPGA;, ADC is configured to two passages samples, export pattern, full scale input along separate routes respectively, go up electric delay 17ms calibration, clock through the configuration bus configuration by it than the data delay semiperiod;

Described storage unit is made up of two parallel SRAM, and the SRAM model is the CY7C1034DV33 of Cypress company; This model SRAM has three control pin: CE, WE, OE, and these three pins are connected to FPGA and are controlled through the SRAM control signal by it;

Described FPGA processing unit is made up of a slice FPGA, adopts the Virtex-II series of Xilinx company, and concrete model is XC2V3000; The FPGA processing unit comprises following ten modules:

The ADC configuration module, output configuration end signal is to control module, and the output configuration bus is connected to the ADC sampling unit;

Store interface module is input as data, address, the SRAM control signal of sampled data receiver module and data input module, and output data, address, SRAM control signal are to storage unit;

The sampled data receiver module is input as signal and the reset signal of control module after outside sampling trigger signal, the ADC sampling, is output as buffering write data, address, SRAM control signal and sampling end signal;

Data input module is input as the buffer memory sense data with reset signal, store interface module that enables of control module, is output as address, SRAM control signal, data useful signal and serial data;

Intermediate frequency trap module is input as the reset signal of control module, the data useful signal and the serial data of data input module, is output as data behind data useful signal and the trap;

2 times are fallen sampling module, are input as data behind data useful signal and the trap of reset signal, intermediate frequency trap module of control module, are output as the data useful signal and fall sampling back data;

The FFT module is input as reset signal, 2 times of data useful signals that fall sampling module of control module and falls sampling back data, is output as data useful signal and frequency spectrum data;

Pulse accumulation module is input as reset signal and the cumulative frequency control signal of control module, the data useful signal and the frequency spectrum data of FFT module, is output as frequency spectrum data;

Peak extraction and Doppler frequency are calculated module, are input as enabling and reset signal of control module;

Control module is input as the configuration end signal of ADC configuration module and the sampling end signal of sampled data receiver module, is output as reset signal, enable signal and cumulative frequency control signal;

The annexation of inner each module of FPGA is: the ADC configuration module is connected to control module through the configuration end signal of its output; The sampled data receiver module is connected with control module with reset signal through the sampling end signal, is connected with store interface module through buffering write data, address and SRAM control signal; Store interface module is connected with data input module with the SRAM control signal through buffer memory sense data, address; Data input module is connected with control module with reset signal through enabling, and is connected with intermediate frequency trap module with serial data through the data useful signal; Intermediate frequency trap module is connected with control module through reset signal, falls sampling module and is connected with 2 times through data behind data useful signal and the trap; 2 times are fallen sampling module and are connected with control module through reset signal, sample afterwards with falling that data are connected with the FFT module through the data useful signal; The FFT module is connected with control module through reset signal, is connected with pulse accumulation module with frequency spectrum data through the data useful signal; Pulse accumulation module is connected with control module with the cumulative frequency control signal through reset signal, calculates module through frequency spectrum data with peak extraction and Doppler frequency and is connected; Peak extraction is calculated module with Doppler frequency and is connected with control module with enable signal through resetting;

External analog signal is connected to the analog input pin of the contained ADC of ADC sampling unit; The configuration bus of the I/O pin output of FPGA is connected to each configuration pin of ADC; The digital output pin of ADC is connected to the I/O pin of FPGA; Outside sampling trigger signal is connected to the I/O pin of FPGA; The address of the I/O pin output of FPGA and the address pin that the SRAM control signal is connected respectively to the contained SRAM of storage unit and each control pin, the data of the I/O pin input and output of FPGA are connected to the data pin of SRAM.

The signal processor of this laser Doppler radar of realizing with FPGA provided by the invention, referring to Fig. 2, the flow process of its work is:

The a.ADC configuration module is configured ADC, and this step forwards step b to after finishing;

B. outer triggering signal starts the sampled data receiver module, signal after the sampling of buffer memory ADC sampling unit, and, after storage finishes, send the sampling end signal to control module with the SRAM in its write storage unit, this step forwards step c to after finishing;

C. control module receive the sampling end signal after the log-on data load module; From storage unit, read the monopulse echo data; Data are fallen sampling module through intermediate frequency trap module and 2 times successively, carry out trap and 2 times respectively and fall sampling processing, and this step forwards steps d to after finishing;

The data of d.2 doubly falling after the sampling are input to the FFT module, carry out Fourier transform, obtain the frequency spectrum of monopulse echo, and this step forwards step e to after finishing;

E. pulse accumulation module starts, and frequency spectrum is accumulated among the FIFO of this module, and this step forwards step f to after finishing;

F. after a monopulse echo accumulation finished, control module judged whether current cumulative frequency reaches designated value, when not reaching designated value, forwards step c to; If reach designated value, forward step g to;

G. peak extraction and Doppler frequency are calculated the module startup, read the multiple-pulse accumulation frequency spectrum of storing among the FIFO of pulse accumulation module, find out the position of peak point in sequence of frequency spectrum, calculate Doppler frequency then, and signal Processing finishes.

The advantage of this Radar Signal Processing device is:

(1) makes full use of big I/O bandwidth of FPGA and characteristics, make up the interior FIFO of sheet the data of ADC are carried out buffer memory with high speed Block RAM in a large amount of sheets.Adopt the multi-disc high-speed SRAM then, multi-site data is parallel, with the data cached SRAM that deposits in of FIFO in the sheet.Solved the echo data storage problem of high sampling rate, high sudden, big data quantity, and realize simple, flexible design, reliability is high.

(2) have the trapper module, the amplitude of frequency interference signal makes it suitable with the useful signal amplitude in can suppressing significantly, thereby reduces the dynamic range of data.In actual treatment under the certain situation of data bit width, can prevent like this that the useful signal amplitude is too small and reduce accuracy of detection.

(3) sampling suitable data volume that reduces under the situation that guarantees precision falls in utilization.The minimizing of data volume has brought the processing time minimizing, can reduce the use of internal storage space simultaneously.

(4) have frequency spectrum accumulation module, make this processor can handle the very little distant object echoed signal of signal to noise ratio (S/N ratio).

(5) make full use of the inner abundant register resources of FPGA, design flow waterline., data adopt pipeline system when falling sampling module through data input module, intermediate frequency trap module and 2 times; Therefore 2 times are fallen sampling module beginning to export the data after falling sampling through after the small delay, have reduced the use of processing time and storage inside.

(6) intermediate frequency trap module and 2 times of required constant multipliers of wave filter that fall sampling module utilize the inner Slice of FPGA to realize that speed is than fast with embedded multiplier.Each multiplier of wave filter is a Parallel Implementation, can in one-period, export a filtering data, has accelerated processing speed.2 times of filter coefficients that fall sampling module are designed with symmetry, can multiplexing multiplier, reduced half number of multipliers.Filter Structures has improved maximum operational speed through transposition.

Description of drawings

The signal processor general structure block diagram that Fig. 1 proposes for the present invention.

The signal processor workflow diagram that Fig. 2 proposes for the present invention, wherein M representes cumulative frequency.

Fig. 3 is trapper structural drawing, wherein f _iBe the intermediate frequency interfering frequency.

Fig. 4 is the structural drawing that falls the required low-pass filter of sampling.

Embodiment

The laser Doppler radar that the present invention is used for needs the measured speed scope to be-20m/s ~ 100m/s, and negative speed representes that target and radar are away from, the Doppler frequency f that this velocity range is corresponding with the emission laser of 1550nm wavelength _dFor-25.8MHz ~ 129MHz, IF-FRE adopts f _i=62.5MHz, the frequency range of echoed signal becomes 36.7MHz ~ 191.5MHz so.SF according to sampling thheorem ADC is decided to be 500MHz, and the sampling time is 32.768us, and so once sampling obtains the N=16384 point data.The transponder pulse repetition is 10KHz, i.e. twice recurrent intervals 100 μ s.

Introduce implementation of the present invention in detail according to specific targets set forth above below.

(1) ADC sampling unit.Be to realize the high-speed, high precision sampling, the present invention adopts the ADC12D1000 type ADC of (at present having incorporated Texas Instruments into) of National Semiconductor, and this ADC is 12bit, and high sampling rate is 2GSPS.The present invention is configured to SF 500MHz, and with the parallel 12bit data of frequency output two-way of 250MHz, the output sampling clock is 125MHz.

(2) storage unit.SRAM adopts the CY7C1034DV33 of Cypress company, and this model SRAM capacity is 256K * 24bit, and the fastest read or write speed reaches 125MHz.Storage unit of the present invention contains 2 SRAM and carries out parallel processing, and the I/O bandwidth of 48bit is provided, and writing clock is 75MHz, two SRAM multipotency storage 64 * 16384 12bit data, the i.e. data of 64 monopulses.

(3) FPGA processing unit.The present invention adopts the Virtex-II Series FPGA of Xilinx company, and model is XC2V3000.This model FPGA has 14336 Slice, 96 embedded multipliers, and 96 embedded RAM of 18Kbit can satisfy the high speed mass data processing and use.

(4) sampled data receiver module.The output interface bandwidth of aforementioned ADC is 24bit, and the output data frequency is 250MHz, and the input interface of this module utilizes the ADC 125MHz sampling clock of output synchronously, and the rise and fall that are designed to clock can be satisfied the data rate of ADC along operation simultaneously.After receiving sampled data, module is once gone here and there and is changed, and is the 48bit data with the 24bit data-switching, and the capacity of being written to is among the FIFO of 2048 * 48bit, and the clock that writes of this FIFO is 125MHz.As previously mentioned, the interface bandwidth of FIFO and sheet external memory unit (two SRAM are parallel) is 48bit, and readout clock is 75MHz.The required maximum buffer of 16384 12bit data that writes once sampling is 6553.6 * 12bit, so the capacity of FIFO is enough.

(5) intermediate frequency trap module.To the excessive problem of velocity radar intermediate frequency interference magnitude; The present invention adds the intermediate frequency trapper in treatment scheme, intermediate frequency is carried out trap, and the amplitude that makes its amplitude and Doppler frequency place quite or littler; Make the dynamic range of echo data reduce greatly, be beneficial to the detection useful signal.

Trapper extracts initial phase and the range parameter that intermediate frequency disturbs from signal; Utilize the newly-generated signal of these two parameter renegotiation then; This signal is the same with the intermediate frequency interference with initial phase in the amplitude at IF-FRE place, from original signal, deducts this signal of generation, realizes trap.Its structural drawing is as shown in Figure 3.

(6) 2 times are fallen sampling module, comprise shift frequency, LPF and extraction.As previously mentioned, the data volume that the ADC single pulse sampling obtains is 16384 points, and data volume is constant behind the trap.13684 point data are directly carried out the FFT conversion, and the required time, resource long, that take was many, therefore under the situation that guarantees precision, the data behind the trap is carried out 2 times fall sampling processing.

According to falling sampling theory; 2 times are fallen sampling and can make 2 times of video stretchings; Directly sampling being fallen in this signal can make its spectral range become 73.4MHz ~ 383MHz; And the signal highest frequency of sampling thheorem restriction is 250MHz, therefore directly falls sampling and can make highest frequency surpass the restriction of sampling thheorem and spectral aliasing takes place.The method that solves is the monolateral band of the only number of winning the confidence, because the symmetry of real signal frequency spectrum, its monolateral band has kept its whole spectrum informations.The frequency range of preparing to keep is 20MHz ~ 200MHz, and this frequency range has comprised the frequency of useful signal fully.Signal at first carries out shift frequency through frequency shifter behind the trap, with signal times behind the trap with complex frequency signal cos (2 π f ₁T)-jsin (2 π f ₁T), f ₁=110MHz, the frequency spectrum integral body of the echoed signal 110MHz that moves to left intends the spectral range that keeps and becomes-90MHz ~ 90MHz so.Be-low-pass filter of 90MHz ~ 90MHz that the signal of gained is the signal at former 20MHz ~ 200MHz place through passband then.Notice that present signal becomes 16284 plural numbers by 16284 original real numbers.At last this complex data is carried out 2 times of extractions, can obtain 8192 point data, operand becomes original half the.

Can utilize multiplier and inner Block RAM to constitute frequency shifter among the FPGA easily.BlockRAM is configured to the ROM form, wherein has the sample value of shift frequency frequency signal.The low-pass filter structure is as shown in Figure 4, is designed to 32 FIR wave filters, and coefficient has symmetry, and multiplier of the common use of identical coefficient has been saved resource.Wave filter realizes that with transpose configuration this can reduce required foundation the retention time when using FPGA to realize, be beneficial to the raising maximum operational speed.The coefficient of considering wave filter is a constant, uses Slice structure multiplier rather than embedded multiplier, and such benefit is that realization speed is fast, and has saved the resource of embedded multiplier.Because the FIR wave filter needs a large amount of multipliers, if use embedded multiplier, have only the FPGA of few high-end model just so many quantity can be provided, this obviously is unfavorable for cost control, and causes the waste of a large amount of other resources easily.And utilize distributed realization, and do not take embedded multiplier, also can make full use of remaining logical resource.Compare with DSP, FPGA can realize various structures according to actual needs neatly by the deviser, uses inner logical resource, can the distributed multiplier of Parallel Implementation, so wave filter can parallel processing, has accelerated processing speed.

(7) FFT module.This module is carried out FFT to the data of falling after the sampling, obtains frequency spectrum.Fall sampling because passed through before the FFT, data volume reduces, and the speed of FFT has been reduced requirement, and FFT module of the present invention be base 2 realizations, uses serial structure completely, just has only a butterfly processing element.This mode is than parallel mode simplicity of design, and it is convenient to realize, maintainable strong, the utilization of resources is also less.Do not consider the cycle of read-write cache etc., this processor realizes that 8192 FFT need 4096 * 13=53248 cycles, and clock frequency needs times spent 1064.96 μ s during for 50MHz.The Block RAM aboundresources that FPGA is inner can provide the buffer memory of intermediate data for FFT.

(8) pulse accumulation module.The echoed signal that pulse of the every emission of radar obtains is a monopulse echo, and radar is when detection is remote, and a little less than the echoed signal that obtains, and noise is stronger relatively, so the signal to noise ratio (S/N ratio) of monopulse is very low, needs to adopt multiple-pulse accumulation mode improve signal to noise ratio (S/N ratio).Pulse accumulation is divided into the coherent pulse accumulation to be accumulated with incoherent pulses, coherent accumulation to the raising of signal to noise ratio (S/N ratio) as shown in the formula shown in (1)

SNR _Mcoherent=M×SNR _s （1）

In the formula, SNR _McoherentBe the signal to noise ratio (S/N ratio) behind the coherent accumulation, M is the pile-up pulse number, SNR _sBe the monopulse signal to noise ratio (S/N ratio).The coherent pulse accumulative effect is better, but requires the phase place of pulse to have correlativity, in reality, is difficult to accomplish.The present invention adopts non-coherent accumulation, non-coherent accumulation to the raising of signal to noise ratio (S/N ratio) as shown in the formula shown in (2)

$\mathrm{SN}{R}_{\mathrm{Mnoncoherent}}=\sqrt{M}\×{\mathrm{SNR}}_s---\left(2\right)$

In the formula, SNR _MnoncoherentBe the signal to noise ratio (S/N ratio) after the non-coherent accumulation.Non-coherent accumulation does not require that impulse phase has correlativity, and the monopulse frequency spectrum data of FFT module output is directly imported the accumulation module, is added among the FIFO.Speed refresh rate and monopulse according to system requirements are handled the required time, can calculate the number of times of maximum accumulations.It is thus clear that, the processing speed of monopulse, promptly intermediate frequency trap, 2 times of speed of falling sampling and FFT are directly relevant with the pulse number that can accumulate.If the monopulse processing speed is slow, cumulative frequency is few so, and signal to noise ratio (S/N ratio) is low, even signal is buried in the noise fully, can't detect Doppler frequency.The monopulse processing speed is fast more, and the number of times that in system's official hour, can accumulate is just many more, and the signal to noise ratio (S/N ratio) that obtains is just big more, detects signal more easily.

(9) peak extraction and calculating Doppler frequency module.After accumulating certain number of times, obtain final frequency spectrum, need to detect the maximal value corresponding sequence number of spectrum amplitude.If the corresponding n data points in spectrum peak, and 0≤n＜N/2 is arranged.If n, explains that the spectrum peak is at the positive frequency place less than N/4; If n, explains that the spectrum peak at the negative frequency place, need be converted to negative value with it greater than N/4.Consider that 2 times are fallen sampling video stretching and the 110MHz frequently that moves to left, the spectrum peak place frequency f of so former echoed signal are arranged _MaxShown in (3)

$f_{\max }=\left\{\begin{array}{c}\frac{n}{N}\&times;500\mathrm{MHz}+110\mathrm{MHz},0\&le;n<N/4\\ \frac{n}{N}\&times;500\mathrm{MHz}-250\mathrm{MHz}+110\mathrm{MHz},N/4\&le;n<N/2\end{array}\right.---\left(3\right)$

Consider that transmitted wave has IF-FRE, so actual Doppler frequency f _dShould be

f _d=f _max-62.5MHz （4）

Utilize FPGA inner multiplier and totalizer can calculate Doppler frequency according to formula (3) (4).

The situation that top speed and resource were used when FPGA of the present invention unit was realized on the XC2V3000 of Xilinx company model FPGA is as shown in table 1.Maximum clock frequency in the attention table is the frequency of total system, and the sampled data receiver module of its front end still can adopt the clock that is higher than this frequency that data are received and dispatched.

Speed and resource after table 1FPGA realizes are used

The twice emitting recurrent intervals 100 μ s of laser Doppler radar accumulates if carry out M time, and all to store the required time of SRAM into be M * 100 μ s to M sampled data so.When XC2V3000 is 50MHz at system clock frequency; 16384: 12 bit data are read in and carried out intermediate frequency trap and 2 times to fall the required time of sampling be 327.7 μ s; Then carrying out the required time of FFT is 1065.0 μ s; Once accumulating the required time then is 163.8 μ s, thus monopulse to handle required T.T. be 1556.5 μ s.Suppose that velocity radar needs the speed refresh rate of 10Hz, the processing time of a speed data permission is 100ms so, and the cumulative frequency that can realize at most can be obtained by following formula

M×100μs+M×1556.5μs<100ms （5）

Obtain by formula (5) and can accumulate at most 60 times.Cumulative frequency of the present invention is decided to be 50 times, and handling required T.T. so is 82.8ms.

In sum, this laser Doppler radar signal processor structure based on FPGA that the present invention proposes is simple, and processing speed is fast, satisfies the signal Processing demand of laser Doppler radar.

Claims (2)

1. the laser Doppler radar signal processor based on FPGA comprises ADC sampling unit, storage unit and FPGA processing unit; It is characterized in that:

Described ADC sampling unit is made up of a slice analog to digital converter ADC, and model is the ADC12D1000 of National Semiconductor, and the simulating signal of input is carried out analog to digital conversion, and the output digital signal is to the FPGA processing unit; This model ADC has ten configuration pin: PDI, PDQ, ECE, DES, TPM, NDM, FSR, CALDLY, CAL, DDRPHASE; These ten pins all are connected to FPGA;, ADC is configured to two passages samples, export pattern, full scale input along separate routes respectively, go up electric delay 17ms calibration, clock through the configuration bus configuration by it than the data delay semiperiod;

Described storage unit is made up of two parallel static memory SRAM, and the SRAM model is the CY7C1034DV33 of Cypress company; This model SRAM has three control pin: CE, WE, OE, and these three pins are connected to FPGA and are controlled through the SRAM control signal by it;

Described FPGA processing unit is made up of a slice on-site programmable gate array FPGA, adopts the Virtex-II series of Xilinx company, and concrete model is XC2V3000; The FPGA processing unit comprises following ten modules:

The ADC configuration module, output configuration end signal is to control module, and the output configuration bus is connected to the ADC sampling unit;

Store interface module is input as data, address, the SRAM control signal of sampled data receiver module and data input module, and output data, address, SRAM control signal are to storage unit;

The sampled data receiver module is input as signal and the reset signal of control module after outside sampling trigger signal, the ADC sampling, is output as buffering write data, address, SRAM control signal and sampling end signal;

Data input module is input as the buffer memory sense data with reset signal, store interface module that enables of control module, is output as address, SRAM control signal, data useful signal and serial data;

Intermediate frequency trap module is input as the reset signal of control module, the data useful signal and the serial data of data input module, is output as data behind data useful signal and the trap;

2 times are fallen sampling module, are input as data behind data useful signal and the trap of reset signal, intermediate frequency trap module of control module, are output as the data useful signal and fall sampling back data;

The FFT module is input as reset signal, 2 times of data useful signals that fall sampling module of control module and falls sampling back data, is output as data useful signal and frequency spectrum data;

Pulse accumulation module is input as reset signal and the cumulative frequency control signal of control module, the data useful signal and the frequency spectrum data of FFT module, is output as frequency spectrum data;

Peak extraction and Doppler frequency are calculated module, are input as enabling and reset signal of control module;

Control module is input as the configuration end signal of ADC configuration module and the sampling end signal of sampled data receiver module, is output as reset signal, enable signal and cumulative frequency control signal;

The annexation of inner each module of FPGA is: the ADC configuration module is connected to control module through the configuration end signal of its output; The sampled data receiver module is connected with control module with reset signal through the sampling end signal, is connected with store interface module through buffering write data, address and SRAM control signal; Store interface module is connected with data input module with the SRAM control signal through buffer memory sense data, address; Data input module is connected with control module with reset signal through enabling, and is connected with intermediate frequency trap module with serial data through the data useful signal; Intermediate frequency trap module is connected with control module through reset signal, falls sampling module and is connected with 2 times through data behind data useful signal and the trap; 2 times are fallen sampling module and are connected with control module through reset signal, sample afterwards with falling that data are connected with the FFT module through the data useful signal; The FFT module is connected with control module through reset signal, is connected with pulse accumulation module with frequency spectrum data through the data useful signal; Pulse accumulation module is connected with control module with the cumulative frequency control signal through reset signal, calculates module through frequency spectrum data with peak extraction and Doppler frequency and is connected; Peak extraction is calculated module with Doppler frequency and is connected with control module with enable signal through resetting;

External analog signal is connected to the analog input pin of the contained ADC of ADC sampling unit; The configuration bus of the I/O pin output of FPGA is connected to each configuration pin of ADC; The digital output pin of ADC is connected to the I/O pin of FPGA; Outside sampling trigger signal is connected to the I/O pin of FPGA; The address of the I/O pin output of FPGA and the address pin that the SRAM control signal is connected respectively to the contained SRAM of storage unit and each control pin, the data of the I/O pin input and output of FPGA are connected to the data pin of SRAM.

2. the signal processing method based on Radar Signal Processing device as claimed in claim 1 is characterized in that, may further comprise the steps:

The a.ADC configuration module is configured ADC, and this step forwards step b to after finishing;

B. outer triggering signal starts the sampled data receiver module, signal after the sampling of buffer memory ADC sampling unit, and, after storage finishes, send the sampling end signal to control module with the SRAM in its write storage unit, this step forwards step c to after finishing;

C. control module receive the sampling end signal after the log-on data load module; From storage unit, read the monopulse echo data; Data are fallen sampling module through intermediate frequency trap module and 2 times successively, carry out trap and 2 times respectively and fall sampling processing, and this step forwards steps d to after finishing;

The data of d.2 doubly falling after the sampling are input to the FFT module, carry out Fourier transform, obtain the frequency spectrum of monopulse echo, and this step forwards step e to after finishing;

E. pulse accumulation module starts, and frequency spectrum is accumulated among the FIFO of this module, and this step forwards step f to after finishing;

F. after a monopulse echo accumulation finished, control module judged whether current cumulative frequency reaches designated value, when not reaching designated value, forwards step c to; If reach designated value, forward step g to;

G. peak extraction and Doppler frequency are calculated the module startup, read the multiple-pulse accumulation frequency spectrum of storing among the FIFO of pulse accumulation module, find out the position of peak point in sequence of frequency spectrum, calculate Doppler frequency then, and signal Processing finishes.

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