CN102867814A - 芯片封装体 - Google Patents

芯片封装体 Download PDF

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Publication number
CN102867814A
CN102867814A CN2011101881347A CN201110188134A CN102867814A CN 102867814 A CN102867814 A CN 102867814A CN 2011101881347 A CN2011101881347 A CN 2011101881347A CN 201110188134 A CN201110188134 A CN 201110188134A CN 102867814 A CN102867814 A CN 102867814A
Authority
CN
China
Prior art keywords
chip
layer
face
wire
packing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011101881347A
Other languages
English (en)
Chinese (zh)
Inventor
吴开文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Original Assignee
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongfujin Precision Industry Shenzhen Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical Hongfujin Precision Industry Shenzhen Co Ltd
Priority to CN2011101881347A priority Critical patent/CN102867814A/zh
Publication of CN102867814A publication Critical patent/CN102867814A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
CN2011101881347A 2011-07-06 2011-07-06 芯片封装体 Pending CN102867814A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011101881347A CN102867814A (zh) 2011-07-06 2011-07-06 芯片封装体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011101881347A CN102867814A (zh) 2011-07-06 2011-07-06 芯片封装体

Publications (1)

Publication Number Publication Date
CN102867814A true CN102867814A (zh) 2013-01-09

Family

ID=47446569

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011101881347A Pending CN102867814A (zh) 2011-07-06 2011-07-06 芯片封装体

Country Status (1)

Country Link
CN (1) CN102867814A (es)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104684370A (zh) * 2013-04-16 2015-06-03 天工方案公司 涉及利用表面贴装器件实施的接地路径的设备及方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1199927A (zh) * 1997-05-17 1998-11-25 现代电子产业株式会社 封装集成电路元件及其制造方法
US20020050407A1 (en) * 1997-07-14 2002-05-02 Signetics Kp Co., Ltd. Ground via structures in semiconductor packages
TW560019B (en) * 2001-02-15 2003-11-01 Broadcom Corp Enhanced die-down ball grid array and method for making the same
CN1489207A (zh) * 2002-08-23 2004-04-14 新光电气工业株式会社 半导体封装和半导体装置
CN101165866A (zh) * 2006-10-20 2008-04-23 美国博通公司 一种集成电路封装体及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1199927A (zh) * 1997-05-17 1998-11-25 现代电子产业株式会社 封装集成电路元件及其制造方法
US20020050407A1 (en) * 1997-07-14 2002-05-02 Signetics Kp Co., Ltd. Ground via structures in semiconductor packages
TW560019B (en) * 2001-02-15 2003-11-01 Broadcom Corp Enhanced die-down ball grid array and method for making the same
CN1489207A (zh) * 2002-08-23 2004-04-14 新光电气工业株式会社 半导体封装和半导体装置
CN101165866A (zh) * 2006-10-20 2008-04-23 美国博通公司 一种集成电路封装体及其制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104684370A (zh) * 2013-04-16 2015-06-03 天工方案公司 涉及利用表面贴装器件实施的接地路径的设备及方法
US10524350B2 (en) 2013-04-16 2019-12-31 Skyworks Solutions, Inc. Apparatus and methods related to conformal coating implemented with surface mount devices
US10561012B2 (en) 2013-04-16 2020-02-11 Skyworks Solutions, Inc. Methods related to implementing surface mount devices with ground paths
US10980106B2 (en) 2013-04-16 2021-04-13 Skyworks Solutions, Inc. Apparatus related to conformal coating implemented with surface mount devices

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20130109