CN102881630A - Manufacturing method for layer with ultralow dielectric constant - Google Patents
Manufacturing method for layer with ultralow dielectric constant Download PDFInfo
- Publication number
- CN102881630A CN102881630A CN2011101938241A CN201110193824A CN102881630A CN 102881630 A CN102881630 A CN 102881630A CN 2011101938241 A CN2011101938241 A CN 2011101938241A CN 201110193824 A CN201110193824 A CN 201110193824A CN 102881630 A CN102881630 A CN 102881630A
- Authority
- CN
- China
- Prior art keywords
- dielectric constant
- layer
- constant layer
- metal
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a manufacturing method for a layer with ultralow dielectric constant. The method comprises the following steps: depositing a layer with low dielectric constant on a metal layer of a silicon wafer and forming a photoetching adhesive layer with patterns of grooves and through holes on the layer with low dielectric constant through a photoetching way; etching the layer with low dielectric constant and forming grooves and through holes by taking the photoetching adhesive layer as a mask; removing the photoetching adhesive layer by using wet cleaning process, depositing metal in the grooves and the through holes, then burnishing the metal to the surface of the layer with low dielectric constant and forming metal connecting lines in the layer with low dielectric constant; performing ultraviolet irradiation on the layer with low dielectric constant for forming the layer with ultralow dielectric constant; and depositing a second metal barrier layer on the layer with low dielectric constant provided with the metal connecting lines and then burnishing the second metal barrier layer for covering the metal connecting line. According to the method provided by the invention, a dielectric constant material in the manufactured layer with ultralow dielectric constant can be prevented from moving.
Description
Technical field
The present invention relates to the making field of semiconductor device, particularly a kind of manufacture method of ultralow dielectric constant layer.
Background technology
In the manufacturing process of semiconductor device, need to make inter-level dielectric.Inter-level dielectric has served as the dielectric material between the silicon substrate of each layer intermetallic and the first metal layer and semiconductor device.Usually, inter-level dielectric all is to adopt silicon dioxide as material, but parasitic resistance values is higher, can affect the performance of the final semiconductor device of making, especially along with the development of semiconductor technology, the characteristic size of semiconductor device is more and more less, and this situation is just more and more serious.Therefore, increased the low-dielectric constant layer that can reduce parasitic resistance values at dielectric layer, this low-dielectric constant layer adopts advanced low-k materials, black diamond (the black diamond that for example contains the similar oxide of silicon, oxygen, carbon and protium, BD) etc., so just can reduce the parasitic resistance values of whole dielectric layer.
In order further to reduce the parasitic resistance values of whole dielectric layer, ultralow dielectric constant layer has appearred in the basis at low-dielectric constant layer, after namely low-dielectric constant layer being carried out ultraviolet ray (UV) irradiation, form the ultralow dielectric constant layer of loose structure, its parasitic resistance values can lack 40% than low-dielectric constant layer.But, ultralow dielectric constant layer as inter-level dielectric, in the process of follow-up making metal connecting line, usually can be caused the migration of dielectric constant material, thereby can improve parasitic resistance values.
Fig. 1 is the method flow diagram that prior art is made the ultralow dielectric constant layer with metal connecting line, makes the designs simplification profile of the ultralow dielectric constant layer with metal connecting line in conjunction with the prior art shown in Fig. 2 a～Fig. 2 d, and the method is elaborated:
Before this step, made device layer at silicon chip, comprise grid and active area etc., then on device layer, make metal level 11, since irrelevant with the present invention, in Fig. 2 a, do not embody;
In this step because ultralow dielectric constant layer 12 ' has loose structure, so when etching owing to the effect of ultralow dielectric constant layer 12 ', can cause the migration of dielectric constant material;
In this step because ultralow dielectric constant layer 12 ' has loose structure, so since in PVD mode plated metal and CMP mode polishing metal process to the effect of ultralow dielectric constant layer 12 ', can cause the migration of dielectric constant material.
Can find out from said process, because ultralow dielectric constant layer 12 ' has loose structure, namely structure is more sparse, when etching, PVC and CMP, will produce larger impact to the sparse ultralow dielectric constant layer 12 ' of structure, cause the migration of dielectric constant material wherein, and the migration of dielectric constant material wherein can so that the parasitic resistance values of ultralow dielectric constant layer 12 ' raises, can finally reduce the performance of the semiconductor device of making again.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of ultralow dielectric constant layer, the method can prevent the migration of the dielectric constant material in the ultralow dielectric constant layer of made.
For achieving the above object, technical scheme of the invention process specifically is achieved in that
A kind of manufacture method of ultralow dielectric constant layer, the method comprises:
Metal level at silicon chip deposits low-dielectric constant layer, adopts photolithographicallpatterned to form the photoresist layer of the pattern with groove and through hole at described low-dielectric constant layer;
Take described photoresist layer as mask, the described low-dielectric constant layer of etching forms groove and through hole;
After wet-cleaned was removed photoresist layer, behind groove and through hole plated metal, the polishing metal formed metal connecting line to described low-dielectric constant layer surface in described low-dielectric constant layer;
Described low-dielectric constant layer is adopted UV-irradiation, form ultralow dielectric constant layer;
Have on the described low-dielectric constant layer of metal connecting line behind the plated metal barrier layer, polishing covers metal connecting line.
Described metal barrier is low-dielectric constant layer.
The thickness on described plated metal barrier layer is 100～3000 dusts.
Described polishing adopts chemical-mechanical planarization CMP mode to carry out, and the thickness of remaining metal barrier is 100～500 dusts after the polishing.
The described time to described low-dielectric constant layer employing UV-irradiation is 50～100 seconds, and power powder is 100 watts.
The abrasive material on described polishing metal to described low-dielectric constant layer surface is the mixed solvent of ammoniacal liquor NH4OH and hydrogen peroxide.
As seen from the above technical solution, the present invention is after adopting successively photoetching, etching, PVD and CMP mode to make metal connecting line first on the low-dielectric constant layer, again low-dielectric constant layer is adopted the UV irradiation to form ultralow dielectric constant layer, like this, just can not be as prior art, when etching, PVC and CMP, will produce larger impact to the sparse ultralow dielectric constant layer of the structure that has formed, cause the migration of dielectric constant material wherein.Just low-dielectric constant layer is formed ultralow dielectric constant layer at last, because adopting the UV irradiation can shrink, so that metal connecting line is higher than ultralow dielectric constant layer, so also need to have on the described low-dielectric constant layer of metal connecting line behind the plated metal barrier layer, polishing, cover metal connecting line, prevent the metal connecting line short circuit.Therefore, method provided by the invention prevents the migration of the dielectric constant material in the ultralow dielectric constant layer of made.
Description of drawings
Fig. 1 is the method flow diagram that prior art is made the ultralow dielectric constant layer with metal connecting line;
Fig. 2 a～Fig. 2 d is the designs simplification profile that prior art is made the ultralow dielectric constant layer with metal connecting line;
Fig. 3 is the method flow diagram that the present invention makes the ultralow dielectric constant layer with metal connecting line;
Fig. 4 a～4f is the designs simplification profile that the present invention makes the ultralow dielectric constant layer with metal connecting line.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
Can find out from prior art, cause the reason of the migration of ultralow dielectric constant layer dielectric constant material wherein to be, can adopt etching, PVD and CMP when making metal connecting line in ultralow dielectric constant layer, these all can produce larger impact to the sparse ultralow dielectric constant layer of structure.Therefore, the present invention has adopted after adopting successively photoetching, etching, PVD and CMP mode to make metal connecting line first on the low-dielectric constant layer in order to overcome this problem, low-dielectric constant layer is adopted the UV irradiation to form ultralow dielectric constant layer again.Because the compact structure of low-dielectric constant layer so etching, PVD and the CMP that can not adopt exert an influence, causes the migration of dielectric constant material wherein when making metal connecting line, make again at last ultralow dielectric constant layer and can further reduce dead resistance.
Further, when forming ultralow dielectric constant layer by low-dielectric constant layer, can shrink, and the metal connecting line that is formed on wherein can not shrink, this will cause metal connecting line surface and the final ultralow dielectric constant layer surface that forms not at grade, but is higher than the ultralow dielectric constant layer surface.In order to overcome this problem, also need to have on the described low-dielectric constant layer of metal connecting line behind the plated metal barrier layer, polishing covers metal connecting line.
Here, metal barrier can be low-dielectric constant layer or silicon dioxide layer.
Fig. 3 is the method flow diagram that the present invention makes the ultralow dielectric constant layer with metal connecting line, is the designs simplification profile that the present invention makes the ultralow dielectric constant layer with metal connecting line in conjunction with Fig. 4 a～4f, and the present invention is described in detail:
Before this step, made device layer at silicon chip, comprise grid and active area etc., then on device layer, make metal level 11, since irrelevant with the present invention, in Fig. 4 a, do not embody;
In this step, for adopting the abrasive material of high selectivity, the excess metal of removing fast low-dielectric constant layer 12 surfaces when the CMP carries out, and this abrasive material is the mixed solvent of ammoniacal liquor (NH4OH) and hydrogen peroxide;
In this step, the UV irradiation time is 50～100 seconds, and power powder is 100 watts;
In this step, owing to adopt the UV irradiation to shrink, so that metal connecting line is higher than ultralow dielectric constant layer 12 ';
In this step, the thickness of the metal barrier 22 of deposition is 100～3000 dusts;
In this step, polishing adopts the CMP mode to carry out, and the thickness of remaining metal barrier is 100～500 dusts after the polishing.
In this embodiment, BARC can omit, and the material of metal level can be copper.
Above act preferred embodiment; the purpose, technical solutions and advantages of the present invention are further described; institute is understood that; the above only is preferred embodiment of the present invention; not in order to limit the present invention; within the spirit and principles in the present invention all, any modification of doing, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the manufacture method of a ultralow dielectric constant layer, the method comprises:
Metal level at silicon chip deposits low-dielectric constant layer, adopts photolithographicallpatterned to form the photoresist layer of the pattern with groove and through hole at described low-dielectric constant layer;
Take described photoresist layer as mask, the described low-dielectric constant layer of etching forms groove and through hole;
After wet-cleaned was removed photoresist layer, behind groove and through hole plated metal, the polishing metal formed metal connecting line to described low-dielectric constant layer surface in described low-dielectric constant layer;
Described low-dielectric constant layer is adopted UV-irradiation, form ultralow dielectric constant layer;
Have on the described low-dielectric constant layer of metal connecting line behind the plated metal barrier layer, polishing covers metal connecting line.
2. will go 1 described method such as right, it is characterized in that, described metal barrier is low-dielectric constant layer.
3. method as claimed in claim 1 or 2 is characterized in that, the thickness on described plated metal barrier layer is 100～3000 dusts.
4. method as claimed in claim 3 is characterized in that, described polishing adopts chemical-mechanical planarization CMP mode to carry out, and the thickness of remaining metal barrier is 100～500 dusts after the polishing.
5. method as claimed in claim 1 or 2 is characterized in that, the described time to described low-dielectric constant layer employing UV-irradiation is 50～100 seconds, and power powder is 100 watts.
6. method as claimed in claim 1 or 2 is characterized in that, the abrasive material on described polishing metal to described low-dielectric constant layer surface is the mixed solvent of ammoniacal liquor NH4OH and hydrogen peroxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101938241A CN102881630A (en) | 2011-07-12 | 2011-07-12 | Manufacturing method for layer with ultralow dielectric constant |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101938241A CN102881630A (en) | 2011-07-12 | 2011-07-12 | Manufacturing method for layer with ultralow dielectric constant |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102881630A true CN102881630A (en) | 2013-01-16 |
Family
ID=47482910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101938241A Pending CN102881630A (en) | 2011-07-12 | 2011-07-12 | Manufacturing method for layer with ultralow dielectric constant |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102881630A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112702A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for decreasing ultra-low-k dielectric layer damage in semiconductor manufacture |
| CN104900580A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1610091A (en) * | 2003-10-17 | 2005-04-27 | 学校法人早稻田大学 | Semiconductor multi-layer wiring plate and forming method thereof |
| CN1832128A (en) * | 2005-02-22 | 2006-09-13 | 国际商业机器公司 | Method of manufacturing interconnection structure and interconnection structure forming by thereof |
| US20090280637A1 (en) * | 2008-05-07 | 2009-11-12 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device including ultra low dielectric constant layer |
-
2011
- 2011-07-12 CN CN2011101938241A patent/CN102881630A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1610091A (en) * | 2003-10-17 | 2005-04-27 | 学校法人早稻田大学 | Semiconductor multi-layer wiring plate and forming method thereof |
| CN1832128A (en) * | 2005-02-22 | 2006-09-13 | 国际商业机器公司 | Method of manufacturing interconnection structure and interconnection structure forming by thereof |
| US20090280637A1 (en) * | 2008-05-07 | 2009-11-12 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device including ultra low dielectric constant layer |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112702A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for decreasing ultra-low-k dielectric layer damage in semiconductor manufacture |
| CN104112702B (en) * | 2013-04-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | The method reducing ultra-low-k dielectric layer damage in semiconductor fabrication |
| CN104900580A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
| CN104900580B (en) * | 2014-03-04 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100515671C (en) | Chemically mechanical polishing process and process for polishing copper layer oxide on base | |
| US9099400B2 (en) | Semiconductor device manufacturing methods | |
| CN107665829B (en) | method for improving metal lead process safety in wafer hybrid bonding | |
| CN103337475B (en) | The synchronous etching technics of double structure contact hole | |
| TWI518765B (en) | Method and apparatus for improving cmp planarity | |
| CN105575887A (en) | Interconnection structure formation method | |
| TW201338225A (en) | Method of making device | |
| CN104701143B (en) | Dual layer hardmask for robust metallization profile | |
| US20140097539A1 (en) | Technique for uniform cmp | |
| CN103066014A (en) | Copper/ air gap preparation method | |
| CN102881630A (en) | Manufacturing method for layer with ultralow dielectric constant | |
| US8673768B2 (en) | Fabrication method for improving surface planarity after tungsten chemical mechanical polishing | |
| US9330989B2 (en) | System and method for chemical-mechanical planarization of a metal layer | |
| CN102881584A (en) | Manufacturing method for layer with ultralow dielectric constant | |
| US8354341B2 (en) | Method for forming an interconnect structure | |
| CN104821279B (en) | The forming method of semiconductor devices | |
| KR100641992B1 (en) | Method for fabricating copper wiring | |
| CN103794545A (en) | Method for manufacturing metal interconnecting wire | |
| CN112259501B (en) | Optimization method for contact hole chemical mechanical planarization | |
| CN104302811B (en) | All integrate the metal hard mask in etching one | |
| JP5924198B2 (en) | Manufacturing method of semiconductor device | |
| CN105742183A (en) | Method for forming semiconductor structure | |
| CN106971973B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| JP2008251741A (en) | Manufacturing method of semiconductor device | |
| CN103151300A (en) | Method for removing defects in hard mask structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130116 |