CN102956704B - Accurate vertical power mosfet and forming method thereof - Google Patents

Accurate vertical power mosfet and forming method thereof Download PDF

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Publication number
CN102956704B
CN102956704B CN201210084622.8A CN201210084622A CN102956704B CN 102956704 B CN102956704 B CN 102956704B CN 201210084622 A CN201210084622 A CN 201210084622A CN 102956704 B CN102956704 B CN 102956704B
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gate electrode
oxide
semiconductor substrate
face
tagma
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CN102956704A (en
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陈吉智
田昆玄
柳瑞兴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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Abstract

MOSFET comprises Semiconductor substrate, has: end face; The tagma of the first conduction type, is arranged in described Semiconductor substrate; And DDD district of double diffusion district, there is the end face of the bottom surface lower than tagma.DDD district is the second conduction type, and the second conduction type is contrary with the first conduction type.MOSFET comprises further: gate oxide, and by gate electrode that gate oxide and tagma keep apart.A part for gate oxide and a part for gate electrode are lower than the end face in tagma.

Description

Accurate vertical power mosfet and forming method thereof
Technical field
The present invention relates in general to semiconductor applications, more specifically, relates to accurate vertical power mosfet and forming method thereof.
Background technology
Metal-oxide semiconductor (MOS) (LDMOS) device of horizontal proliferation is widely used in power management applications due to the superperformance of its puncture voltage BVdss and conducting resistance Ron.Traditional LDMOS can comprise the gate stack above well region and well region, and this gate stack comprises gate dielectric and gate electrode.Tagma and double-diffused drain electrode (DDD) district extend to below gate stack, and this tagma and double-diffused drain electrode are kept apart by the part being positioned at the well region immediately below gate stack.Source electrode pick-up area is arranged on the relative both sides of gate stack with drain electrode pick-up area, and is respectively formed at above tagma and DDD district.
The cell gap of LDMOS is determined by the lateral dimension in gate stack, tagma, DDD district etc.In order to obtain the puncture voltage BVdss of expectation, the cell gap of LDMOS can not be less than particular value usually, therefore, have lost conducting resistance Ron.Therefore, the scale of the gate densities of LDMOS is reduced have received restriction.
Summary of the invention
For solving the problem, the invention provides a kind of device, comprising: mos field effect transistor MOSFET comprises: Semiconductor substrate, comprises end face; Tagma, has the first conduction type, is arranged in Semiconductor substrate; Double-diffused drain electrode DDD district, has end face, and end face is lower than the bottom surface in tagma, and wherein, DDD district is the second conduction type, and the second conduction type is contrary with the first conduction type; Gate oxide; And gate electrode, by gate oxide and tagma spaced apart, wherein, a part for gate oxide and a part for gate electrode are positioned at the below of the end face in tagma.
Wherein, the bottom of gate oxide is lower than the bottom surface in tagma.
Wherein, the end face in DDD district is lower than the bottom of gate electrode.
Wherein, gate electrode comprises top and is positioned at the bottom of below an upper section, wherein, spaced first spacing of forefield in top and tagma, first spacing equals the thickness of gate electrode, and wherein, spaced second spacing of forefield of bottom and Semiconductor substrate, the second spacing is greater than the first spacing.
This device comprises further: dark conductive plug, dark conductive plug extends downwardly into DDD district from the horizontal plane flushed with the top of gate electrode.
Wherein, gate electrode comprises two parts, is positioned at the horizontal plane place identical with a part for dark conductive plug, and wherein, two parts are positioned at the relative both sides of dark conductive plug.
This device comprises further: the source electrode pick-up area of the second conduction type; And the first body pick-up area of conduction type, wherein, source electrode pick-up area and body pick-up area extend to Semiconductor substrate from the end face of Semiconductor substrate substantially.
In addition, additionally provide a kind of device, comprising: mos field effect transistor MOSFET, comprising: raceway groove, extend to Semiconductor substrate from the end face of Semiconductor substrate; Gate electrode, from the end face of Semiconductor substrate to downward-extension, wherein, gate electrode is arranged in raceway groove; Tagma, is arranged in Semiconductor substrate, and wherein, tagma is the first conduction type; Gate oxide, between tagma and the top of gate electrode, wherein, gate oxide is disposed vertically on the direction vertical with the end face of Semiconductor substrate; And double-diffused drain electrode DDD district, be the second conduction type, the second conduction type is contrary with the first conduction type, and wherein, DDD district is lower than tagma.
Wherein, gate oxide has the first thickness, and wherein, gate electrode comprises further: bottom, lower than top, and wherein, bottom is kept apart by the forefield of dielectric region and Semiconductor substrate, and dielectric region has the second thickness, and the second thickness is greater than the first thickness.
Wherein, the whole bottom of gate electrode is lower than whole tagma.
This device comprises further: dark conductive plug, extends downwardly into DDD district from the top of raceway groove.
Wherein, gate electrode comprises two parts, is positioned at the horizontal plane place identical with a part for dark conductive plug, and wherein, two parts are positioned at the relative both sides of dark conductive plug.
This device comprises further: the drain electrode pick-up area of the second conduction type, is arranged in DDD district, and wherein, drain electrode pick-up area to be positioned at immediately below dark conductive plug and to be electrically connected with dark conductive plug.
In addition, additionally provide a kind of method, comprising: form raceway groove, raceway groove extends to Semiconductor substrate from the end face of Semiconductor substrate; The double-diffused drain electrode DDD district of the first conduction type to be formed in Semiconductor substrate and below raceway groove; Formed in channels the first oxide region, wherein, the first oxide region comprises: the sidewall portion of the base section being positioned at the bottom place of raceway groove and the side-walls that is positioned at raceway groove, and wherein, and the top in sidewall portion is lower than the end face of Semiconductor substrate; Form gate oxide, gate oxide extends downwardly into the top in the sidewall portion of the first oxide region from the end face of Semiconductor substrate; On sidewall gate electrode being formed in gate oxide and on the sidewall in the sidewall portion of the first oxide region; And formation tagma, the end face of the contiguous Semiconductor substrate in tagma, wherein, tagma is the second conduction type, and the second conduction type is contrary with the first conduction type.
The method comprises further: after the step forming gate electrode, fill the second oxide region in the remainder of raceway groove; Etch the second oxide region, thus form opening, wherein, exposed the end face in DDD district by opening; Inject DDD district by opening, thus form drain electrode pick-up area; And fill dark conductive plug in the opening.
The method comprises further: top face contact plug being formed in Semiconductor substrate, and wherein, contact plug is electrically connected with dark conductive plug.
Wherein, the step forming the first oxide region comprises: fill oxide in the bottom of raceway groove; Distance piece is formed in above oxide with on the sidewall of raceway groove; And use distance piece as mask etching oxide, wherein, the remainder of oxide forms the first oxide region.
Wherein, the step forming gate oxide comprises thermal oxidation.
Wherein, the step forming gate electrode comprises: form gate electrode layer, gate electrode layer comprises: Part I, is positioned at the outside of raceway groove; Part II, on the sidewall being positioned at gate oxide and on the sidewall in the sidewall portion of the first oxide region; And Part III, be positioned at the bottom place of raceway groove; And etch-gate electrode layer, thus form gate electrode, wherein, remove Part I and the Part III of gate electrode layer, and retain the Part II of gate electrode layer, thus form gate electrode.
The method comprises further: form source electrode pick-up area, and the end face of contiguous Semiconductor substrate, wherein, source electrode pick-up area is the first conduction type, and wherein, source electrode pick-up area comprises two parts, is positioned at the relative both sides of raceway groove.
Accompanying drawing explanation
In order to understand embodiment and advantage thereof better, now by following description carried out by reference to the accompanying drawings as a reference, wherein:
Fig. 1 to Figure 13 is the cross-sectional view in the interstage during the manufacture of N-shaped power metal oxide semiconductor field-effect transistor (MOSFET) according to each embodiment; And
Figure 14 shows the cross-sectional view of p-type power MOSFET.
Embodiment
Below, manufacture and the use of the embodiment of the present invention is discussed in detail.But, should be appreciated that, present embodiments provide many applicable inventive concepts that can realize in various specific environment.The specific embodiment discussed is only exemplary, and is not used in restriction the scope of the present disclosure.
Power metal oxide semiconductor field-effect transistor (MOSFET) and forming method thereof is provided according to multiple embodiment.Show the interstage forming power MOSFET.Discuss the modified example of embodiment.In whole accompanying drawing and described embodiment, identical reference number is used to specify identical element.
Fig. 1 to Figure 13 is at the cross-sectional view forming the interstage during N-shaped power MOSFET.With reference to figure 1, provide Semiconductor substrate 20.Semiconductor substrate 20 can be crystalline silicon substrate.Alternatively, Semiconductor substrate 20 can be formed by other semi-conducting materials, such as, and SiGe.In addition, Semiconductor substrate 20 can be bulk substrate.Semiconductor substrate 20 can have p-type impurity by light dope, such as boron or indium.In an embodiment, N-shaped well region 22 is formed in the substrate 20, and can extend to Semiconductor substrate 20 from the end face 20A of Semiconductor substrate 20.Shallow trench isolation (STI) district 24 also can extend to Semiconductor substrate 20 from the end face 20A of Semiconductor substrate 20.
With reference to figure 2, formed and pattern mask 28.In an embodiment, mask 28 is formed by silicon nitride.Then, etching well region 22, thus use mask 28 to make etching mask formation raceway groove 30.In an embodiment, the degree of depth D1 of raceway groove 30 is greater than about 1 μm.Degree of depth D1 also may be greater than the degree of depth D2 of STI region 24.Next, implement injection as shown by arrows, thus N-shaped impurity is injected in raceway groove 30, and be injected in a part for the well region 22 be in below raceway groove 30, thus form double-diffused drain electrode (DDD) district 32.In an embodiment, DDD district 32 has and is in about 10 16/ cm 3with about 10 17/ cm 3between impurity concentration.
Fig. 3 shows the formation of the dielectric region 34 in raceway groove 30.Dielectric region 34 can be formed by the oxide of such as silica, therefore, hereinafter, this dielectric region is called oxide region 34, but this dielectric region can be formed by other dielectric materials in addition to oxide.In the exemplary formation process forming oxide region 34, raceway groove 30 is filled with oxide, until the end face of oxide (using shown in dotted line 36) is higher than the end face of mask 28.Then, implement the leveling of such as chemico-mechanical polishing (CMP), thus the end face of the oxide of filling is flattened, until the end face of oxide flushes with the end face of mask 28.Then, implement etching step to make oxide recessed, and the oxide generated forms oxide region 34.
With reference to figure 4, form distance piece 38, the formation of distance piece 38 can comprise: form all thick (blanket) wall, then, implement etching step, thus remove the horizontal component of wall, and the vertical component of wall is retained on the sidewall of raceway groove 30, to form distance piece 38.The vertical component of wall forms distance piece 38.The material (such as silicon nitride) identical with the material of mask 28 can be used to form distance piece 38, but distance piece 38 and mask 28 can be formed by different materials.Next, as shown in Figure 5, distance piece 38 is used as mask to make oxide region 34 recessed.After etching oxide district 34, rest layers 34A is retained in the bottom of raceway groove 30.In an embodiment, be etched to the anisotropic etching using dry-etching method to implement, but also can use wet etch process.
Fig. 6 shows and removes separator 38 and mask 28, and wherein, such as, the etchant of etching can comprise H 3pO 4solution.In addition, any pad oxide (padoxide) (not shown) be positioned at below mask 28 is also removed.Then, the surface of exposing semiconductor substrate 20, wherein, the surface of exposure comprises the part in the face of raceway groove 30.Next, as shown in Figure 7, implement thermal oxidation, thus oxide skin(coating) 42 is formed on the surface of substrate 20/ well region 22.Oxide skin(coating) 42 comprises the horizontal component being in raceway groove 30 outside, and is positioned at the vertical component of raceway groove 30 inside.As the result of thermal oxidation, oxide skin(coating) 42 can comprise Part I, and this Part I is positioned at the top of raceway groove 30.Wherein, Part I has the first thickness T1.Oxide skin(coating) 42 comprises Part II further, and this Part II contacts with the exterior side wall of oxide region 34.Dotted line 43 schematically shows the interface between the Part II and oxide region 34 of oxide skin(coating) 42.In describing in the whole text, reference number 34 ' represents the Part II of oxide skin(coating) 42 and the combination region of oxide region 34.The sidewall portion of oxide region 34 ' has thickness T2, and this thickness T2 is greater than thickness T1.
Fig. 8 shows the deposition of gate electrode layer 44.In an embodiment, gate electrode layer 44 is polysilicon layer, and such as, this gate electrode layer can have N-shaped impurity for in-situ doped.In an alternative embodiment, gate electrode layer 44 is formed by other electric conducting materials, such as, and metal, metal silicide etc.Gate electrode layer 44 comprises the horizontal component be positioned at above substrate 20, the horizontal component being positioned at the bottom place of raceway groove 30 and the vertical component be positioned on the sidewall of raceway groove 30.
Fig. 9 shows and implements etching to gate electrode layer 44, thus makes the horizontal component removing gate electrode layer 44, and the vertical component of gate electrode layer 44 is retained on the sidewall of oxide region 34 ' and gate oxide level 42.The remainder of gate electrode layer 44 forms gate electrode 46.In the vertical view of the structure shown in Fig. 9, gate electrode 46 can form the ring around residue raceway groove 30.Gate electrode 46 can comprise the Part I on the vertical component being positioned at oxide skin(coating) 42, and is positioned at the Part II on the sidewall of oxide region 34 '.The Part I of gate electrode 46 has thickness T3, and this thickness T3 is substantially equal to the thickness T4 of Part II.
With reference to Figure 10, form dielectric region 50, thus fill residue raceway groove 30.The formation of dielectric region 50 can comprise: be filled into by dielectric material in raceway groove 30, arrives the horizontal plane of the end face 20A higher than Semiconductor substrate 20, then implements CMP, thus removes the redundance of the dielectric material be positioned at above end face 20A.In an embodiment, dielectric region 50 comprises silica, but this dielectric region also can be formed by other dielectric materials.In the structure generated, such as, removed the horizontal component of oxide skin(coating) 42 by CMP, and in describing, the residue vertical component of oxide skin(coating) 42 is called gate oxide 45 in the whole text.Gate oxide 45 is used as the power MOSFET 100 generated gate oxide (gate-dielectric) (Figure 13).
Figure 11 shows the formation of p-type body district 52, p-type body pick-up area 54 and source electrode pick-up area 56.P-type body district 52 and p-type body pick-up area 54 are formed by being injected into by p-type impurity in well region 22/ substrate 20, and source electrode pick-up area 56 is formed by being injected into by N-shaped impurity in well region 22/ substrate 20.The impurity concentration in p-type body district 52 is lower than the impurity concentration of p-type body pick-up area 54 and source electrode pick-up area 56.In the exemplary embodiment, p-type body district 52 has about 10 17/ cm 3with about 10 18/ cm 3between impurity concentration.P type body pick-up area 54 and source electrode pick-up area 56 are heavily doped region.In the embodiment shown, term " heavy doping " expression is greater than about 10 19/ cm 3impurity concentration.But those of skill in the art should be understood that heavy doping is the technical term depending on the generation of certain device types, technology, least part size etc.In an embodiment, the bottom 45A of gate oxide 45 lower than the bottom surface 52A in p-type body district 52, thus guarantees that raceway groove (channel) is formed in above the low side of gate oxide 45.Bottom surface 52A can higher than low side 45A deviation delta H, and in the exemplary embodiment, this deviation is greater than about 0.1 μm.
In fig. 12, make dielectric region 50 recessed, thus at the middle formation opening 60 of dielectric region 50 and oxide region 34 ', wherein, expose DDD district 32 by opening 60.Gate electrode 46 is spaced apart with opening 60 by remaining dielectric region 50.In an embodiment, the thickness T5 of remaining dielectric region 50 is greater than about 0.1 μm.Next, implement to inject the bottom arriving opening 60, thus form drain electrode pick-up area 62, wherein, drain electrode pick-up area 62 can be heavily doped n-type area.When implementing to inject, photoresist (not shown) blanket p-type tagma 52, p-type body pick-up area 54 and source electrode pick-up area 56 can be passed through.Alternatively, after formation opening 60, also form source electrode pick-up area 56, thus source electrode pick-up area 56 and drain electrode pick-up area 62 can be formed simultaneously.
Figure 13 shows the formation of the remainder of power MOSFET 100.In an embodiment, opening 60 is filled with electric conducting material, such as, and tungsten and tungsten alloy, and the plug of generation is called dark conductive plug 64, this dark conductive plug is embedded in dielectric region 50/34.The formation of dark conductive plug 64 can comprise: by filled with conductive material in opening 60, and implement CMP, thus remove too much electric conducting material.Figure 13 further illustrates the manifold formation relevant to power MOSFET 100, and this part comprises silicide area 66, contact plug 68 and interlayer dielectric (ILD) 70.
In the power MOSFET 100 generated, by DDD district 32 and drain electrode pick-up area 62 buried in well region 22/ substrate 20, and the end face 62A of the end face 32A in DDD district 32 and drain electrode pick-up area 62 is lower than the end face of p-type body pick-up area 54 and source electrode pick-up area 56 and bottom surface.In addition, the end face 32A in DDD the district 32 and end face 62A of drain electrode pick-up area 62 is also lower than end face (this end face is the interface between p-type body district 52 and top regions 54 and 56) and the bottom surface 52A in p-type body district 52.Therefore, between source electrode pick-up area 56 and drain electrode pick-up area 62, the major part of the drain-source current I of flowing is the vertical direction vertical with the surperficial 20A (Fig. 1) of substrate 20.In addition, drain electrode pick-up area 62 is connected to dark conductive plug 64, and this dark conductive plug is formed in the below of the end face of well region 22 (substrate 22).Dark conductive plug 64 to be positioned at further below contact plug 68 and to be connected to this contact plug, and wherein, this contact plug is formed in the top face of substrate 20.
Gate oxide 45 extends in vertical direction, and the part being in the well region 22 between DDD district 32 and p-type body district 52 also forms the interface 72 with oxide region 34, and wherein, this interface 72 also extends in vertical direction.P-type body district 52 comprises the part on the relative both sides of raceway groove 30 and the part on the relative both sides of dark conductive plug 64 with each in source electrode pick-up area 56.Have at power MOSFET 100 in the embodiment of the single channel structure comprising single drain electrode, in the vertical view of Figure 13, gate electrode 46 can form the ring around dark conductive plug 64, and each in source electrode pick-up area 56, p-type body district 52 and p-type body pick-up area 54 can form the ring that maybe cannot be formed around dark conductive plug 64.
Although the embodiment shown in Fig. 1 to Figure 13 provides the method forming N-shaped power MOSFET, but it will be understood by those skilled in the art that, the instruction provided easily for the formation of p-type power MOSFET, wherein, by reverse for the conduction type of respective area 22,32,52,54,56 and 62.Figure 14 shows p-type power MOSFET 200, wherein, and mark respective area.Similar substantially with shown in Fig. 1 to Figure 13 of the formation process of p-type power MOSFET 200.
By using embodiment, the MOSFET100 (Figure 13) of generation and MOSFET200 (Figure 14) is for having the accurate vertical MOSFET of vertical gate oxide and vertical gate electrode.Therefore, significantly reduce cell gap, and can increasing power MOSFET density and do not lose corresponding puncture voltage BVdss and conducting resistance Ron.
According to embodiment, a kind of MOSFET comprises Semiconductor substrate, this Semiconductor substrate has end face, is arranged in the tagma of the first conduction type of Semiconductor substrate and double-diffused drain electrode (DDD) district, and the end face in this double-diffused drain electrode district is lower than the bottom surface in tagma.Second conduction type in DDD district is contrary with the first conduction type.The gate electrode that MOSFET is comprised gate oxide further and kept apart by this gate oxide and tagma.A part for gate oxide and a part for gate electrode are positioned at the below of the end face in tagma.
According to other embodiments, a kind of MOSFET comprises the raceway groove extended to from the end face of Semiconductor substrate Semiconductor substrate.Gate electrode is from the end face of Semiconductor substrate to downward-extension, and wherein, gate electrode is arranged in raceway groove.Tagma is arranged in Semiconductor substrate, and wherein, tagma is the first conduction type.Gate oxide is between tagma and the end face of gate electrode, and wherein, gate oxide is disposed vertically on the direction vertical with the end face of Semiconductor substrate.The DDD district of the second conduction type is lower than tagma, and this second conduction type is contrary with the first conduction type.
According to other embodiment, a kind of method comprises: form raceway groove, this raceway groove extends to Semiconductor substrate from the end face of Semiconductor substrate, and to be formed in the DDD district of the first conduction type in Semiconductor substrate and below raceway groove.First oxide region is formed in channels, and wherein, the first oxide region comprises the sidewall portion of the base section being positioned at trench bottom place and the side-walls being positioned at raceway groove.The top in sidewall portion is lower than the end face of Semiconductor substrate.Gate oxide is formed as the top in the sidewall portion extending downwardly into the first oxide region from the end face of Semiconductor substrate.Gate electrode is formed on the sidewall in the sidewall of gate oxide and the sidewall portion of the first oxide region.Form tagma, the end face of the contiguous Semiconductor substrate in this tagma, wherein, tagma is the second conduction type, and the second conduction type is contrary with the first conduction type.
Although describe in detail the present invention and advantage thereof, should be appreciated that, when not deviating from purport of the present invention and the scope of claims restriction, various different change can have been made, replaced and change.And, the scope of the application be not limited in describe in this specification technique, machine, manufacture, material component, device, method and step specific embodiment.Should understand as those of ordinary skill in the art, pass through the present invention, existing or Future Development for perform with according to the substantially identical function of described corresponding embodiment of the present invention or obtain the technique of basic identical result, machine, manufacture, material component, device, method or step can be used according to the present invention.Therefore, claims should be included in the scope of such technique, machine, manufacture, material component, device, method or step.In addition, every bar claim forms independent embodiment, and the combination of multiple claim and embodiment within the scope of the invention.

Claims (18)

1. a semiconductor device, comprising:
Mos field effect transistor MOSFET comprises:
Semiconductor substrate, comprises end face;
Tagma, has the first conduction type, is arranged in described Semiconductor substrate;
Double-diffused drain electrode DDD district, has end face, and described end face is lower than the bottom surface in described tagma, and wherein, described DDD district is the second conduction type, and described second conduction type is contrary with described first conduction type;
Dielectric region, be formed as ring with around and contact dark conductive plug, described dark conductive plug extends in described Semiconductor substrate;
Gate electrode, be formed as ring with around and contact described dielectric region, wherein, the end face in described DDD district is lower than the bottom of described gate electrode;
Gate oxide, be formed as ring with around and contact described gate electrode; And
Described gate electrode, by described gate oxide and described tagma spaced apart, wherein, a part for described gate oxide and a part for described gate electrode are positioned at the below of the described end face in described tagma.
2. semiconductor device according to claim 1, wherein, the bottom of described gate oxide is lower than the bottom surface in described tagma.
3. semiconductor device according to claim 1, wherein, described gate electrode comprises top and is positioned at the bottom of described below an upper section, wherein, spaced first spacing of forefield in described top and described tagma, described first spacing equals the thickness of described gate electrode, and wherein, spaced second spacing of forefield of described bottom and described Semiconductor substrate, described second spacing is greater than described first spacing.
4. semiconductor device according to claim 1, comprises further: described dark conductive plug extends downwardly into described DDD district from the horizontal plane flushed with the top of described gate electrode.
5. semiconductor device according to claim 4, wherein, described gate electrode comprises two parts, is positioned at the horizontal plane place identical with a part for described dark conductive plug, and wherein, described two parts are positioned at the relative both sides of described dark conductive plug.
6. semiconductor device according to claim 1, comprises further:
The source electrode pick-up area of described second conduction type; And
The body pick-up area of described first conduction type, wherein, described source electrode pick-up area and described body pick-up area extend to described Semiconductor substrate from the end face of described Semiconductor substrate.
7. a semiconductor device, comprising:
Mos field effect transistor MOSFET, comprising:
Raceway groove, extends to described Semiconductor substrate from the end face of Semiconductor substrate;
Gate electrode, from the described end face of described Semiconductor substrate to downward-extension, wherein, described gate electrode is arranged in described raceway groove;
Tagma, is arranged in described Semiconductor substrate, and wherein, described tagma is the first conduction type;
Gate oxide, between described tagma and the top of described gate electrode, wherein, described gate oxide is disposed vertically on the direction vertical with the end face of described Semiconductor substrate; And
Double-diffused drain electrode DDD district is the second conduction type, and described second conduction type is contrary with described first conduction type, wherein, the end face in described DDD district lower than the bottom surface in described tagma,
Dark conductive plug, extends downwardly into described DDD district from the top of described raceway groove,
Wherein, the first dielectric region, be formed as ring with around and contact described dark conductive plug;
Described gate electrode, be formed as ring with around and contact described first dielectric region;
Described gate oxide, be formed as ring with around and contact described gate electrode.
8. semiconductor device according to claim 7, wherein, described gate oxide has the first thickness, and wherein, described gate electrode comprises further: bottom, lower than described top, and wherein, described bottom is kept apart by the forefield of dielectric region and described Semiconductor substrate, and described dielectric region has the second thickness, and described second thickness is greater than described first thickness.
9. semiconductor device according to claim 8, wherein, the whole bottom of described gate electrode is lower than whole tagma.
10. semiconductor device according to claim 7, wherein, described gate electrode comprises two parts, is positioned at the horizontal plane place identical with a part for described dark conductive plug, and wherein, described two parts are positioned at the relative both sides of described dark conductive plug.
11. semiconductor device according to claim 7, comprise further: the drain electrode pick-up area of described second conduction type, are arranged in described DDD district, and wherein, described drain electrode pick-up area to be positioned at immediately below described dark conductive plug and to be electrically connected with described dark conductive plug.
The formation method of 12. 1 kinds of semiconductor device, comprising:
Form raceway groove, described raceway groove extends to described Semiconductor substrate from the end face of Semiconductor substrate;
The double-diffused drain electrode DDD district of the first conduction type to be formed in described Semiconductor substrate and below described raceway groove;
First oxide region is formed in described raceway groove, wherein, described first oxide region comprises: the sidewall portion of the base section being positioned at the bottom place of described raceway groove and the side-walls that is positioned at described raceway groove, and wherein, and the top in described sidewall portion is lower than the end face of described Semiconductor substrate;
Form gate oxide, described gate oxide extends downwardly into the top in the described sidewall portion of described first oxide region from the end face of described Semiconductor substrate;
On sidewall gate electrode being formed in described gate oxide and on the sidewall in the described sidewall portion of described first oxide region; And
Form tagma, the end face of the contiguous described Semiconductor substrate in described tagma, wherein, described tagma is the second conduction type, and described second conduction type is contrary with described first conduction type, and the end face in described DDD district is lower than the bottom surface in described tagma;
Wherein, described gate oxide is formed as ring with around described gate electrode, described gate electrode be formed as ring with around and contact dielectric region, described dielectric region be formed as ring with around and contact dark conductive plug, described dark conductive plug extends downwardly into described DDD district from the top of described raceway groove.
The formation method of 13. semiconductor device according to claim 12, comprises further:
After the step forming described gate electrode, in the remainder of described raceway groove, fill the second oxide region;
Etch described second oxide region, thus form opening, wherein, exposed the end face in described DDD district by described opening;
Inject described DDD district by described opening, thus form drain electrode pick-up area; And
Fill described dark conductive plug in said opening.
The formation method of 14. semiconductor device according to claim 13, comprises further: top face contact plug being formed in described Semiconductor substrate, and wherein, described contact plug is electrically connected with described dark conductive plug.
The formation method of 15. semiconductor device according to claim 12, wherein, the step forming described first oxide region comprises:
Fill oxide in the bottom of described raceway groove;
Distance piece is formed in above described oxide with on the sidewall of described raceway groove; And
Use described distance piece as oxide described in mask etching, wherein, the remainder of described oxide forms described first oxide region.
The formation method of 16. semiconductor device according to claim 12, wherein, the step forming described gate oxide comprises thermal oxidation.
The formation method of 17. semiconductor device according to claim 12, wherein, the step forming described gate electrode comprises:
Form gate electrode layer, described gate electrode layer comprises:
Part I, is positioned at the outside of described raceway groove;
Part II, on the sidewall being positioned at described gate oxide and on the sidewall in the sidewall portion of described first oxide region; And
Part III, is positioned at the bottom place of described raceway groove; And
Etch described gate electrode layer, thus form described gate electrode, wherein, remove the described Part I of described gate electrode layer and described Part III, and retain the described Part II of described gate electrode layer, thus form described gate electrode.
The formation method of 18. semiconductor device according to claim 12, comprise further: form source electrode pick-up area, the end face of contiguous described Semiconductor substrate, wherein, described source electrode pick-up area is the first conduction type, and wherein, described source electrode pick-up area comprises two parts, is positioned at the relative both sides of described raceway groove.
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