CN103022147A - Array substrate, preparation method of array substrate, thin film transistor and display device - Google Patents
Array substrate, preparation method of array substrate, thin film transistor and display device Download PDFInfo
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- CN103022147A CN103022147A CN2012105262730A CN201210526273A CN103022147A CN 103022147 A CN103022147 A CN 103022147A CN 2012105262730 A CN2012105262730 A CN 2012105262730A CN 201210526273 A CN201210526273 A CN 201210526273A CN 103022147 A CN103022147 A CN 103022147A
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Abstract
The invention discloses a thin film transistor. The thin film transistor comprises a source-drain electrode, an active layer, a gate insulation layer and a gate electrode which are sequentially formed, the active layer is prepared by microcrystalline silicon, a crystallization process is not required when the microcrystalline silicon is used for forming the active layer, and the preparing process is simple; simultaneously, field effect mobility ratios of the active layer formed by the microcrystalline silicon is higher than that of an active layer in an amorphous silicon thin film transistor (TFT) structure, influences of a hatching layer on a current path between a source electrode and a drain electrode can be reduced by means of a top gate type thin film transistor structure, therefore, the drive capability of the thin film transistor with the active layer formed by the microcrystalline silicon is high. The invention further provides a thin film transistor array substrate with the thin film transistor, a preparation method of the thin film transistor array substrate and a display device with the thin film transistor array substrate.
Description
Technical field
The present invention relates to the Display Technique field, particularly a kind of array base palte and preparation method thereof, thin-film transistor and display unit.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) has the characteristics such as volume is little, low in energy consumption, radiationless, has occupied leading position in current flat panel display market.In TFT-LCD, high performance thin-film transistor is the Primary Component of whole TFT-LCD, in the existing market, adopt in the thin-film transistor amorphous silicon deposition crystallization such as a-Si to form as the active layer of active switch device, there are some intrinsic problems in the active layer that adopts the amorphous silicon deposition crystallization to form, and is lower such as mobility more, less stable etc., limited further developing of TFT-LCD, the especially application in the models such as high-resolution, current drives, problem is then more outstanding.Low temperature polycrystalline silicon (LTPSpoly-Si) can address this problem, but which kind of crystallization process no matter it adopt, and all is two step crystallization methods, and complex process brings deficiency also for its practical application.
Summary of the invention
An object of the present invention is to provide a kind of thin-film transistor, the preparation technology of this thin-film transistor is simple, and has preferably driving force.
Another object of the present invention provides a kind of transistorized thin-film transistor array base-plate of said film that has, and the preparation technology of this thin-film transistor array base-plate is simple, and driven nature is good.
The present invention also provides a kind of preparation method of said film transistor (TFT) array substrate, and its active layer material does not need crystallization, and preparation technology is simple.
The present invention also provides a kind of display unit with said film transistor (TFT) array substrate.
For achieving the above object, the invention provides following technical scheme:
A kind of top gate type thin film transistor comprises the source-drain electrode, active layer, gate insulation layer and the grid that form successively, and described active layer is prepared from by microcrystal silicon.
The present invention also provides a kind of thin-film transistor array base-plate, comprises underlay substrate and the source-drain electrode, active layer, gate insulation layer and the grid that form successively, and described active layer is prepared from by microcrystal silicon.
Preferably, also comprise:
Be prepared from by Single Walled Carbon Nanotube, and be positioned at nesa coating on the described underlay substrate; Described source-drain electrode is positioned on the described nesa coating.
Preferably, also comprise: pixel electrode, described pixel electrode is connected with drain electrode, and is formed by described nesa coating.
The invention provides a kind of preparation method of said film transistor (TFT) array substrate, comprising:
Form the figure of source-drain electrode at underlay substrate;
Form active layer pattern at the source-drain electrode figure, be positioned at the gate insulation layer figure on the described active layer figure and be positioned at gate patterns on the gate insulation layer figure, described active layer is prepared by the microcrystal silicon material.
Preferably, describedly form active layer pattern at the source-drain electrode figure, be arranged in the gate insulation layer figure on the described active layer figure and be positioned at gate patterns on the gate insulation layer figure, described active layer figure, gate insulation layer figure, gate patterns are finished by a composition technique.
Preferably, describedly form active layer pattern at the source-drain electrode figure, be arranged in the gate insulation layer figure on the described active layer figure and be positioned at gate patterns on the gate insulation layer figure, specifically comprise:
Utilize magnetron sputtering deposition semiconductor layer microcrystal silicon at the source-drain electrode figure, and on described semiconductor layer microcrystal silicon sputtering sedimentation gate insulation material layer, and on the gate insulation material layer sputtering sedimentation grid metal level;
Apply one deck photoresist at the grid metal level, and with grey or half-tone mask plate photoresist is carried out exposure imaging, and carry out the etching first time, form active layer and the gate insulation layer of predetermined pattern, through behind the cineration technics, the grid metal level is carried out the etching second time, form grid.
Preferably, after forming grid, also comprise:
Form the passivation layer figure at described gate patterns.
Preferably, form the passivation layer figure at described gate patterns, specifically comprise:
Utilize PECVD deposition layer of passivation material;
Apply one deck photoresist in layer of passivation material, use mask plate that photoresist is carried out exposure imaging;
Layer of passivation material is carried out the etching first time, draw grid;
Then carry out etching gate insulation layer and the active layer second time, draw data wire, form the passivation layer figure.
Preferably, form at underlay substrate before the figure of source-drain electrode, also comprise:
Adopt volume to volume coating roll to roll technique at the transparency conducting layer of underlay substrate deposition Single Walled Carbon Nanotube material.
Preferably, in the described formation source-drain electrode figure, the composition technique of source-drain electrode comprises:
Metal level at source-drain electrode applies one deck photoresist:
And with grey or half-tone mask plate photoresist is carried out exposure imaging;
Carry out the etching first time, form the source-drain electrode figure;
Carry out cineration technics, photoresist that will be corresponding with the pixel unit area of tft array substrate is removed;
Carry out the etching second time, with the transparency conducting layer etching certain thickness of pixel electrode area;
Source electrode and photoresist lift off corresponding to drain electrode with source-drain electrode.
The present invention also provides a kind of display unit, and any thin-film transistor array base-plate that provides in the technique scheme is provided.
Thin-film transistor provided by the invention comprises the source-drain electrode, active layer, gate insulation layer and the grid that form successively, and described active layer is prepared from by microcrystal silicon.
In the said film transistor, the generating material of its active layer is microcrystal silicon, and microcrystal silicon is as a kind of crystalline silicon, both had the large-area Direct precipitation ability of traditional amorphous silicon low temperature, have the preparation technology compatible with it, therefore need not to carry out crystallization process when forming active layer, preparation technology is simple; Simultaneously, the field-effect mobility of the active layer that microcrystal silicon forms is higher than the active layer in the amorphous silicon film transistor, and the thin-film transistor of top gate type can reduce hatching layer to the impact of the current path between the source-drain electrode, therefore, the driving force of the thin-film transistor of employing microcrystal silicon formation active layer is higher.
In addition, also has good stability with this thin-film transistor with Crystallized Silicon formation active layer.
The present invention also provides a kind of thin-film transistor array base-plate, comprises underlay substrate and the source-drain electrode, active layer, gate insulation layer and the grid that form successively, and described active layer is prepared from by microcrystal silicon.
Because above-mentioned microcrystal silicon need not to carry out crystallization process when forming active layer, preparation technology is simple; Simultaneously, the field-effect mobility of the active layer that microcrystal silicon forms is higher than the active layer in the amorphous silicon film transistor, and therefore, the driving force of the thin-film transistor of employing microcrystal silicon formation active layer is higher.
So the preparation technology of thin-film transistor array base-plate provided by the invention is simple, and driven nature is good.
In further technical scheme, thin-film transistor array base-plate provided by the invention also comprises:
Be prepared from by Single Walled Carbon Nanotube, and be positioned at nesa coating on the described underlay substrate; Described source-drain electrode is positioned on the described nesa coating.Single Walled Carbon Nanotube has excellent conductivity, light transmission and flexibility, and then can increase flexibility and the conducting function of thin-film transistor in the array base palte, thereby can improve the performance of array base palte.
Further, thin-film transistor array base-plate also comprises: pixel electrode, described pixel electrode is connected with drain electrode, and is formed by the nesa coating that Single Walled Carbon Nanotube consists of.The figure of the figure of source-drain electrode and nesa coating (being pixel electrode) is realized by a composition technique, can be simplified further the preparation technology of said film transistor (TFT) array substrate.
The present invention also provides a kind of preparation method of said film transistor (TFT) array substrate, comprising:
Form the figure of source-drain electrode;
Form active layer pattern at the source-drain electrode figure, be positioned at the gate insulation layer figure on the described active layer figure and be positioned at gate patterns on the gate insulation layer figure, described active layer is prepared by the microcrystal silicon material.
Among the preparation technology of said film transistor (TFT) array substrate, microcrystal silicon is from begin to grow into the structural change process that grows up to complete microcrystal silicon layer, grow first be the hatching layer of one deck structural disorder, then a transition region is arranged, finally grow a comparatively complete microcrystal silicon layer, the present invention adopts the top gate type structure can reduce hatching layer to the impact of the current path between the source-drain electrode, because microcrystal silicon need not crystallization process when forming active layer, can simplify the preparation technology of thin-film transistor array base-plate.
The present invention also provides a kind of display unit with said film transistor (TFT) array substrate, and this display unit driven nature is good.
Description of drawings
Fig. 1 is the structural representation of thin-film transistor array base-plate provided by the invention;
Fig. 2 is thin-film transistor array base-plate preparation method's provided by the invention flow chart;
Fig. 3 is the principle schematic that forms source-drain electrode and nesa coating among the thin-film transistor array base-plate preparation method provided by the invention;
Fig. 4 is the principle schematic that forms active layer, grid among the thin-film transistor array base-plate preparation method provided by the invention;
Fig. 5 is deposit passivation layer and draw data wire and the principle schematic of grid among the thin-film transistor array base-plate preparation method provided by the invention;
Fig. 6 is deposit passivation layer shown in Figure 5 and draws data wire and the end view of the principle schematic of grid.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Embodiment one
Thin-film transistor provided by the invention comprises the source-drain electrode 7, active layer 3, gate insulation layer 6 and the grid 1 that form successively, as shown in Figure 1; Wherein, active layer 3 is prepared from by microcrystal silicon.
In the said film transistor, the generating material of its active layer 3 is microcrystal silicon, microcrystal silicon is as a kind of crystalline silicon, both had the large-area Direct precipitation ability of traditional amorphous silicon low temperature, have the preparation technology compatible with it, therefore need not to carry out crystallization process when forming active layer 3, preparation technology is simple; Simultaneously, the field-effect mobility of the active layer 3 that microcrystal silicon forms is higher than the active layer in the amorphous silicon film transistor, and therefore, the driving force of the thin-film transistor of employing microcrystal silicon formation active layer is higher.
In addition, also has good stability with this thin-film transistor with Crystallized Silicon formation active layer 3.
As shown in Figure 1, the present invention also provides a kind of thin-film transistor array base-plate, comprises underlay substrate 5 and the source-drain electrode 7, active layer 3, gate insulation layer 6 and the grid 1 that form successively, and above-mentioned active layer 3 is prepared from by microcrystal silicon.
Because above-mentioned microcrystal silicon need not to carry out crystallization process when forming active layer 3, preparation technology is simple; Simultaneously, the field-effect mobility of the active layer 3 that microcrystal silicon forms is higher than the active layer in the amorphous silicon film transistor, and therefore, the driving force of the thin-film transistor of use microcrystal silicon formation active layer is higher.
So the preparation technology of thin-film transistor array base-plate provided by the invention is simple, and driven nature is good.
In further technical scheme, thin-film transistor array base-plate provided by the invention also comprises:
Be prepared from by Single Walled Carbon Nanotube, and be positioned at nesa coating 4 on the underlay substrate; Source-drain electrode 7 is positioned on the nesa coating 4.Single Walled Carbon Nanotube has excellent conductivity, light transmission and flexibility, and then can increase flexibility and the conducting function of thin-film transistor in the array base palte, thereby can improve the performance of array base palte.
Further, thin-film transistor array base-plate also comprises: pixel electrode, pixel electrode is connected with the drain electrode of source-drain electrode 7, and is formed by the nesa coating 4 that Single Walled Carbon Nanotube consists of.The figure of source-drain electrode 7 and nesa coating 4(are pixel electrode) figure realize by composition technique, can simplify further the preparation technology of said film transistor (TFT) array substrate.
As shown in Figure 2, the present invention also provides a kind of preparation method of said film transistor (TFT) array substrate, comprising:
Step S201: the figure that forms source-drain electrode 7 at underlay substrate;
Step S202: form active layer 3 figures at source-drain electrode 7 figures, be positioned at gate insulation layer 6 figures on active layer 3 figures and be positioned at grid 1 figure on gate insulation layer 6 figures, active layer 3 is prepared by the microcrystal silicon material.
Among the preparation technology of said film transistor (TFT) array substrate, microcrystal silicon is from begin to grow into the structural change process that grows up to complete microcrystal silicon layer, grow first be the hatching layer of one deck structural disorder, then a transition region is arranged, finally grow a comparatively complete microcrystal silicon layer, the present invention adopts the top gate type structure, can reduce hatching layer to the impact of the current path between the source-drain electrode, because microcrystal silicon need not crystallization process when forming active layer, can simplify the preparation technology of thin-film transistor array base-plate.
For further simplifying the preparation method of said film transistor (TFT) array substrate, above-mentioned figure at the active layer 3 that source-drain electrode 7 figures form, be arranged in gate insulation layer 6 figures on the figure of active layer 3 and be positioned at grid 1 figure on gate insulation layer 6 figures, the figure of active layer 3, gate insulation layer 6 figures, grid 1 figure are finished by a composition technique.
Particularly, the above-mentioned figure that forms active layer 3 figures, is arranged in gate insulation layer 6 figures on active layer 3 figures and is positioned at the grid 1 on gate insulation layer 6 figures at source-drain electrode 7 figures specifically comprises:
Figure at source-drain electrode 7 utilizes magnetron sputtering deposition semiconductor layer microcrystal silicon 31, and on semiconductor layer microcrystal silicon 31 sputtering sedimentation gate insulation material layer 61, and on gate insulation material layer 61 sputtering sedimentation grid metal level 11; Shown in a among Fig. 4.
Apply one deck photoresist at grid metal level 11, and with grey or half-tone mask plate photoresist 8 being carried out exposure imaging, the photoresist 8 that obtains after the exposure imaging and carries out the etching first time shown in b among Fig. 4, form active layer 3 and the gate insulation layer 6 of predetermined pattern, shown in c among Fig. 4; Through behind the cineration technics, grid metal level 11 is carried out the etching second time, form grid 1, shown in d among Fig. 4.
Wherein, the coating of photoresist 8 can be adopted the modes such as spin coating mode or roller coating.
Certainly, after forming grid 1, the preparation method of said film transistor (TFT) array substrate also comprises:
Figure at the grid 1 that forms forms the passivation layer figure.
Particularly, the figure that forms passivation layer at the figure of grid 1 specifically comprises:
Utilize PECVD deposition layer of passivation material 2, shown in a among a among Fig. 5 and Fig. 6;
Apply one deck photoresist (not shown) in layer of passivation material 2, use mask plate that photoresist is carried out exposure imaging;
Layer of passivation material 2 is carried out the etching first time, draw grid 1, shown in b among b among Fig. 5 and Fig. 6;
Then carry out etching gate insulation layer 6 and active layer 3 second time, draw data wire, form the passivation layer figure, shown in c among c among Fig. 5 and Fig. 6.
Particularly, in step S201, before underlay substrate forms the figure of source-drain electrode, also comprise:
Adopt volume to volume (roll to roll) coating process at the transparency conducting layer 41 of underlay substrate 5 deposition Single Walled Carbon Nanotube materials, shown in a among Fig. 3.Single Walled Carbon Nanotube has excellent conductivity, light transmission and flexibility, and then can increase flexibility and the conducting function of thin-film transistor in the array base palte, thereby can improve the performance of array base palte.
Particularly, for further simplifying the preparation technology of thin-film transistor array base-plate, among the said film transistor (TFT) array substrate preparation method, the figure of the figure of source-drain electrode 7 and ELD 4 adopts a composition technique to finish, concrete, in the above-mentioned formation source-drain electrode figure, the composition technique of source-drain electrode comprises:
And with grey or half-tone mask plate photoresist 8 is carried out exposure imaging, shown in b among Fig. 3;
Carry out the etching first time, form the source-drain electrode figure;
Carry out cineration technics, photoresist 8 that will be corresponding with the pixel unit area of thin-film transistor array base-plate is removed;
Carry out the etching second time, with the transparency conducting layer 41 etching certain thickness of pixel electrode area;
Source electrode and the photoresist 8 corresponding to drain electrode of source-drain electrode are peeled off, finally obtained the figure of source-drain electrode 7 and the figure of nesa coating 4, the final graphics that obtains is shown in c among Fig. 3, and the nesa coating 4 of this moment can be used as pixel electrode.
In like manner, the coating of photoresist 8 can be adopted the modes such as spin coating mode or roller coating.
The figure of source-drain electrode 7 and nesa coating 4(are pixel electrode) figure realize by composition technique, can simplify further the preparation technology of said film transistor (TFT) array substrate.
Preferably, be 200nm at the thickness of the transparency conducting layer 41 of underlay substrate 5 deposition, metal level 71 thickness of sputtering sedimentation are 200 ~ 400nm, the thickness of the transparent conductive film 4 that forms of etching is 50nm for the second time.The thickness of transparent conductive film 4 is 50nm, and the thickness of source-drain electrode 7 is the thickness of metal level 71, can be 200nm, 230nm, 250nm, 300nm, 350nm, 380nm and 400nm.
And form in the technical process of source-drain electrode 7 and transparent conductive film 4, the deposition materials of the metal level 71 that transparency conducting layer 41 deposits above can have multiple choices, such as copper, aluminium, molybdenum or titanium etc.
In the optional technical scheme, in the technique that forms active layer 3, grid 1 and grid line, use active layer 3 thickness of microcrystal silicon deposition of material to be 50nm.
And in the technique that forms active layer 3, grid 1 and grid line, the deposition materials of gate insulation layer 6 can have multiple choices, as being Al
2O
3, AlN or SiO2, SiNx etc.
Alternatively, the deposition materials of above-mentioned grid metal level 11 also can have multiple choices, as being copper, aluminium, molybdenum or titanium etc.
In the preferred implementation, deposit passivation layer and draw data wire and the technique of grid 1 in, the thickness of the passivation layer of deposition is 200 ~ 400nm.
The present invention also provides a kind of display unit, and the thin-film transistor array base-plate that provides in the arbitrary execution mode that provides in the technique scheme is provided this display unit, and this display unit driven nature is good.
Obviously, those skilled in the art can carry out various changes and modification to the embodiment of the invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. a top gate type thin film transistor comprises the source-drain electrode, active layer, gate insulation layer and the grid that form successively, it is characterized in that, described active layer is prepared from by microcrystal silicon.
2. a thin-film transistor array base-plate comprises underlay substrate and the source-drain electrode, active layer, gate insulation layer and the grid that form successively, it is characterized in that, described active layer is prepared from by microcrystal silicon.
3. thin-film transistor array base-plate according to claim 2 is characterized in that, also comprises:
Be prepared from by Single Walled Carbon Nanotube, and be positioned at nesa coating on the described underlay substrate; Described source-drain electrode is positioned on the described nesa coating.
4. thin-film transistor array base-plate according to claim 3 is characterized in that, also comprises: pixel electrode, described pixel electrode is connected with drain electrode, and is formed by described nesa coating.
5. the preparation method of a thin-film transistor array base-plate is characterized in that, comprising:
Form the figure of source-drain electrode at underlay substrate;
Form active layer pattern at the source-drain electrode figure, be positioned at the gate insulation layer figure on the described active layer figure and be positioned at gate patterns on the gate insulation layer figure, described active layer is prepared by the microcrystal silicon material.
6. preparation method according to claim 5, it is characterized in that, describedly form active layer pattern at the source-drain electrode figure, be arranged in the gate insulation layer figure on the described active layer figure and be positioned at gate patterns on the gate insulation layer figure, described active layer figure, gate insulation layer figure, gate patterns are finished by a composition technique.
7. preparation method according to claim 6 is characterized in that, describedly forms active layer pattern at the source-drain electrode figure, is arranged in the gate insulation layer figure on the described active layer figure and is positioned at gate patterns on the gate insulation layer figure, specifically comprises:
Utilize magnetron sputtering deposition semiconductor layer microcrystal silicon at the source-drain electrode figure, and on described semiconductor layer microcrystal silicon sputtering sedimentation gate insulation material layer, and on the gate insulation material layer sputtering sedimentation grid metal level;
Apply one deck photoresist at the grid metal level, and with grey or half-tone mask plate photoresist is carried out exposure imaging, and carry out the etching first time, form active layer and the gate insulation layer of predetermined pattern, through behind the cineration technics, the grid metal level is carried out the etching second time, form grid.
8. preparation method according to claim 6 is characterized in that, after forming grid, also comprises:
Form the passivation layer figure at described gate patterns.
9. preparation method according to claim 8 is characterized in that, forms the passivation layer figure at described gate patterns, specifically comprises:
Utilize PECVD deposition layer of passivation material;
Apply one deck photoresist in layer of passivation material, use mask plate that photoresist is carried out exposure imaging;
Layer of passivation material is carried out the etching first time, draw grid;
Then carry out etching gate insulation layer and the active layer second time, draw data wire, form the passivation layer figure.
10. each described preparation method is characterized in that according to claim 5 ~ 9, forms at underlay substrate before the figure of source-drain electrode, also comprises:
Adopt the volume to volume coating process at the transparency conducting layer of underlay substrate deposition Single Walled Carbon Nanotube material.
11. preparation method according to claim 10 is characterized in that, in the described formation source-drain electrode figure, the composition technique of source-drain electrode comprises:
Metal level at source-drain electrode applies one deck photoresist:
And with grey or half-tone mask plate photoresist is carried out exposure imaging;
Carry out the etching first time, form the source-drain electrode figure;
Carry out cineration technics, photoresist that will be corresponding with the pixel unit area of tft array substrate is removed;
Carry out the etching second time, with the transparency conducting layer etching certain thickness of pixel electrode area;
Source electrode and photoresist lift off corresponding to drain electrode with source-drain electrode.
12. a display unit is characterized in that, comprises arbitrary described thin-film transistor array base-plate such as claim 2-4.
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| CN108598093A (en) * | 2018-05-24 | 2018-09-28 | 京东方科技集团股份有限公司 | Manufacturing method, array substrate and the display panel of array substrate |
| CN111864069A (en) * | 2019-04-26 | 2020-10-30 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method thereof and display device |
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| CN102629585A (en) * | 2011-11-17 | 2012-08-08 | 京东方科技集团股份有限公司 | Display device, thin film transistor, array substrate and manufacturing method thereof |
| CN102646714A (en) * | 2011-05-16 | 2012-08-22 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and preparation method thereof |
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Application publication date: 20130403 |