CN103066047A - Lead frame strip and packaging method for semiconductor packing - Google Patents
Lead frame strip and packaging method for semiconductor packing Download PDFInfo
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- CN103066047A CN103066047A CN201210585689XA CN201210585689A CN103066047A CN 103066047 A CN103066047 A CN 103066047A CN 201210585689X A CN201210585689X A CN 201210585689XA CN 201210585689 A CN201210585689 A CN 201210585689A CN 103066047 A CN103066047 A CN 103066047A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a lead frame strip and a packaging method for semiconductor packing. The lead frame strip comprises an outer frame, a plurality of connecting supports, a plurality of lead frame units and at least one through hole portion. Each lead support unit is composed of a chip seat, at least one support strip and a plurality of pins which are arranged at intervals. The support strip is connected with the chip seat to the connecting supports, the pins are connected with the connecting supports, and the through portion is formed on the connecting supports which are connected between two adjacent lead frame units. By design of the through portion, burr phenomena that a cutter cuts the connecting supports can be reduced, and packing quality of a chip and process yield of a final finished product are effectively improved.
Description
Technical field
The invention relates to the manufacture method of a kind of conductive wire frame strip and encapsulation, particularly relevant for a kind of semiconductor-sealing-purpose conductive wire frame strip and method for packing.
Background technology
Now; semiconductor packaging is mainly to prevent that chip is subject to ambient temperature; the impact of moisture; and the pollution of assorted dirt; and provide electric connection between chip and the external circuit; therefore; in order to satisfy various package requirements; develop gradually the packaging structure of various different types; the silicon (chip) that is for example formed by semiconductor silicon wafer (wafer) cutting; utilize the appropriate ways such as routing (wire bonding) or projection (bumping); and select to be fixed on lead frame (leadframe) or the substrate (substrate); then recycle the colloid encapsulation and coat the protection silicon, so can finish the basic framework of semiconductor packaging structure.At present, in order to emphasize compact trend in response to consumption electronic products, adopt a kind of square surface non-exterior pin semiconductor packaging construction (QFN, Quad Flat No lead) encapsulation kenel, described square surface non-exterior pin semiconductor packaging construction (QFN, Quad Flat No lead) do not have outer pin, normally at a conductive wire frame strip (leadframe strip) several lead frame unit are set, then simultaneously several chips are fixed on the chip carrier of lead frame unit, routing is in conjunction with procedures such as (wire bonding) and sealings, unnecessary framework is removed in cutting more at last, in order to make simultaneously and finish the packaging structure that several have lead frame, wherein the mode by routing combination (wire bonding) is electrically connected to chip on the pin of conductive wire frame strip, shorter signal bang path can be arranged, thereby have faster signal transmission speed.
Yet, described square surface non-exterior pin semiconductor packaging construction (QFN, Quad Flat No lead) in the process of encapsulation, separate each lead frame unit and must laterally reach longitudinally cutting action at conductive wire frame strip, because semiconductor all is to adopt the high-density pin spacing now, and described conductive wire frame strip is copper alloy, in described cutting action, utilize cutter cutting meeting to produce burr (bur) at conductive wire frame strip, make two the adjacent leads Yin Maoci contact on the conductive wire frame strip and cause the situation of product short-circuit failure, thereby have a strong impact on the package quality of chip and the process rate of final finished.
Therefore, be necessary to provide a kind of semiconductor-sealing-purpose conductive wire frame strip, to solve the existing problem of prior art.
Summary of the invention
In view of this, the invention provides a kind of semiconductor-sealing-purpose conductive wire frame strip, to solve in the cutting process after encapsulation, cutting action causes the problem of product short-circuit failure at conductive wire frame strip generation burr.
Main purpose of the present invention is to provide a kind of semiconductor-sealing-purpose conductive wire frame strip, it can be by forming through-hole section in connection bracket, to reduce the cutter cutting burr phenomena that connection bracket was produced, relatively avoid two adjacent pin Yin Maoci contacts and cause the risk of product short-circuit failure.
Secondary objective of the present invention is to provide a kind of semiconductor-sealing-purpose conductive wire frame strip, it can be by forming through-hole section in connection bracket, to reduce the cutter cutting burr phenomena that connection bracket was produced, can effectively promote the process rate of chip package quality and final finished.
For reaching aforementioned purpose of the present invention, one embodiment of the invention provides a kind of semiconductor-sealing-purpose conductive wire frame strip, wherein said semiconductor-sealing-purpose conductive wire frame strip comprises a housing, several connection brackets, several lead frame unit and at least one through-hole section, described connection bracket is staggered in the scope of described housing, described lead frame unit is arranged in the space of described connection bracket definition, each lead frame unit comprises a chip carrier, at least one support bar and several spaced pins, described support bar connects described chip carrier to described connection bracket, described pin is connected in described connection bracket, and described through-hole section is formed on the connection bracket between two adjacent lead frame unit of described connection at least.
Moreover, another embodiment of the present invention provides a kind of semiconductor-sealing-purpose conductive wire frame strip, wherein said semiconductor-sealing-purpose conductive wire frame strip comprises a housing, several connection brackets, several lead frame unit and at least one through-hole section, described connection bracket is staggered in the scope of described housing, described lead frame unit is arranged in the space of described connection bracket definition, each lead frame unit comprises several spaced pins, described pin is connected in described connection bracket, and described through-hole section is formed on the connection bracket between described two adjacent lead frame unit at least.
In addition, further embodiment of this invention provides a kind of method for packing, and wherein said manufacture method comprises step: purchase a conductive wire frame strip, described conductive wire frame strip comprises a housing, several connection brackets, is staggered in the scope of described housing; And several lead frame unit, being arranged in the space of described connection bracket definition, each lead frame unit comprises: several pins are connected in described connection bracket; At least one through-hole section is formed on two connection brackets between the adjacent described lead frame unit at least; Several chips are separately fixed on the described lead frame unit; Be electrically connected described pin and chip with several conducting elements; Described conductive wire frame strip is positioned in the mould, and the filling colloid coats described chip; Cut each connection bracket is disconnected, make two adjacent lead frame unit separately.
According to above-mentioned semiconductor-sealing-purpose conductive wire frame strip and method for packing, in the cutting process after encapsulation, the present invention is by forming through-hole section in described connection bracket, can reduce the burr phenomena that cutter cutting connection bracket produces, relatively avoid two adjacent pin Yin Maoci contacts and cause the risk of product short-circuit failure, can effectively promote the process rate of chip package quality and final finished.
Description of drawings
Fig. 1 is the top view of one embodiment of the invention semiconductor-sealing-purpose conductive wire frame strip.
Fig. 2 is the cutaway view of Fig. 1 embodiment semiconductor-sealing-purpose conductive wire frame strip II-II of the present invention.
Figure 1A to 1D is the top view of other form of through-hole section of Fig. 1 embodiment semiconductor-sealing-purpose conductive wire frame strip of the present invention.
Fig. 3 is the top view of another embodiment of the present invention semiconductor-sealing-purpose conductive wire frame strip.
Fig. 3 A is the top view of the another kind of form of Fig. 3 embodiment semiconductor-sealing-purpose conductive wire frame strip of the present invention.
Fig. 4 is the cutaway view of Fig. 3 A embodiment semiconductor-sealing-purpose conductive wire frame strip IV-IV.
Fig. 5 is the top view of further embodiment of this invention semiconductor-sealing-purpose conductive wire frame strip.
Fig. 6 is the cutaway view of Fig. 5 embodiment semiconductor-sealing-purpose conductive wire frame strip VI-VI.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to the specific embodiment of implementing in order to illustration the present invention.Moreover, the direction term that the present invention mentions, such as upper and lower, top, the end, front, rear, left and right, inside and outside, side, on every side, central authorities, level, laterally, vertically, vertically, axially, radially, the superiors or orlop etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to limit the present invention.
Please refer to shown in Fig. 1,2, one embodiment of the invention provides a kind of semiconductor-sealing-purpose conductive wire frame strip 100 can be applied in square surface non-exterior pin semiconductor packaging construction (QFN, Quad Flat No lead), and utilize a metallic plate to be made, described metallic plate can be selected from the metal of various tool satisfactory electrical conductivities, such as copper, iron, aluminium, nickel, zinc or its alloy etc.Described semiconductor-sealing-purpose conductive wire frame strip 100 comprises a housing 1, several connection brackets 2, several lead frame unit 3 and several through-hole section 21, and the present invention will be in the detail structure, assembled relation and the operation principles thereof that hereinafter describe one by one described each element of embodiment in detail.
Described connection bracket 2 is staggered in the scope of described housing 1, described lead frame unit 3 is arranged in the space 20 of described connection bracket 2 definition, each lead frame unit 3 comprises a chip carrier 31, several support bars 32 and several spaced pins 33, as shown in Figure 1, the support bar 32 of each lead frame unit 3 is four, two connection brackets 2 that connect respectively described chip carrier 31 both sides, make described support bar 32 from described chip carrier 31 to described connection bracket 2, but described support bar 32 also can only arrange one, in order to support on the described chip carrier 31, in addition, described pin 33 is connected in described connection bracket 2, be that the pin 33 of a lead frame unit 3 is respectively extended respectively in each connection bracket 2 both sides, described through-hole section 21 is formed on the connection bracket 2 between two adjacent lead frame unit 3 of described connection, in this enforcement, described through-hole section 21 is single long slot bore, described long slot bore refers to a perforation, the size of described perforation on the length direction of the connection bracket 2 at its place is greater than the size on the length direction of the connection bracket 2 at vertical its place of described perforation.Described long slot bore can have any shape, and is the strip, ellipse of curved edge or irregularly shaped etc. such as rectangle, two ends, and described long slot bore is between the pin 33 of two lead frame unit 3.
In addition, in other embodiments of the invention, shown in Figure 1A, described through-hole section 21 also can be two (or more than two) spaced long slot bores; Or, as shown in Figure 1B, described through-hole section 21 ' is formed at least described connection bracket 2 and connects on the position of described pin 33, and be several spaced short slotted eyes, described short slotted eye refers to a perforation, the size of described perforation on the length direction of the connection bracket 2 at its place is less than or equal to the size on the length direction of connection bracket 2 at vertical its place of described perforation.Described short slotted eye can have any shape, for example circle, square, rectangle or other shapes; And shown in Fig. 1 C, described through-hole section 21 is a long slot bore, and described through-hole section 21 is the concavo-convex spaced long slot bore in a border; Moreover shown in Fig. 1 D, described through-hole section 21,21 ' is respectively staggered spaced two long slot bores and a short slotted eye.Described long slot bore refers to a perforation, and the size of described perforation on the length direction of the connection bracket 2 at its place is greater than the size on the length direction of the connection bracket 2 at vertical its place of described perforation.The shape of described long slot bore can have any shape, and is the strip, ellipse of curved edge or irregularly shaped etc. such as rectangle, two ends.Described short slotted eye refers to a perforation, and the size of described perforation on the length direction of the connection bracket 2 at its place is less than or equal to the size on the length direction of connection bracket 2 at vertical its place of described perforation.Described short slotted eye can have any shape, for example circle, square, rectangle or other shapes.
As mentioned above, in the cutting process after encapsulation, separate each lead frame unit 3 and must carry out cutting action in the connection bracket 2 of metal or alloy first, and the present invention is by described through-hole section 21,21 ' is the design of long slot bore or short slotted eye, can reduce cutter at the area of described connection bracket 2 cuttings, thereby reduce cutter and cut the burr phenomena that connection bracket 2 produces, relatively avoid two adjacent pins 33 to cause the risk of product short-circuit failure because of the burr contact, can effectively promote the process rate of chip package quality and final finished, in addition, described long slot bore (cutting out continuous larger area at the connection bracket length direction) is used in the situation of the wider width of described connection bracket 2, the formation of described long slot bore can not affect the bulk strength of described semiconductor-sealing-purpose conductive wire frame strip 100, described short slotted eye (cutting out the area at interval at the connection bracket length direction) is used in the narrower situation of width of described connection bracket 2, and the formation of described short slotted eye can be played the effect of the bulk strength of as far as possible avoiding affecting described semiconductor-sealing-purpose conductive wire frame strip 100.And, specific design according to described semiconductor-sealing-purpose conductive wire frame strip 100, described long slot bore and described short slotted eye reasonably can be distributed, to reach to greatest extent burr phenomena when reducing cutting and not affect the bulk strength of described semiconductor-sealing-purpose conductive wire frame strip 100.Moreover the through-hole section on the connection bracket between upper each lead frame unit of same described semiconductor-sealing-purpose conductive wire frame strip 100 can be that identical design is arranged, and also can be that different designs is arranged.
Please refer to shown in Fig. 3 and the 3A, the semiconductor-sealing-purpose conductive wire frame strip 100 of another embodiment of the present invention is similar in appearance to Fig. 1 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of the present embodiment is: described lead frame unit 3 comprises several pins, described pin comprises the first pin 33 and several the second pins 33 ', described the first pin 33 is different from the length of the second pin 33 ', and arrangement interlaced with each other and being connected on the corresponding connection bracket 2.
As mentioned above, at the chip of encapsulation in the fixing and electric connection process, the chip carrier 31 of described lead frame unit 3 is to provide one or several chips 4 fixing, then utilizes routing in conjunction with bonding wire (not illustrating) juncture of (wirebonding); Or such as Fig. 3 A, the projection 41 (bump that utilize flip-chip 4 (flipchip) shown in Figure 4, Fig. 3 A is illustrated among the figure with the dotted line ball) combination, described chip 4 and described the first pin 33 and the second pin 33 ' are electrically connected, by the design different from the length of the second pin 33 ' of described the first pin 33, can improve the tie point space of electric connection, and then can increase the closeness of the tie point of electric connection, thereby can further improve the quantity of described the first pin 33 and the second pin 33 '.
The described semiconductor-sealing-purpose conductive wire frame strip 100 of above embodiment can be applied in square surface non-exterior pin semiconductor packaging construction (QFN, Quad Flat No lead), in addition, this semiconductor-sealing-purpose conductive wire frame strip with through-hole section design can be useful in any non-exterior pin semiconductor packaging construction equally, be not limited to the square surface non-exterior pin semiconductor packaging construction, also go for both sides and have the semiconductor packaging structure of pin, for example little profile non-exterior pin semiconductor packaging construction (SON, Small Outline Nolead), perhaps on one side, three limits have the non-exterior pin semiconductor packaging construction of pin.As long as the semiconductor packaging structure without outer pin need to cut processing procedure, the semiconductor-sealing-purpose conductive wire frame strip that this kind has the through-hole section design all plays the burr phenomena that prevents or reduce generation when cutting equally.
Please refer to shown in Figure 5, the semiconductor-sealing-purpose conductive wire frame strip 100 of further embodiment of this invention is similar in appearance to Fig. 1 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of the present embodiment is: described semiconductor-sealing-purpose conductive wire frame strip 100 only comprises a housing 1, several connection brackets 2 and several lead frame unit 3, described connection bracket 2 is staggered in the scope of described housing 1, described lead frame unit 3 is arranged in the space 20 of described connection bracket 2 definition, each lead frame unit 3 comprises several spaced pins, described pin comprises the first pin 33 and the second pin 33 ', but do not have chip carrier, described the first pin 33 and the second pin 33 ' are connected in described connection bracket 2, the length of described the first pin 33 and the second pin 33 ' is different, and arrangement interlaced with each other, described connection bracket 2 has a through-hole section 21, described through-hole section 21 is a long slot bore, and described through-hole section 21 is the concavo-convex spaced long slot bore in a border.
As mentioned above, in the cutting process after encapsulation, the present embodiment can reduce the burr phenomena that cutter cutting connection bracket 2 produces, and then effectively promote the package quality of described chip 4 and the process rate of final finished by the design of the concavo-convex spaced long slot bore in described border.
Please cooperate with reference to Fig. 1, it shows the semiconductor-sealing-purpose conductive wire frame strip 100 according to one embodiment of the invention.The manufacture method of the semiconductor-sealing-purpose conductive wire frame strip 100 of the present embodiment can comprise the steps:
Purchase a conductive wire frame strip 100, wherein said conductive wire frame strip comprises a housing 1, several connection brackets 2 and several lead frame unit 3, described connection bracket 2 is staggered in the scope of described housing 1, described lead frame unit 3 is arranged in the space 20 of described connection bracket 2 definition, each lead frame unit 3 comprises a chip carrier 31, several spaced pins, described pin comprises the first pin 33, described the first pin 33 is connected in described connection bracket 2, wherein said connection bracket 2 has a through-hole section 21, is formed on described connection bracket 2 and connects on the position of described the first pin 33.
Several chips (not illustrating) are separately fixed on the chip carrier 31 of described lead frame unit 3, then utilize the mode of routing combination (wire bonding) with the first pin 33 and chip as described in several conducting elements (such as bonding wire) electric connection.
Described conductive wire frame strip 100 is positioned in the mould (not illustrating), and filling colloid (not illustrating) coats described chip, and described colloid is solidified, then utilize a cutter (not illustrating) that each connection bracket 2 is cut along described through-hole section 21 longitudinal breakings, two adjacent lead frame unit 3 are separated, namely can finish semi-conductive packaging operation.
In addition, if use Fig. 5,6 conductive wire frame strip 100, then be that a chip 4 directly is fixed on described the first pin 33 and the second pin 33 ', and first, second pin 33 as described in being electrically connected with several conducting elements (such as wire or projection), 33 ' and as described in chip 4, again described conductive wire frame strip 100 is positioned in the mould (not illustrating), and the filling colloid coats described chip 4 and conducting element, at last each connection bracket 2 is cut along described through-hole section 21 longitudinal breakings, two adjacent lead frame unit 3 are separated.
As mentioned above, in the cutting process after encapsulation, the present invention is by forming through-hole section 21 in described connection bracket 2, can reduce the burr phenomena that cutter cutting connection bracket 2 produces, relatively avoid two the first adjacent pins 33 to contact the risk that causes the product short-circuit failure because of burr, can effectively promote the process rate of chip package quality and final finished.
The present invention is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present invention.Must be pointed out that, published embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in the scope of the present invention.
Claims (11)
1. semiconductor-sealing-purpose conductive wire frame strip, it is characterized in that: described semiconductor-sealing-purpose conductive wire frame strip comprises:
One housing;
Several connection brackets are staggered in the scope of described housing; And
Several lead frame unit are arranged in the space of described connection bracket definition, and each lead frame unit comprises: a chip carrier; At least one support bar connects described chip carrier to described connection bracket; And several spaced pins, described pin is connected in described connection bracket;
At least one through-hole section is formed on the connection bracket between two adjacent lead frame unit of described connection at least.
2. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 1, it is characterized in that: several through-hole section are formed on the connection bracket between any two adjacent described lead frame unit.
3. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 1 or 2, it is characterized in that: described through-hole section is at least one long slot bore.
4. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 1 or 2, it is characterized in that: described through-hole section is at least one short slotted eye.
5. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 4 is characterized in that, described short slotted eye has several, and is arranged between the corresponding pin of adjacent described two lead frame unit on the connection bracket.
6. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 1 or 2, it is characterized in that: described through-hole section is the combination of at least one long slot bore and at least one short slotted eye.
7. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 6 is characterized in that, described long slot bore and described short slotted eye are staggered.
8. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 1, it is characterized in that: described pin comprises several first pins and several second pins, described the first pin is different from the length of described the second pin, and arrangement interlaced with each other and being connected on the described connection bracket.
9. semiconductor-sealing-purpose conductive wire frame strip, it is characterized in that: described semiconductor-sealing-purpose conductive wire frame strip comprises:
One housing;
Several connection brackets are staggered in the scope of described housing; And
Several lead frame unit are arranged in the space of described connection bracket definition, and each lead frame unit comprises: several spaced pins, and described pin is connected in described connection bracket;
At least one through-hole section is formed on the connection bracket between described two adjacent lead frame unit at least.
10. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 9, it is characterized in that: described pin comprises several first pins and several second pins, described the first pin is different from the length of the second pin, and arrangement interlaced with each other and being connected on the described connection bracket.
11. a method for packing is characterized in that: described manufacture method comprises step:
Purchase a conductive wire frame strip, described conductive wire frame strip comprises a housing, several connection brackets, is staggered in the scope of described housing; And several lead frame unit, being arranged in the space of described connection bracket definition, each lead frame unit comprises: several pins are connected in described connection bracket; At least one through-hole section is formed on two connection brackets between the adjacent described lead frame unit at least;
Several chips are separately fixed on the described lead frame unit;
Be electrically connected described pin and chip with several conducting elements;
Described conductive wire frame strip is positioned in the mould, and the filling colloid coats described chip; And
Cut each connection bracket is disconnected, make two adjacent lead frame unit separately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210585689.XA CN103066047B (en) | 2012-12-28 | 2012-12-28 | Semiconductor-sealing-purpose conductive wire frame strip and method for packing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210585689.XA CN103066047B (en) | 2012-12-28 | 2012-12-28 | Semiconductor-sealing-purpose conductive wire frame strip and method for packing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103066047A true CN103066047A (en) | 2013-04-24 |
| CN103066047B CN103066047B (en) | 2016-09-07 |
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| CN201210585689.XA Expired - Fee Related CN103066047B (en) | 2012-12-28 | 2012-12-28 | Semiconductor-sealing-purpose conductive wire frame strip and method for packing |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584456A (en) * | 2020-05-08 | 2020-08-25 | 武汉华星光电半导体显示技术有限公司 | Chip on film |
| US11373943B2 (en) | 2020-05-08 | 2022-06-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Flip-chip film |
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2012
- 2012-12-28 CN CN201210585689.XA patent/CN103066047B/en not_active Expired - Fee Related
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| CN202308051U (en) * | 2011-11-03 | 2012-07-04 | 广东德豪润达电气股份有限公司 | LED packaging support and LED device |
| CN203134784U (en) * | 2012-12-28 | 2013-08-14 | 日月光封装测试(上海)有限公司 | Lead frame strip for semiconductor packaging |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584456A (en) * | 2020-05-08 | 2020-08-25 | 武汉华星光电半导体显示技术有限公司 | Chip on film |
| US11373943B2 (en) | 2020-05-08 | 2022-06-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Flip-chip film |
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| CN103066047B (en) | 2016-09-07 |
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