CN103077051B - load processing circuit, method and system - Google Patents
load processing circuit, method and system Download PDFInfo
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- CN103077051B CN103077051B CN201210587299.6A CN201210587299A CN103077051B CN 103077051 B CN103077051 B CN 103077051B CN 201210587299 A CN201210587299 A CN 201210587299A CN 103077051 B CN103077051 B CN 103077051B
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Abstract
The embodiment of the invention provides a loading processing circuit, a method and a system. The loading processing circuit comprises a channel selection module, a first control module and a second control module, wherein the channel selection module is respectively connected with a controller, a JTAG slave node and storage equipment and is used for respectively connecting the controller or the JTAG slave node with the storage equipment when a reset signal in the JTAG slave node is low level or high level; the time sequence conversion module is respectively connected with the JTAG slave node and the channel selection module and is used for carrying out time sequence conversion processing on TMS signals output by the TMS interface in the JTAG slave node; and when the reset signal in the JTAG slave node is at a high level, outputting the TMS signal after the time sequence conversion processing to a low-level effective CS interface of the storage equipment. The embodiment of the invention can load the storage equipment according to the TDI signal and the TCK signal of the JTAG slave node and the TMS signal after the time sequence conversion processing.
Description
Technical field
The embodiment of the present invention relates to semiconductor technology, particularly relates to a kind of loading processing circuit, method and system.
Background technology
Joint test working group (Joint Test Action Group, is below abbreviated as JTAG) is mainly used in the boundary scan testing of circuit and the on-line system programming of programmable chip.External storage equipment is had at JTAG device, such as serial peripheral interface (Serial Peripheral Interface, below be abbreviated as SPI) device such as quick flashing (FLASH) memory device time, can be loaded memory device by the controller in scanning JTAG device.
In the process realizing the embodiment of the present invention, inventor to find in prior art when being loaded memory device by the controller in scanning JTAG device, need to scan each pin of JTAG device, and by controlling 0,1 sequence of each pin, complete the program loading procedure to such as SPI FLASH memory device, thus cause load time longer problem, reduce the efficiency of loading.
Summary of the invention
For the above-mentioned defect of prior art, the embodiment of the present invention provides a kind of loading processing circuit, method and system, to improve the efficiency of memory device being carried out to program loading.
Embodiment of the present invention first aspect is to provide a kind of loading processing circuit, it is characterized in that, comprising:
Channel selecting module, respectively with controller, JTAG is connected from node with memory device, for when described JTAG is low level from the reset signal that the Low level effective TRST interface node exports, is connected by described controller with described memory device;
Timing conversion module, be connected with described channel selecting module from node with described JTAG respectively, tms signal for exporting from the TMS interface node described JTAG carries out timing conversion process, obtain the tms signal after timing conversion process, wherein, the sequential of the signal that the sequential of the tms signal after described timing conversion process is corresponding with the Low level effective CS interface of described memory device is identical;
Described channel selecting module, also for when described reset signal is high level, disconnect the connection between described controller and described memory device, and described JTAG is inputed to the SI interface of described memory device, SCK interface and Low level effective CS interface from the TDI interface corresponding TDI signal node, described JTAG respectively from the corresponding tck signal of TCK interface node and the tms signal after described timing conversion process, carry out loading processing for described memory device according to the tms signal after TDI signal, tck signal and described timing conversion process.
In the implementation that the first is possible, described channel selecting module comprises:
One MUX, described first data input pin of a MUX is connected with the SCLK interface of described controller, second data input pin of a described MUX is connected from the TCK interface of node with described JTAG, the described output terminal of a MUX is connected with the SCK interface of described memory device, for realizing when described reset signal is low level, first data input pin of selection the one MUX is corresponding with the SCK interface of described memory device to be connected; When described reset signal is high level, second data input pin of selection the one MUX is corresponding with the SCK interface of described memory device to be connected;
2nd MUX, described first data input pin of the 2nd MUX is connected with the MOSI interface of described controller, second data input pin of described 2nd MUX is connected from the TDI interface of node with described JTAG, the described output terminal of the 2nd MUX is connected with the SI interface of described memory device, for realizing when described reset signal is low level, first data input pin of selection the 2nd MUX is corresponding with the SI interface of described memory device to be connected; When described reset signal is high level, second data input pin of selection the 2nd MUX is corresponding with the SI interface of described memory device to be connected;
3rd MUX, first data input pin of described 3rd MUX is connected with the Low level effective SS interface of described controller, second data input pin of described 3rd MUX with or the output terminal of door be connected, the output terminal of described 3rd MUX is connected with the Low level effective CS interface of described memory device, for realizing when described reset signal is low level, first data input pin of selection the 3rd MUX is corresponding with the Low level effective CS interface of described memory device to be connected; When described reset signal is high level, second data input pin of selection the 3rd MUX is corresponding with the Low level effective CS interface of described memory device to be connected.
In conjunction with the first possible implementation of first aspect, in the implementation that the second is possible, described timing conversion module comprises:
First d type flip flop, the D input end of described first d type flip flop is connected with described TMS interface, tck signal for exporting according to described TCK interface carries out timing conversion process to the tms signal that described TMS interface exports, and obtains the first tms signal, and is exported by described first tms signal;
Second d type flip flop, the D input end of described second d type flip flop is connected with the Q output terminal of described first d type flip flop, for described first tms signal that the Q output terminal receiving described first d type flip flop exports, the second tms signal that the Q output terminal obtaining described second d type flip flop exports, described second tms signal is that the tck signal that described second d type flip flop exports according to described TCK interface carries out the signal after timing conversion process to described first tms signal;
3d flip-flop, the D input end of described 3d flip-flop is connected with the Q output terminal of described second d type flip flop, for described second tms signal that the Q output terminal receiving described second d type flip flop exports, the 3rd tms signal that the Q output terminal obtaining described 3d flip-flop exports, described 3rd tms signal is that the tck signal that described 3d flip-flop exports according to described TCK interface carries out the signal after timing conversion process to described second tms signal;
Described or door, be connected with described 3rd MUX with the Q output terminal of described second d type flip flop, the Q output terminal of described 3d flip-flop respectively, for carrying out phase or process to described second tms signal and described 3rd tms signal, obtain the tms signal after described timing conversion process.
In conjunction with the first possible implementation of first aspect, in the implementation that the third is possible, described loading processing circuit is CPLD.
Embodiment of the present invention second aspect is to provide a kind of loading processing method, it is characterized in that, comprising:
Timing conversion process is carried out to the tms signal that JTAG exports from the TMS interface node, obtain the tms signal after timing conversion process, wherein, the sequential of the signal that the sequential of the tms signal after described timing conversion process is corresponding with the Low level effective CS interface of memory device is identical;
When described JTAG is high level from the reset signal that the Low level effective TRST interface node exports, connection between breaking controller and described memory device, and described JTAG is inputed to the SI interface of described memory device, SCK interface and Low level effective CS interface from the TDI interface corresponding TDI signal node, described JTAG respectively from the corresponding tck signal of TCK interface node and the tms signal after described timing conversion process, carry out loading processing for described memory device according to the tms signal after TDI signal, tck signal and described timing conversion process.
In the implementation that the first is possible, described timing conversion process is carried out to the tms signal that JTAG exports from the TMS interface node, obtains the tms signal after timing conversion process, comprising:
According to the tck signal that described TCK interface exports, timing conversion process is carried out to the tms signal that described JTAG exports from the TMS interface node, obtains the first tms signal;
According to the tck signal that described TCK interface exports, timing conversion process is carried out to described first tms signal, obtains the second tms signal;
According to the tck signal that described TCK interface exports, timing conversion process is carried out to described second tms signal, obtain the 3rd tms signal;
Phase or process are carried out to described two tms signals and described 3rd tms signal, obtains the tms signal after described timing conversion process.
In conjunction with the first possible implementation of second aspect, in the implementation that the second is possible, also comprise: when described JTAG is low level from the reset signal node, controller is connected with described memory device.
In conjunction with the implementation that the second of second aspect is possible, in the implementation that the third is possible, also comprise: when described JTAG becomes high level from the reset signal node from low level, disconnect the connection of described controller and described memory device.
The embodiment of the present invention third aspect is to provide a kind of loading processing system, comprise master control borad and business board, described business board comprises JTAG device, described JTAG device comprises the first of above-mentioned first aspect and first aspect may loading processing circuit according to any one of the implementation possible with the second, and described master control borad is connected by JTAG control bus with described business board.
Embodiment of the present invention fourth aspect is to provide a kind of loading processing system, comprise management board and business board, described business board comprises JTAG device, described JTAG device comprises the first of above-mentioned first aspect and first aspect may loading processing circuit according to any one of the implementation possible with the second, and described management board is connected by CAN with described business board.
Loading processing circuit, method and apparatus that the embodiment of the present invention provides, can realize utilizing JTAG Fast simulation SPI sequential by timing conversion module and channel selecting module, realize the rapid loading process to external storage equipment program, the problem that in prior art, the load time is long can be solved, the efficiency that program loads can be improved.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is loading processing circuit of the present invention based on the configuration diagram of JTAG system;
Fig. 2 is loading processing circuit of the present invention based on JTAG state transition diagram;
Fig. 3 is loading processing circuit of the present invention based on jtag instruction time diagram;
Fig. 4 is the structural representation of a loading processing circuit of the present invention embodiment;
Fig. 5 is the circuit theory diagrams of another embodiment of loading processing circuit of the present invention;
Fig. 6 is prior art SPI interface sequence schematic diagram;
Fig. 7 be existing JTAG sequential with SPI sequential compare schematic diagram;
What Fig. 8 was the present invention by the JTAG sequential after loading processing processing of circuit and SPI sequential compares schematic diagram;
Fig. 9 is the process flow diagram of a loading processing method of the present invention embodiment;
Figure 10 is the configuration diagram of a loading processing system of the present invention embodiment;
Figure 11 is the configuration diagram of another embodiment of loading processing system of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is loading processing circuit of the present invention based on the configuration diagram of JTAG system, as shown in Figure 1, this JTAG system comprises: the JTAG on the processor 111 on systematic master control board 11 and JTAG host node 112 and appliance services plate 12 is from node 121 and JTAG device 122.Various piece is that the jtag interface by each parts are arranged connects successively.Last JTAG device 122 can mount the loading of memory device 123 (such as: SPI FLASH) realization to memory device.
Concrete, processor 111 issues JTAG scan instruction by JTAG host node 112; On business board, JTAG is from node 121, for docking with the JTAG host node 112 on master control borad; The scan chain that JTAG exports from node 121, mounting JTAG device 122, circuit JTAG being carried out to loading processing from the signal of node 121 is comprised in JTAG device 122, memory device 123 such as SPI FLASH memory is articulated on the SPI interface of the JTAG device 122 on business board 12, the main circuit of described loading processing will complete the conversion of JTAG signal sequence to memory device input signal sequential such as SPI sequential, makes to carry out program loading to it by system JTAG.
Wherein, jtag interface signal has 5, is respectively test clock TCK (Test Clock) interface, test data input TDI (Test Data Input) interface, test data exports TDO (Test Data Output) interface, test pattern selects TMS (Test Mode Select) interface and reset signal/TRST (Test Reset) interface.
Below in conjunction with Fig. 2 and Fig. 3, the implementation procedure of the program scanning chain of JTAG system in above-mentioned Fig. 1 is described in detail.
Fig. 2 is loading processing circuit of the present invention based on JTAG state transition diagram, as shown in Figure 2, order register (instruction register, IR) is used for preserving an instruction on the current scan chain performed.When an execution instruction, first it is got in data register (data register, DR) from internal memory, and then be sent to IR.During test TCK synchronous under, first determine that test pattern is order or data by TMS, this order or data are tested subsequently from TDI/TDO test data input/test data output interface, exiting of test pattern is realized by TMS again after completing, the State Transferring track of thick black line for being scan instruction register (scan IR, SIR) in Fig. 2.
When having reset or/TRST Low level effective period of jtag interface chip, state that jtag test process is in " test logic reset ", under effective tck clock excitation, if TMS=1, state retains, otherwise state that state switches to " test/idle ", this state switches in JTAG scanning initial phase and completes, and can send jtag instruction or data after completing.Test mode transition diagram has two similar branches: one is the relevant branch of DR, comprises " selecting DR scanning ", " loading DR ", " displacement DR ", " exiting 1DR ", " suspending DR ", " exiting 2DR ", " upgrading DR " state; Another is the relevant branch of IR, comprises " selecting IR scanning ", " loading IR ", " displacement IR ", " exiting 1IR ", " suspending IR ", " exiting 2IR ", " upgrading IR " state.To send jtag instruction, first TMS=0 several cycle is kept to ensure to be in " test/idle " state, be enter " displacement IR " state after going through " select DR scanning ", " selecting IR scanning ", " loading IR " state under the control of 0 or 1 subsequently at TMS, now TDI can input command word; TMS=0 in input command word process, state that state remains " displacement IR ", gets back to " test/idle " state after completing input command word under the control of TMS after going through " exiting 1IR ", " upgrading IR " state.
Fig. 3 is loading processing circuit of the present invention based on jtag instruction time diagram, as shown in Figure 3, JTAG adopts and performs serial vector format (Serial Vector Format, below be abbreviated as SVF) script realize instruction issuing, SVF is a kind of syntax gauge for illustration of high-rise IEEE 1149.1 (JTAG) bus operation.Above-mentioned jtag instruction refers in particular to the instruction in SVF specification.In Fig. 3/TRST is high always, represents that above-mentioned Fig. 2 is in the test scan stage." test logic reset ", " test/idle ", " selecting DR scanning " in " Test Logic/Reset ", " RunTest/ldle ", " SDS " " SIS " " CIR " " SIR " " EIR " " UIR " difference corresponding diagram 2 in Fig. 3, " selection IR scanning ", " loading IR ", " displacement IR ", " exiting 1IR ", " upgrading IR " state.There is shown the corresponding sequential of TCK, TMS, TDI, TDO under each state.
Fig. 4 is the structural representation of a loading processing circuit of the present invention embodiment, and in conjunction with JTAG system shown in above-mentioned Fig. 1, as shown in Figure 4, this loading processing circuit is arranged in JTAG device, and this circuit comprises: channel selecting module 401 and timing conversion module 402.Concrete, channel selecting module 401, respectively with controller, JTAG is connected from node with memory device, for when this JTAG is low level from the reset signal that the Low level effective TRST interface node exports, is connected by this controller with this memory device, timing conversion module 402, be connected with channel selecting module 401 from node with this JTAG respectively, tms signal for exporting from the TMS interface node this JTAG carries out timing conversion process, obtain the tms signal after timing conversion process, wherein, the sequential of the signal that the sequential of the tms signal after this timing conversion process is corresponding with the Low level effective CS interface of this memory device is identical, channel selecting module 401, also for when this reset signal is high level, disconnect the connection between this controller and this memory device, and by this JTAG from the corresponding TDI signal of the TDI interface node, this JTAG inputs to the SI interface of this memory device respectively from the tms signal after the corresponding tck signal of TCK interface node and this timing conversion process, SCK interface and Low level effective CS interface, for this memory device according to TDI signal, tms signal after tck signal and this timing conversion process carries out loading processing.
Preferably, described timing conversion module 402 can be programmable logic device (PLD), as CPLD (Complex Programmable Logic Device, CPLD) or similar hardware chip, the function of the timing conversion having realized corresponding signal can also be built with discrete component.
The present embodiment and loading procedure of the prior art are contrasted known, due to prior art use system JTAG by scanning monitor, SPI FLASH is loaded time, need to scan the complete JTAG chain of controller, in order to the output of control SPI interface or the input of acquisition SPI interface, namely the SPI interface signal adopting jtag instruction to control controller realizes the simulation that SPI loads sequential, each scanning can only realize a level saltus step, to be converted to example between TCK and SCK, SCK frequency=TCK frequency ÷ scans chain length ÷ 2.Because all are based on the clock of SCK in prior art loading procedure, therefore in prior art, between TCK to SCK, conversion efficiency is low, directly causes the low of loading efficiency.As supposed, the scanning chain length 500 of controller, sweep frequency 5MHz, SPI FLASH size to be loaded are 32Mb, every 2 scanning t test or export 1b, the time that then reading whole scan chain needs is: 500 × 2 × 32 ÷ 5=6400 ≈ second 1.78 hours, in addition, the write time is also longer than the reading time.And the present invention directly adopts the frequency of TCK to load, SCK frequency=TCK the frequency of Fast simulation, the amplitude of improved efficiency reaches the speed-up ratio of scanning chain length × 2, further, loading processing circuit of the present invention can under TCK loading frequency, realize the conversion (sequential of JTAG upper other signal with the sequential of its on SPI corresponding signal identical) of TMS sequential to/CS sequential, thus make the SPI FLASH time loading 32Mb be about 120 seconds, speed is compared in above-mentioned prior art and is loaded reading in example and each 1.78 hours of ablation process by scanning monitor, more than 100 times can be improved, greatly improve loading efficiency.
More preferred, the TDO signal that the MISO interface of controller and JTAG export from the SO interface that the TDO interface of node can receive memory device, and make controller and JTAG carry out shifting processing from node to this TDO signal respectively, to be tested to memory device by the TDO signal after shifting processing.
In the present embodiment, when using JTAG to simulate SPI interface sequence, controller and the JTAG isolation from the TMS interface node is realized by channel selecting module, be input in timing conversion module with the tms signal that JTAG is exported from the TMS interface node, and by timing conversion module, timing conversion process is carried out to this tms signal, identical with the sequential of the signal making the sequential of the tms signal after timing conversion process corresponding with the Low level effective CS interface in memory device.The embodiment of the present invention directly adopts the frequency of TCK to load, thus achieves the conversion of TMS sequential to/CS sequential fast, makes JTAG can Fast simulation SPI sequential, improves the efficiency that program loads.
Fig. 5 is the circuit theory diagrams of another embodiment of loading processing circuit of the present invention, and as shown in Figure 5, this loading processing circuit 50 comprises: channel selecting module 401 and timing conversion module 402, wherein, channel selecting module 401 can comprise multiple alternative data selector (Multiplexer, below be abbreviated as MUX), specifically comprise: a MUX 31, first data input pin of the one MUX 31 is connected with the clock sclk interface of controller 51, second data input pin of the one MUX 31 is connected from the TCK interface of node 121 with this JTAG, the output terminal of the one MUX 31 is connected with the SCK interface of this memory device 123, for realizing when this reset signal is low level, select that first data input pin of a MUX31 is corresponding with the SCK interface of this memory device 123 to be connected, when this reset signal is high level, second data input pin of selection the one MUX 31 is corresponding with the SCK interface of this memory device 123 to be connected,
2nd MUX 32, first data input pin of the 2nd MUX 32 is connected with MOSI (the Master Output Slave Input) interface of this controller 51, second data input pin of the 2nd MUX 32 is connected from the TDI interface of node 121 with this JTAG, the output terminal of the 2nd MUX 32 is connected with the SI interface of this memory device 123, for realizing when this reset signal is low level, first data input pin of selection the 2nd MUX 32 is corresponding with the SI interface of this memory device 123 to be connected; When this reset signal is high level, second data input pin of selection the 2nd MUX 32 is corresponding with the SI interface of this memory device 123 to be connected;
3rd MUX 33, first data input pin and the sheet of this controller 51 of the 3rd MUX 33 select Low level effective SS interface to be connected, second data input pin of the 3rd MUX 33 with or the output terminal of door 24 be connected, the output terminal of the 3rd MUX 33 is connected with the Low level effective CS interface of this memory device 123, for realizing when this reset signal is low level, first data input pin of selection the 3rd MUX 33 is corresponding with the Low level effective CS interface of this memory device 123 to be connected; When this reset signal is high level, second data input pin of selection the 3rd MUX 33 is corresponding with the Low level effective CS interface of this memory device 123 to be connected.Wherein, in Fig. 5, Low level effective SS interface represents with/SS, and Low level effective CS interface represents with/CS.
This timing conversion module 402 comprises:
First d type flip flop 21, the D input end of this first d type flip flop 21 is connected with this TMS interface, tck signal for exporting according to this TCK interface carries out timing conversion process to the tms signal that this TMS interface exports, and obtains the first tms signal, and is exported by this first tms signal;
Second d type flip flop 22, the D input end of this second d type flip flop 22 is connected with the Q output terminal of this first d type flip flop 21, for this first tms signal that the Q output terminal receiving this first d type flip flop 21 exports, the second tms signal that the Q output terminal obtaining this second d type flip flop 22 exports, this second tms signal is that the tck signal that this second d type flip flop 22 exports according to this TCK interface carries out the signal after timing conversion process to this first tms signal;
3d flip-flop 23, the D input end of this 3d flip-flop 23 is connected with the Q output terminal of this second d type flip flop 22, for this second tms signal that the Q output terminal receiving this second d type flip flop 22 exports, the 3rd tms signal that the Q output terminal obtaining this 3d flip-flop 23 exports, the 3rd tms signal is that the tck signal that this 3d flip-flop 23 exports according to this TCK interface carries out the signal after timing conversion process to this second tms signal;
Be somebody's turn to do or door 24, be connected with the 3rd MUX 33 with the Q output terminal of this second d type flip flop 22, the Q output terminal of this 3d flip-flop 23 respectively, for carrying out phase or process to this second tms signal and the 3rd tms signal, obtain the tms signal mutually or after process.It should be noted that, this phase or the tms signal after processing are the tms signal after above-mentioned timing conversion process.
MISO (the Master Input Slave Output) interface of this controller 51 is directly connected from the TDO interface of node 121 and the SO interface of memory device 123 with this JTAG.
In the present embodiment, Fig. 6 is prior art SPI interface sequence schematic diagram.General SPI FLASH interface signal has 4, be respectively serial input SI (Serial Input), Serial output SO (Serial Output), clock SCK (Serial Clock) and sheet choosing/CS (Chip Select, low effectively), SPI interface sequence as shown in Figure 5, wherein, CYCLE# is the clock signal of external crystal-controlled oscillation.To in SPI device read-write operation process, as clock polarity CPOL=0, SCK gives tacit consent to level is low, if now clock phase CPHA=0, MISO interface is in rising edge clock sampling input, MOSI interface exports data at clock falling edge, if CPHA=1, in clock falling edge sampling input, export data at rising edge clock; As CPOL=1, SCK gives tacit consent to level be high, if now CPHA=0, in clock falling edge sampling input, exports data at rising edge clock, if CPHA=1, in rising edge clock sampling input, in clock falling edge output data; Must retention tab choosing/CS signal be low level in SPI device read-write operation process, choose this SPI device for enable.
Fig. 7 be existing JTAG sequential with SPI sequential compare schematic diagram, what Fig. 8 was the present invention by the JTAG sequential after loading processing processing of circuit and SPI sequential compares schematic diagram, as shown in Figure 7, the first half is each signal sequence of JTAG, and Lower Half is each signal sequence of SPI.Identical with Fig. 3 of each Status Name of test scan stage " Test Logic/Reset " in Fig. 7 with Fig. 8, " Run Test/ldle ", " SDS " " SIS " " CIR " " SIR " " EIR " " UIR ".Investigate JTAG sequential and SPI sequential chart in Fig. 7, can be found both closely similar, as the CPOL=0 of SPI sequential and CPHA=0 time, except TMS cannot meet in sequential/timing requirements of CS except, the corresponding relation of other signal sequences is: TCK-SCK, TDI-MOSI, TDO-MISO, visible, to realize by the loading of jtag interface to SPI interface FLASH program, TMS in jtag interface is changed in sequential, make it with SPI interface /CS sequential is corresponding.Specifically the timing conversion module 402 of the embodiment of the present invention in above-mentioned Fig. 4 can be utilized exactly to realize, this timing conversion module 402, by the conversion of TMS sequential to/CS sequential, completes the object of JTAG Fast simulation SPI sequential.
The loading processing circuit of the present embodiment is that/TRST remains low level when JTAG does not initiate JTAG scan chain operation from node, and alternative data selector MUX chooses controller to be connected with SPI FLASH; When JTAG initiates JTAG scan chain operation from node ,/TRST draws high, and this Time Controller and SPI FLASH isolate.
Fig. 9 is the process flow diagram of a loading processing method of the present invention embodiment, and as shown in Figure 9, the method is the method that the invention described above loading processing circuit performs, and the method can comprise:
S901, to JTAG from node TMS interface export tms signal carry out timing conversion process, obtain the tms signal after timing conversion process, wherein, the sequential of the signal that the sequential of the tms signal after this timing conversion process is corresponding with the Low level effective CS interface of memory device is identical;
S902, this JTAG from node Low level effective TRST interface export reset signal be high level time, connection between breaking controller and this memory device, and this JTAG is inputed to the SI interface of this memory device, SCK interface and Low level effective CS interface from the TDI interface corresponding TDI signal node, this JTAG respectively from the corresponding tck signal of TCK interface node and the tms signal after this timing conversion process, carry out loading processing for this memory device according to the tms signal after TDI signal, tck signal and this timing conversion process.
The method of the present embodiment is the Low level effective CS interface sequence utilizing JTAG Fast simulation SPI memory device, can solve to memory device the problem that in prior art, the load time is long by the method, because when prior art uses system JTAG to be loaded SPI FLASH by scanning monitor, need to scan the complete JTAG chain of controller, in order to the output of control SPI interface or the input of acquisition SPI interface, therefore the load time is very long.And the method for the embodiment of the present invention is by carrying out timing conversion process to tms signal, obtain TMS transformation result, can realize TMS to SPI memory device /timing conversion of CS signal.Namely simulate SPI sequential with JTAG can load fast, realize the rapid loading process to external storage equipment program, the problem that in prior art, the load time is long can be solved, greatly can improve the efficiency that program loads.
Below the timing conversion process of the loading processing method of above-described embodiment is illustrated.
Composition graphs 5 and Fig. 8, further, carry out timing conversion process to the tms signal that JTAG exports from the TMS interface node in the method for above-described embodiment, obtain the tms signal after timing conversion process, comprising:
According to the tck signal that this TCK interface exports, timing conversion process is carried out to the tms signal that this JTAG exports from the TMS interface node, obtains the first tms signal;
According to the tck signal that this TCK interface exports, timing conversion process is carried out to this first tms signal, obtains the second tms signal;
According to the tck signal that this TCK interface exports, timing conversion process is carried out to this second tms signal, obtain the 3rd tms signal;
Phase or process are carried out to this second tms signal and the 3rd tms signal, obtains the tms signal mutually or after process.
Concrete, TMS changes as shown in Figure 8 to/CS signal sequence, and require that TMS negative edge time delay backward 2 is clapped, rising edge time delay backward 1 is clapped, and aligns with the negative edge of TCK.Realize the second d type flip flop 22 that this requirement can be triggered TMS by TCK negative edge and 3d flip-flop 23 time delay export after signal TMS2 and TMS3 phase maybe can obtain, previous with TCK rising edge trigger the first d type flip flop 21 for give TMS shaping, because of arrive logic input terminal TMS and TCK between phase place there is certain deviation, tms signal after shaping and TMS1 along and TCK negative edge between at least there is the interval of half clock period, no longer there is the deviation causing logic error, stable output can be obtained, by the tms signal of output after the 3rd MUX gating, can with SPI FLASH /CS signal is connected.So just achieve the process of JTAG sequential to SPI sequential rapid translating.
Further, the method for above-described embodiment can also comprise: when this JTAG is low level from the reset signal node, be connected by controller with this memory device.
The method of above-described embodiment can also comprise: this JTAG from the reset signal node for becoming high level from low level time, disconnect the connection of this controller and this memory device.
Concrete, by the control inputs of reset signal/TRST signal as the Enable Pin of channel selecting module, respectively to the { SCLK that controller and JTAG export from node, TCK}, { MOSI, TDI}, { Low level effective SS, TMS transformation result } carry out control selection, finally export SCK, the SI of JTAG from the signal of node to SPI FLASH interface end ,/CS signal, can be memory device and carry out program loading.
Figure 10 is the configuration diagram of a loading processing system of the present invention embodiment, as shown in Figure 10, this loading processing system, comprise master control borad 11 and business board 12, this business board 12 comprises JTAG device 122, this JTAG device 122 comprises the loading processing circuit 50 of the various embodiments described above, and this master control borad 11 is connected by JTAG control bus with this business board 12.
Concrete, the present embodiment application scenarios comprises two pieces of master control borads 11, and every block master control borad 11 has processor 111 and JTAG host node 112, both are connected by JTAG control bus, and processor 111 issues JTAG scan instruction by JTAG host node 112; The configurable polylith business board 12 of this system, each business board 12 has JTAG from node 121, for docking with the JTAG host node 111 on master control borad 11; JTAG goes out several scan chains from node 121, can mount multiple JTAG device 122 under every bar scan chain, and each scan chain also can be merged into a scan chain by chaining separately; Circuit JTAG being carried out to loading processing from the signal of node 121 in above-described embodiment is comprised in JTAG device 122, system JTAG between master control borad 11 to business board 12 connects the relation for one-to-many, can only set up scan channel sometime to the JTAG on single business board from node 121; Memory device 123 is articulated on the SPI interface of certain controller on business board as SPI FLASH memory, loads by system JTAG.
Processor on the present embodiment master control borad issues JTAG scan instruction by JTAG host node toward system jtag bus, chooses JTAG on certain business board also realize scanning from node and hang the loading of SPI FLASH device finishing service plate JTAG device.
Figure 11 is the configuration diagram of another embodiment of loading processing system of the present invention, as shown in figure 11, this loading processing system, comprise management board 41 and business board 42, this business board 42 comprises JTAG device 122, this JTAG device 122 comprises the loading processing circuit 50 of the various embodiments described above, and this management board 41 is connected by CAN with this business board 42.
Concrete, with the system class of above-mentioned Figure 10 embodiment seemingly, difference is had on forming unlike system hardware, system is with management board 41 in the present embodiment, use baseboard management controller (BaseboardManagement Controller, below be abbreviated as BMC) each business board of module management, management board 41 is provided with processor 411, BMC host node 412 and Ethernet interface Eth 413 and Universal Asynchronous Receive/transmission (Universal Asynchronous Receiver/Transceiver, is below abbreviated as UART) interface 414.In the present embodiment, processor 411 control BMC host node 412 on management board 41 is connected from node 421 by the BMC on backboard CANBUS (Controller Area Net-work Bus) bus and business board 42, BMC explains from node 421 and performs the instruction that BMC host node 412 sends to, data are two-way, existing BMC reports from node 421 to BMC host node 412, also has BMC host node 412 to be issued to BMC from node 421.BMC from node 421 go out quantity not wait jtag interface, be used for scanning the JTAG device 122 on business board 42, comprise the circuit 50 JTAG signal being carried out to loading processing in above-described embodiment in JTAG device 122, therefore use the online rapid loading that the system of the present embodiment can realize SPI FLASH on business board.
The system of the present embodiment, may be used for performing the technical scheme of loading processing Method and circuits embodiment provided by the present invention and possess corresponding functional module, it realizes principle and technique effect is similar, repeats no more herein.
In sum, loading processing circuit, method and apparatus that the embodiment of the present invention provides, obtain TMS transformation result by the timing conversion module of loading processing circuit, realizes TMS to the conversion of/CS signal; By the control inputs of reset signal/TRST signal as the Enable Pin of channel selecting module, carry out control to controller and JTAG from each signal that node exports respectively to select, finally export the signal of JTAG from the signal of node to storage device interface end, can be memory device and carry out program loading, the embodiment of the present invention can utilize JTAG Fast simulation SPI sequential, realize the rapid loading process to external storage equipment program, the problem that in prior art, the load time is long can be solved, the efficiency that program loads can be improved.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above each embodiment is only in order to illustrate the technical scheme of the embodiment of the present invention, be not intended to limit; Although be described in detail the embodiment of the present invention with reference to foregoing embodiments, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of each embodiment technical scheme of the embodiment of the present invention.
Claims (10)
1. a loading processing circuit, is characterized in that, comprising:
Channel selecting module, respectively with controller, JTAG is connected from node with memory device, for when described JTAG is low level from the reset signal that the Low level effective TRST interface node exports, is connected by described controller with described memory device;
Timing conversion module, be connected with described channel selecting module from node with described JTAG respectively, tms signal for exporting from the TMS interface node described JTAG carries out timing conversion process, obtain the tms signal after timing conversion process, wherein, the sequential of the signal that the sequential of the tms signal after described timing conversion process is corresponding with the Low level effective CS interface of described memory device is identical;
Described channel selecting module, also for when described reset signal is high level, disconnect the connection between described controller and described memory device, and described JTAG is inputed to the SI interface of described memory device, SCK interface and Low level effective CS interface from the TDI interface corresponding TDI signal node, described JTAG respectively from the corresponding tck signal of TCK interface node and the tms signal after described timing conversion process, carry out loading processing for described memory device according to the tms signal after TDI signal, tck signal and described timing conversion process.
2. circuit according to claim 1, is characterized in that, described channel selecting module comprises:
One MUX, described first data input pin of a MUX is connected with the SCLK interface of described controller, second data input pin of a described MUX is connected from the TCK interface of node with described JTAG, the described output terminal of a MUX is connected with the SCK interface of described memory device, for realizing when described reset signal is low level, first data input pin of selection the one MUX is corresponding with the SCK interface of described memory device to be connected; When described reset signal is high level, second data input pin of selection the one MUX is corresponding with the SCK interface of described memory device to be connected;
2nd MUX, described first data input pin of the 2nd MUX is connected with the MOSI interface of described controller, second data input pin of described 2nd MUX is connected from the TDI interface of node with described JTAG, the described output terminal of the 2nd MUX is connected with the SI interface of described memory device, for realizing when described reset signal is low level, first data input pin of selection the 2nd MUX is corresponding with the SI interface of described memory device to be connected; When described reset signal is high level, second data input pin of selection the 2nd MUX is corresponding with the SI interface of described memory device to be connected;
3rd MUX, first data input pin of described 3rd MUX is connected with the Low level effective SS interface of described controller, second data input pin of described 3rd MUX with or the output terminal of door be connected, the output terminal of described 3rd MUX is connected with the Low level effective CS interface of described memory device, for realizing when described reset signal is low level, first data input pin of selection the 3rd MUX is corresponding with the Low level effective CS interface of described memory device to be connected; When described reset signal is high level, second data input pin of selection the 3rd MUX is corresponding with the Low level effective CS interface of described memory device to be connected.
3. circuit according to claim 2, is characterized in that, described timing conversion module comprises:
First d type flip flop, the D input end of described first d type flip flop is connected with described TMS interface, tck signal for exporting according to described TCK interface carries out timing conversion process to the tms signal that described TMS interface exports, and obtains the first tms signal, and is exported by described first tms signal;
Second d type flip flop, the D input end of described second d type flip flop is connected with the Q output terminal of described first d type flip flop, for described first tms signal that the Q output terminal receiving described first d type flip flop exports, the second tms signal that the Q output terminal obtaining described second d type flip flop exports, described second tms signal is that the tck signal that described second d type flip flop exports according to described TCK interface carries out the signal after timing conversion process to described first tms signal;
3d flip-flop, the D input end of described 3d flip-flop is connected with the Q output terminal of described second d type flip flop, for described second tms signal that the Q output terminal receiving described second d type flip flop exports, the 3rd tms signal that the Q output terminal obtaining described 3d flip-flop exports, described 3rd tms signal is that the tck signal that described 3d flip-flop exports according to described TCK interface carries out the signal after timing conversion process to described second tms signal;
Described or door, be connected with described 3rd MUX with the Q output terminal of described second d type flip flop, the Q output terminal of described 3d flip-flop respectively, for carrying out phase or process to described second tms signal and described 3rd tms signal, obtain the tms signal after described timing conversion process.
4. circuit according to claim 2, is characterized in that, described loading processing circuit is CPLD.
5. a loading processing method, is characterized in that, comprising:
Timing conversion process is carried out to the tms signal that JTAG exports from the TMS interface node, obtain the tms signal after timing conversion process, wherein, the sequential of the signal that the sequential of the tms signal after described timing conversion process is corresponding with the Low level effective CS interface of memory device is identical;
When described JTAG is high level from the reset signal that the Low level effective TRST interface node exports, connection between breaking controller and described memory device, and described JTAG is inputed to the SI interface of described memory device, SCK interface and Low level effective CS interface from the TDI interface corresponding TDI signal node, described JTAG respectively from the corresponding tck signal of TCK interface node and the tms signal after described timing conversion process, carry out loading processing for described memory device according to the tms signal after TDI signal, tck signal and described timing conversion process.
6. method according to claim 5, is characterized in that, describedly carries out timing conversion process to the tms signal that JTAG exports from the TMS interface node, obtains the tms signal after timing conversion process, comprising:
According to the tck signal that described TCK interface exports, timing conversion process is carried out to the tms signal that described JTAG exports from the TMS interface node, obtains the first tms signal;
According to the tck signal that described TCK interface exports, timing conversion process is carried out to described first tms signal, obtains the second tms signal;
According to the tck signal that described TCK interface exports, timing conversion process is carried out to described second tms signal, obtain the 3rd tms signal;
Phase or process are carried out to described two tms signals and described 3rd tms signal, obtains the tms signal after described timing conversion process.
7. method according to claim 6, is characterized in that, also comprises: when described JTAG is low level from the reset signal node, be connected by controller with described memory device.
8. method according to claim 7, is characterized in that, also comprises: when described JTAG becomes high level from the reset signal node from low level, disconnect the connection of described controller and described memory device.
9. a loading processing system, comprise master control borad and business board, described business board comprises JTAG device, it is characterized in that, described JTAG device comprises the loading processing circuit described in any one of claim 1-3, and described master control borad is connected by JTAG control bus with described business board.
10. a loading processing system, comprise management board and business board, described business board comprises JTAG device, it is characterized in that, described JTAG device comprises the loading processing circuit described in any one of claim 1-3, and described management board is connected by CAN with described business board.
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