CN103078618B - Voltage switcher circuit - Google Patents
Voltage switcher circuit Download PDFInfo
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- CN103078618B CN103078618B CN201110329202.7A CN201110329202A CN103078618B CN 103078618 B CN103078618 B CN 103078618B CN 201110329202 A CN201110329202 A CN 201110329202A CN 103078618 B CN103078618 B CN 103078618B
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Abstract
A kind of voltage switcher circuit, utilize low-doped (Lightly Doped) PMOS transistor to bear high voltage stress in this voltage switcher circuit, nmos pass transistor is made to bear high voltage stress, due to and low-doped PMOS transistor is compatible with logical circuit processing procedure, therefore voltage switcher circuit can complete under logical circuit processing procedure.
Description
Technical field
The invention relates to a kind of voltage switcher circuit, and relate to one especially and utilize PMOS transistor to bear the voltage switcher circuit of high voltage stress (voltage stress).
Background technology
Please refer to Fig. 1, its illustrate is decoding circuit module in known as memory device (decode circuitmodule) schematic diagram.Decoding circuit module comprises high pressure decoding switched system (HV decode switchsystem) 110, switched system (LV decode switch system) 150 of decoding with a low pressure.
High pressure decoding switched system 110 comprises voltage switcher circuit 120,1 first voltage switcher circuit group 130 and a decoding unit 140.Voltage switcher circuit 120, according to control signal (EN), optionally exports the first voltage (HV) or the second voltage (MV) input voltage (VPP) as decoding unit 140.
Moreover the first voltage switcher circuit group 130 comprises N number of voltage switcher circuit, its circuit structure is same as above-mentioned voltage switcher circuit 120.First voltage switcher circuit group 130 is controlled by the address signal A<N-1:0> of N position, and according to the address signal A<N-1:0> of N position, produce the high voltage decode signal HVDEC<N-1:0> of N position and input decoding unit 140.
For example, when supposing the address signal A [N-1] of N-1 position for low level (L), the high voltage decode signal HVDEC [N-1] of N-1 position is the first voltage (HV); Otherwise when supposing the address signal A [N-1] of N-1 position for high level (H), the high voltage decode signal HVDEC [N-1] of N-1 position is the second voltage (MV).In like manner, in the first voltage switcher circuit group 130, the operating principle of other voltage switch is all identical, repeats no more.
After decoding unit 140 receives the high voltage decode signal HVDEC<N-1:0> of input voltage (VPP) and N position, can 2
nindividual array bus holding wire Array_bus<2
n– 1:0> produces different states, that is, opening (ON) or closed condition (OFF).Substantially, the operating principle not emphasis of the present invention of decoding unit 140, therefore its internal circuit and operating principle will be omitted.
Moreover low pressure decoding switched system 150 comprises the second voltage switcher circuit group 160.Second voltage switcher circuit group 160 comprises 2
nindividual voltage switcher circuit, its output is distinctly connected to 2
nindividual array bus holding wire Array_bus<2
non – 1:0>.And the second voltage switcher circuit group 160 is controlled by the address signal A<N-1:0> of N position and reads signal Read.Its operating principle is described below:
With the (2
n-1) strip array bus signal line Array_bus [2
n– 1] be example, when decoding unit 140 controls the (2
n-1) strip array bus signal line Array_bus [2
n– 1] for opening (ON) time, the (2
n-1) strip array bus signal line Array_bus [2
n– 1] on voltage be input voltage (VPP), now the second voltage switcher circuit group 160 can provide floating (floating) to the (2
n-1) strip array bus signal line Array_bus [2
n– 1].Moreover, when decoding unit 140 controls the (2
n-1) strip array bus signal line Array_bus [2
n– 1] for closed condition (OFF) time, the (2
n-1) strip array bus signal line Array_bus [2
n– 1] on voltage can be provided by the second voltage switcher circuit group 160, its according to address signal A<N-1:0> and read signal (read), may the (2
n-1) strip array bus signal line Array_bus [2
n– 1] on provide 0V or read voltage (VR).In like manner, the operating principle of other array bus holding wire connects identical, repeats no more.
In the processing procedure field of logical circuit, namely the voltage exceeding logic level more than 2 to 3 times can be considered high voltage.For example, when logic of propositions level is 2.5V, namely the voltage higher than more than 7V can be considered high voltage; When logic level is 3.3V, namely the voltage higher than more than 9V can be considered high voltage; When logic level is 5V, namely the voltage higher than more than 18V can be considered high voltage.
For decoding circuit module in memory in Fig. 1, its logic level is 5V, and the first voltage (HV) is 18V, and the second voltage (MV) is 10V.That is, in high voltage decode switched system 110, voltage switcher circuit 120 and the first switching circuit group 130 connect and can be connected to high voltage (the first voltage HV); In like manner, the voltage switcher circuit in the second voltage switcher circuit group 160, when particular state, also can receive high voltage (the first voltage HV).
In general, when logical circuit can receive high voltage (HV) in operation, this logical circuit cannot be compatible with traditional logical circuit processing procedure, and need to utilize special circuit processing procedure, and therefore Logic Circuit Design can more complicated and cost of manufacture can improve.In other words, the voltage switcher circuit in Fig. 1 cannot utilize existing logical circuit processing procedure, and it needs just can complete by special circuit manufacture procedure, therefore can improve cost of manufacture.
Therefore, utilize be compatible with logical circuit processing procedure to manufacture voltage switcher circuit be the present invention object for reaching.
Summary of the invention
The object of the invention is to propose a kind of voltage switcher circuit, utilize low-doped (Lightly Doped) PMOS transistor to bear high voltage stress in this voltage switcher circuit, and low-doped (LightlyDoped) PMOS transistor is compatible with logical circuit processing procedure, therefore voltage switcher circuit can complete under logical circuit processing procedure.
The invention relates to a kind of voltage switcher circuit, comprise: an output circuit, comprise one first PMOS transistor, source electrode and substrate are connected to a high voltage source, drain electrode is connected to the reversed-phase output of this voltage switcher circuit, and grid is connected to the output of this voltage switcher circuit; And, one second PMOS transistor, source electrode and substrate are connected to this high voltage source, the reversed-phase output that drain electrode is connected to the output of this voltage switcher circuit, grid is connected to this voltage switcher circuit; One first pressure drop control circuit, comprise one the 3rd PMOS transistor, substrate is connected to this high voltage source, and source electrode is connected to this reversed-phase output, and drain electrode is connected to a node e, and grid is connected to a reference voltage source; And, one the 4th PMOS transistor, substrate is connected to this high voltage source, and source electrode is connected to this output, and drain electrode is connected to a node f, and grid is connected to this reference voltage source; One second pressure drop control circuit, comprises one first nmos pass transistor, one second nmos pass transistor, one first bias control circuit and one second bias control circuit; Wherein, the drain electrode of this first nmos pass transistor is connected to the control end of this node e and this first bias control circuit, and grid is connected to the output of this first bias control circuit, and substrate and source electrode are connected to a node c; And, this second nmos pass transistor, drain electrode is connected to the control end of this node f and this second bias control circuit, and grid is connected to the output of this second bias control circuit, and substrate and source electrode are connected to a node d; One the 3rd pressure drop control circuit, comprises one the 3rd nmos pass transistor, and drain electrode is connected to this node c, grid is connected to a logic voltage source, substrate and source electrode and is connected to a node a; And, one the 4th nmos pass transistor, drain electrode is connected to this node d, grid is connected to this logic voltage source, substrate and source electrode and is connected to a node b; And an input circuit, comprise one the 5th nmos pass transistor, one the 6th nmos pass transistor, one the 3rd bias control circuit, with one the 4th bias control circuit; Wherein, the 5th nmos pass transistor, drain electrode is connected to the output of this node a and the 3rd bias control circuit, and grid is connected to the input of this voltage switcher circuit, and substrate and source electrode are connected to an earth terminal; And the 6th nmos pass transistor, drain electrode is connected to the output of this node b and the 4th bias control circuit, and grid is connected to the inverting input of this voltage switcher circuit, and substrate and source electrode are connected to this earth terminal.
The invention relates to a kind of voltage switcher circuit, the output of this voltage switcher circuit is connected to a bus signal line and this bus signal line can optionally provide an input voltage by a control circuit, comprise: one first nmos pass transistor, drain electrode is connected to the output of voltage switcher circuit, and source electrode and substrate are connected to a node b; One first bias control circuit, the control end of this first bias control circuit is connected to the output of this voltage switcher circuit, the input of this first bias control circuit is connected to the input of this voltage switcher circuit, and the output of this first bias control circuit is connected to this first nmos pass transistor grid; One second nmos pass transistor, drain electrode is connected to this node b, grid is connected to a logic voltage source, source electrode and substrate and is connected to a node a; One second bias control circuit, the control end of this second bias control circuit is connected to the input of this voltage switcher circuit, the input of this second bias control circuit is optionally connected to this logic voltage source and and reads voltage source, and the output of this second bias control circuit is connected to this node a; And one the 3rd nmos pass transistor, drain electrode is connected to this node a, grid is connected to this voltage switcher circuit input, source electrode and substrate are connected to an earth terminal.
The invention relates to a kind of voltage switcher circuit, there is one first pressure drop path, comprise a node a, and, one second pressure drop path has a node b, this voltage switcher circuit also comprises: an output circuit, is connected to a high voltage source, and has one first output and be connected to this first pressure drop path and one second output is connected to this second pressure drop path; Multiple pressure drop control circuit, be connected between this first output and this node a and be connected between this second output and this node b; One input circuit, is connected to this node a and this node b, and this input circuit has a first input end and one second input; Wherein, when this first input end receives a high logic level and this second input receives a low logic level, the voltage of this node a equals an earth terminal, this first output produces voltage level in, this node b produces this high logic level, and this second output produces the voltage of this high voltage source, wherein, the voltage of this high voltage source is greater than voltage level in this, and in this, voltage level is greater than this high logic level.
In order to have better understanding, preferred embodiment cited below particularly to above-mentioned and other side of the present invention, and coordinating institute's accompanying drawings, being described in detail below.
Accompanying drawing explanation
Fig. 1 illustrate is decoding circuit module diagram in known as memory device.
Fig. 2 A illustrate specific embodiment into voltage switcher circuit of the present invention.
Fig. 2 B illustrate bias voltage schematic diagram into voltage switcher circuit of the present invention.
Fig. 3 A illustrate is another voltage switcher circuit schematic diagram of the present invention.
Fig. 3 B to Fig. 3 D illustrate as voltage switcher circuit bias voltage schematic diagram under various regimes.
[main element label declaration]
110: high pressure decoding switched system 120: voltage switcher circuit
130: the first voltage switcher circuit groups 140: decoding unit
150: low pressure decoding switched system 160: the second voltage switcher circuit group
210: output circuit 220: the first pressure drop circuit
230: the second pressure drop circuit 232: the first bias circuits
234: the second bias circuit 240: the three pressure drop circuit
250: input circuit 252: the three bias circuit
254: the four bias circuit 310: the first bias circuits
320: the second bias circuits 340: decoding unit
Embodiment
A kind of high voltage bearing low-doped (Lightly Doped) PMOS transistor can be provided in semiconductor maker now in standard logic processing procedure.In other words, this kind of low-doped PMOS transistor can resist high voltage stress, and is compatible with standard logic processing procedure now.Therefore, namely the present invention utilizes low-doped PMOS transistor to design a voltage switcher circuit.That is, in voltage switcher circuit of the present invention, only low-doped PMOS transistor can meet with high voltage stress, and other transistor can not meet with high voltage stress.
Please refer to Fig. 2 A, its illustrate specific embodiment into voltage switcher circuit of the present invention.Voltage switcher circuit comprises: output circuit 210, first pressure drop control circuit (voltage drop controlcircuit) 220, a second pressure drop control circuit 230, the 3rd pressure drop control circuit 240 and an input circuit 250.Wherein, high voltage source (HV) is greater than reference voltage source (Vref), and reference voltage source (Vref) is greater than logic voltage source (VDD).
Output circuit 210 comprises one first PMOS transistor to (PMOS transistor pair), wherein, first PMOS transistor p1 source electrode (source) and substrate (body) are connected to high voltage source (HV), drain electrode (drain) is connected to reversed-phase output (OUTB), and grid (gate) is connected to output (OUT); Second PMOS transistor p2 source electrode and substrate are connected to high voltage source (HV), and drain electrode is connected to output (OUT), grid is connected to reversed-phase output (OUTB).
First pressure drop control circuit 220 comprises one second PMOS transistor pair, wherein, the substrate of the 3rd PMOS transistor p3 is connected to high voltage source (HV), source electrode is connected to reversed-phase output (OUTB), drain electrode is connected to node e, and grid is connected to reference voltage source (Vref); The substrate of the 4th PMOS transistor p4 is connected to high voltage source (HV), and source electrode is connected to output (OUT), and drain electrode is connected to node f, and grid is connected to reference voltage source (Vref).
Second pressure drop control circuit 230 comprises one first nmos pass transistor to, one first bias control circuit 232 and one second bias control circuit 234.
First bias control circuit 232 comprises one the 5th PMOS transistor p5 and the 6th PMOS transistor p6.5th PMOS transistor p5 source electrode is the input of the first bias control circuit 232 and is connected to node b, and grid is connected to reference voltage (Vref), substrate and drain electrode and is interconnected and as the output of the first bias control circuit 232; 6th PMOS transistor p6 source electrode is connected to logic voltage source (VDD), and grid is the control end of the first bias control circuit 232 and is connected to node e, and substrate and drain electrode are interconnected and are connected to the output of the first bias control circuit 232.
Second bias control circuit 234 comprises one the 7th PMOS transistor p7 and the 8th PMOS transistor p8.7th PMOS transistor p7 source electrode is the input of the second bias control circuit 234 and is connected to node a, and grid is connected to reference voltage (Vref), substrate and drain electrode and is interconnected and as the output of the second bias control circuit 234; 8th PMOS transistor p8 source electrode is connected to logic voltage source (VDD), and grid is the control end of the second bias control circuit 234 and is connected to node f, and substrate and drain electrode are interconnected and are connected to the output of the second bias control circuit 234.
First nmos pass transistor is to comprising: the first nmos pass transistor n1 and the second nmos pass transistor n2.The drain electrode of the first nmos pass transistor n1 is connected to the control end of node e and the first bias control circuit 232, and grid is connected to the output of the first bias control circuit 232, and substrate and source electrode are connected to node c; The drain electrode of the second nmos pass transistor n2 is connected to the control end of node f and the second bias control circuit 234, and grid is connected to the output of the second bias control circuit 234, and substrate and source electrode are connected to node d.
3rd pressure drop control circuit 240 comprises one second nmos pass transistor pair, and wherein, the drain electrode of the 3rd nmos pass transistor n3 is connected to node c, grid is connected to logic voltage source (VDD), substrate and source electrode and is connected to node a; The drain electrode of the 4th nmos pass transistor n4 is connected to node d, grid is connected to logic voltage source (VDD), substrate and source electrode and is connected to node b.
Input circuit 250 comprises one the 3rd nmos pass transistor to, one the 3rd bias control circuit 252 and one the 4th bias control circuit 254.
3rd bias control circuit 252 comprise one the 9th PMOS transistor p9 source electrode and substrate be the input of the 3rd bias control circuit 252 and be connected to logic voltage source (VDD), control end that grid is the 3rd bias control circuit 252 and be connected to input IN, drain be the 3rd bias control circuit 252 output and be connected to node a.
4th bias control circuit 254 comprise 1 the tenth PMOS transistor p10 source electrode and substrate be the input of the 4th bias control circuit 254 and be connected to logic voltage source (VDD), control end that grid is the 4th bias control circuit 254 and be connected to inverting input INB, drain be the 4th bias control circuit 254 output and be connected to node b.
3rd nmos pass transistor is to comprising: the 5th nmos pass transistor n5 and the 6th nmos pass transistor n6.The drain electrode of the 5th nmos pass transistor n5 is connected to the output of node a and the 3rd bias control circuit 252, and grid is connected to input (IN), and substrate and source electrode are connected to earth terminal; The drain electrode of the 6th nmos pass transistor n6 is connected to the output of node b and the 4th bias control circuit 254, and grid is connected to inverting input (INB), and substrate and source electrode are connected to earth terminal.
Please refer to Fig. 2 B, its illustrate bias voltage schematic diagram into voltage switcher circuit of the present invention.Wherein, high voltage source (HV) is 18V, and reference voltage source (Vref) is 9V, and logic voltage source (VDD) is 6V.And by forming a pressure drop path between inverse output terminal (OUTB) to earth terminal, form another pressure drop path by between output (OUT) to earth terminal.Below its operating process is introduced in detail.
When input (IN) receives high logic level (6V) and inverting input (INB) receives low logic level (0V), in input circuit 250 1 the 3rd bias control circuit 252 inoperation (inactivated), one the 4th bias control circuit 254 operate (activated), the 5th nmos pass transistor n5 opens (turnon), the 6th nmos pass transistor n6 closes (turn off), now the voltage of node a is the voltage of 0V (Va=0V), node b is 6V (Vb=6V).
Voltage due to node a is the voltage of 0V (Va=0V), node b is 6V (Vb=6V), and the 3rd nmos pass transistor n3 therefore in the 3rd pressure drop control circuit 240 opens, and the 4th nmos pass transistor n4 closes.Now, the voltage of node c is that the voltage (Vd) of 0V (Vc=0V), node d need be decided by the second pressure drop control circuit 230.
Moreover, because node b voltage is 6V (Vb=6V), node c voltage is 0V (Vc=0V), (the 6th PMOS transistor p6 opens the first bias control circuit 232 in second pressure drop control circuit 230,5th PMOS transistor p5 close) output can export 6V to the first nmos pass transistor n1 grid (Vg=6V), first nmos pass transistor n1 is opened, and the voltage of node e is 0V (Ve=0V).
When the voltage of node e is 0V (Ve=0V), and the 3rd PMOS transistor p3 in the first pressure drop control circuit 220 and the 4th PMOS transistor p4 grid are connected to the reference voltage source (Vref) of 9V, therefore reversed-phase output (OUTB) voltage can be made, that is the 3rd PMOS transistor p3 source voltage, for (9V+| Δ Vp ∣), wherein Δ Vp is the limit voltage (threshold voltage) of PMOS transistor.
Then, in output circuit 210, because reversed-phase output (OUTB) voltage is (9V+| Δ Vp|), therefore, second PMOS transistor p2 opens, it is 18V that output (OUT) voltage equals high power supply voltage (HV), and the first PMOS transistor p1 closes.
Because output end voltage (OUT) is 18V, will the 4th PMOS transistor p4 in the first pressure drop control circuit 220 be opened, and the voltage of node f be 18V (Vf=18V).
Voltage due to node f is 18V (Vf=18V) and the voltage of node a is 0V (Va=0), therefore, the 8th PMOS transistor p8 in second bias control circuit 234 closes, make the output of the second bias control circuit 234 produce voltage to the second nmos pass transistor n2 grid (Vg=9V+| Δ Vp|) of (9V+| Δ Vp|), therefore the voltage of node d will maintain 9V (Vd=9V).
Because voltage switcher circuit of the present invention is symmetrical circuit, therefore, when input (IN) for low logic level (0V) and inverting input (INB) for high logic level (6V) time, all operating principles all can with reference to above description, make output (OUT) produce (9V+| Δ Vp|), reversed-phase output (OUTB) produces 18V.
Suppose that the limit voltage Δ Vp of PMOS transistor is for (-1V), then, when input (IN) receives high logic level (6V), output (OUT) can produce the 18V of high voltage source (HV); When input (IN) receives low logic level (0V), output (OUT) can produce 10V.
Certainly, in Fig. 2 A, input (IN) and inverting input (INB) can be exchanged, when making input (IN) receive low logic level (0V), output (OUT) can produce the 18V of high voltage source (HV); When input (IN) receives high logic level (6V), output (OUT) can produce 10V.
Or, in Fig. 2 A, output (OUT) and reversed-phase output (OUTB) can be exchanged, when making input (IN) receive low logic level (0V), output (OUT) can produce the 18V of high voltage source (HV); When input (IN) receives high logic level (6V), output (OUT) can produce 10V.
Moreover, from in the bias voltage schematic diagram of voltage switcher circuit, first to the 8th PMOS transistor p1 ~ p8 can bear high voltage stress on other occasions, therefore utilizes the low-doped PMOS transistor being compatible with logical circuit processing procedure to carry out first to the 8th PMOS transistor p1 ~ p8.Therefore, voltage switcher circuit of the present invention can utilize logical circuit processing procedure to complete, and can reduce costs and the complexity of design circuit.
Utilize bias control circuit of the present invention, also can apply to the voltage switcher circuit in known second voltage switcher circuit group.Clear with reference to Fig. 3 A, its illustrate is another voltage switcher circuit schematic diagram of the present invention.Wherein, the output (OUT) of voltage switcher circuit is connected to array bus holding wire (Array_bus), and decoding unit 340 can optionally provide input voltage (VPP) to the output (OUT) of voltage switcher circuit.
Voltage switcher circuit comprises the first nmos pass transistor n1, the second nmos pass transistor n2, the 3rd nmos pass transistor n3, the first bias control circuit 310 and the second bias control circuit 320.
First bias control circuit 310 comprises one first PMOS transistor p1 and one second PMOS transistor p2.First PMOS transistor p1 source electrode is the input of the first bias control circuit 310 and connects the input (IN) of voltage switcher circuit, and grid is connected to reference voltage (Vref), substrate and drain electrode and is interconnected and as the output of the first bias control circuit 310; Second PMOS transistor p2 source electrode is connected to logic voltage source (VDD), grid is the control end of the first bias control circuit 310 and is connected to the output (OUT) of voltage switcher circuit, and substrate and drain electrode are interconnected and are connected to the output of the first bias control circuit 310.
First nmos pass transistor n1 drain electrode is connected to the output (OUT) of voltage switcher circuit, and grid is connected to the output of the first bias control circuit 310, and source electrode and substrate are connected to node b.
Second nmos pass transistor n2 drain electrode is connected to node b, grid is connected to logic voltage source (VDD), source electrode and substrate and is connected to node a.
Second bias control circuit 320 comprise input that one the 3rd PMOS transistor p3 source electrode and substrate are the second bias control circuit 320 and be optionally connected to logic voltage source (VDD) or read voltage source (VR), control end that grid is the second bias control circuit 320 and be connected to voltage switcher circuit input (NB), drain be the second bias control circuit 320 output and be connected to node a.
3rd input (NB), source electrode and the substrate that nmos pass transistor n3 drain electrode is connected to node a, grid is connected to voltage switcher circuit is connected to earth terminal.
Please refer to Fig. 3 B to Fig. 3 D, its illustrate as voltage switcher circuit bias voltage schematic diagram under various regimes.Wherein, the input voltage (VPP) that decoding unit 340 provides is 18V, and reference voltage source (Vref) is 9V, and logic voltage source (VDD) is 6V, reading voltage source (VR) is 1.8V.Below its operating process is introduced in detail.
As shown in Figure 3 B, when the first state, the 18V input voltage (VPP) that decoding unit 340 provides to the output (OUT) of voltage switcher circuit and input (IN) for low logic level (0V) time, second bias control circuit 320 operates (activated), the 3rd nmos pass transistor n3 closes, and now the voltage of node a is 6V (Va=6V).
Voltage due to node a is 6V (Va=6V), and the second nmos pass transistor n2 grid is connected to the logic voltage source (VDD) of 6V.Therefore, the second nmos pass transistor n2 closes, and the voltage (Vb) of node b need decide according to the bias voltage of the first nmos pass transistor n1.
Voltage due to output (OUT) is 18V (OUT=18V) and the voltage of input (IN) is low logic level (IN=0V), therefore, the second PMOS transistor p2 in first bias control circuit 310 closes, make the output of the first bias control circuit 310 produce voltage to the first nmos pass transistor n1 grid (Vg=9V+| Δ Vp|) of (9V+| Δ Vp|), therefore the voltage of node b will maintain 9V (Vb=9V).
As shown in Figure 3 C, when the second state, decoding unit 340 output (OUT) of 18V input voltage (VPP) to voltage switcher circuit is not provided and input (IN) for high logic level (6V) time, second bias control circuit 320 inoperation (inact ivated), the 3rd nmos pass transistor n3 open, and now the voltage of node a is 0V (Va=0V).
Voltage due to node a is 0V (Va=0V), and therefore the second nmos pass transistor n2 opens.Now, the voltage of node b is 0V (Vb=0V).
Moreover, because node b voltage is 0V (Vb=0V) and input (IN) receives the high logic level of 6V, (the second PMOS transistor p2 opens first bias control circuit 310, first PMOS transistor p1 close) output can export 6V to the first nmos pass transistor n1 grid (Vg=6V), first nmos pass transistor n1 is opened, and makes the voltage of output (OUT) be 0V (OUT=0V).
As shown in Figure 3 D, when the third state, the 18V input voltage (VPP) that decoding unit 340 does not provide to the output (OUT) of voltage switcher circuit and input (IN) for low logic level (0V) and the second bias control circuit 320 input is connected to the reading voltage source (VR) of 1.8V.Now, the second bias control circuit 320 operates (activated), the 3rd nmos pass transistor n3 closes, and now the voltage of node a is 1.8V (Va=1.8V).
Voltage due to node a is 1.8V (Va=1.8V), and the second nmos pass transistor n2 grid is connected to the logic voltage source (VDD) of 6V.Therefore, the second nmos pass transistor n2 opens, and the voltage of node b is 1.8V (Vb=1.8V).
Moreover, because node b voltage is 1.8V (Vb=1.8V) and input (IN) receives the low logic level of 0V, (the second PMOS transistor p2 opens first bias control circuit 310, first PMOS transistor p1 close) output can export 6V to the first nmos pass transistor n1 grid (Vg=6V), first nmos pass transistor n1 is opened, and makes the voltage of output (OUT) be 1.8V (OUT=1.8V).
From voltage switcher circuit bias voltage schematic diagram in Fig. 3 B to Fig. 3 D, the first to the second PMOS transistor p1 ~ p2 can bear high voltage stress on other occasions, therefore utilizes the low-doped PMOS transistor being compatible with logical circuit processing procedure to complete first and second PMOS transistor p1 ~ p2.Therefore, voltage switcher circuit of the present invention can utilize logical circuit processing procedure to complete, and can reduce costs and the complexity of design circuit.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on the appended right person of defining.
Claims (30)
1. a voltage switcher circuit, comprising:
One output circuit, comprise one first PMOS transistor, source electrode and substrate are connected to a high voltage source, and drain electrode is connected to the reversed-phase output of this voltage switcher circuit, and grid is connected to the output of this voltage switcher circuit; And, one second PMOS transistor, source electrode and substrate are connected to this high voltage source, the reversed-phase output that drain electrode is connected to the output of this voltage switcher circuit, grid is connected to this voltage switcher circuit;
One first pressure drop control circuit, comprise one the 3rd PMOS transistor, substrate is connected to this high voltage source, and source electrode is connected to this reversed-phase output, and drain electrode is connected to a node e, and grid is connected to a reference voltage source; And, one the 4th PMOS transistor, substrate is connected to this high voltage source, and source electrode is connected to this output, and drain electrode is connected to a node f, and grid is connected to this reference voltage source;
One second pressure drop control circuit, comprises one first nmos pass transistor, one second nmos pass transistor, one first bias control circuit and one second bias control circuit; Wherein, the drain electrode of this first nmos pass transistor is connected to the control end of this node e and this first bias control circuit, and grid is connected to the output of this first bias control circuit, and substrate and source electrode are connected to a node c; And, this second nmos pass transistor, drain electrode is connected to the control end of this node f and this second bias control circuit, and grid is connected to the output of this second bias control circuit, and substrate and source electrode are connected to a node d;
One the 3rd pressure drop control circuit, comprises one the 3rd nmos pass transistor, and drain electrode is connected to this node c, grid is connected to a logic voltage source, substrate and source electrode and is connected to a node a; And, one the 4th nmos pass transistor, drain electrode is connected to this node d, grid is connected to this logic voltage source, substrate and source electrode and is connected to a node b; And
One input circuit, comprises one the 5th nmos pass transistor, one the 6th nmos pass transistor, one the 3rd bias control circuit, with one the 4th bias control circuit; Wherein, the 5th nmos pass transistor, drain electrode is connected to the output of this node a and the 3rd bias control circuit, and grid is connected to the input of this voltage switcher circuit, and substrate and source electrode are connected to an earth terminal; And the 6th nmos pass transistor, drain electrode is connected to the output of this node b and the 4th bias control circuit, and grid is connected to the inverting input of this voltage switcher circuit, and substrate and source electrode are connected to this earth terminal.
2. voltage switcher circuit according to claim 1, wherein the voltage of this high voltage source is greater than the voltage of this reference voltage source, and the voltage of this reference voltage source is greater than the voltage in this logic voltage source.
3. voltage switcher circuit according to claim 1, wherein the voltage of this high voltage source is 18V, and the voltage of this reference voltage source is 9V, and the voltage in this logic voltage source is 6V.
4. voltage switcher circuit according to claim 1, wherein this first PMOS transistor, this second PMOS transistor, the 3rd PMOS transistor, with the 4th PMOS transistor be high voltage bearing low-doped PMOS transistor.
5. voltage switcher circuit according to claim 1, wherein, this first bias control circuit comprises: one the 5th PMOS transistor and one the 6th PMOS transistor; Wherein, the 5th PMOS transistor source electrode is the input of this first bias control circuit and is connected to this node b, and grid is connected to this reference voltage source, substrate and drain electrode and is interconnected and as the output of this first bias control circuit; And the 6th PMOS transistor, source electrode is connected to this logic voltage source, and grid is the control end of this first bias control circuit and is connected to this node e, and substrate and drain electrode are interconnected and are connected to the output of this first bias control circuit.
6. voltage switcher circuit according to claim 5, wherein the 5th PMOS transistor, with the 6th PMOS transistor be high voltage bearing low-doped PMOS transistor.
7. voltage switcher circuit according to claim 1, wherein, this second bias control circuit comprises: one the 7th PMOS transistor and one the 8th PMOS transistor; Wherein, the 7th PMOS transistor source electrode is the input of this second bias control circuit and is connected to this node a, and grid is connected to this reference voltage source, substrate and drain electrode and is interconnected and as the output of this second bias control circuit; And the 8th PMOS transistor source electrode is connected to this logic voltage source, grid is the control end of this second bias control circuit and is connected to this node f, and substrate and drain electrode are interconnected and are connected to the output of this second bias control circuit.
8. voltage switcher circuit according to claim 7, wherein the 7th PMOS transistor, with the 8th PMOS transistor be high voltage bearing low-doped PMOS transistor.
9. voltage switcher circuit according to claim 1, wherein the 3rd bias control circuit comprises: one the 9th PMOS transistor, source electrode and substrate be the input of the 3rd bias control circuit and be connected to this logic voltage source, control end that grid is the 3rd bias control circuit and be connected to this voltage switcher circuit input, drain for the 3rd bias control circuit output and be connected to this node a.
10. voltage switcher circuit according to claim 1, wherein the 4th bias control circuit comprises: 1 the tenth PMOS transistor, source electrode and substrate be the input of the 4th bias control circuit and be connected to this logic voltage source, control end that grid is the 4th bias control circuit and be connected to this voltage switcher circuit inverting input, drain for the 4th bias control circuit output and be connected to this node b.
11. 1 kinds of voltage switcher circuit, the output of this voltage switcher circuit is connected to a bus signal line and this bus signal line can optionally provide an input voltage by a control circuit, comprising:
One first nmos pass transistor, drain electrode is connected to the output of voltage switcher circuit, and source electrode and substrate are connected to a node b;
One first bias control circuit, the control end of this first bias control circuit is connected to the output of this voltage switcher circuit, another control end of this first bias control circuit is connected to a reference voltage source, the input of this first bias control circuit is connected to the input of this voltage switcher circuit, and the output of this first bias control circuit is connected to this first nmos pass transistor grid;
One second nmos pass transistor, drain electrode is connected to this node b, grid is connected to a logic voltage source, source electrode and substrate and is connected to a node a;
One second bias control circuit, the control end of this second bias control circuit is connected to the input of this voltage switcher circuit, the input of this second bias control circuit is optionally connected to this logic voltage source and and reads voltage source, and the output of this second bias control circuit is connected to this node a; And
One the 3rd nmos pass transistor, drain electrode is connected to this node a, grid is connected to this voltage switcher circuit input, source electrode and substrate are connected to an earth terminal.
12. voltage switcher circuit according to claim 11, wherein the input voltage of this control circuit is greater than the voltage of this reference voltage source, the voltage of this reference voltage source is greater than the voltage in this logic voltage source, and the voltage in this logic voltage source is greater than the voltage of this reading voltage source.
13. voltage switcher circuit according to claim 11, wherein the input voltage of this control circuit is 18V, and the voltage of this reference voltage source is 9V, and the voltage in this logic voltage source is 6V, and the voltage of this reading voltage source is 1.8V.
14. voltage switcher circuit according to claim 11, wherein, this first bias control circuit, comprising: one first PMOS transistor and one second PMOS transistor; Wherein, this the first PMOS transistor source electrode is the input of this first bias control circuit and connects the input of this voltage switcher circuit, and grid is connected to this reference voltage source, substrate and drain electrode and is interconnected and as the output of this first bias control circuit; And, this second PMOS transistor, source electrode is connected to this logic voltage source, and grid is the control end of this first bias control circuit and is connected to the output of this voltage switcher circuit, and substrate and drain electrode are interconnected and are connected to the output of this first bias control circuit.
15. voltage switcher circuit according to claim 14, wherein this first PMOS transistor, with this second PMOS transistor be high voltage bearing low-doped PMOS transistor.
16. voltage switcher circuit according to claim 11, wherein, this second bias control circuit comprises: one the 3rd PMOS transistor, source electrode and substrate be this second bias control circuit input and be optionally connected to control end that this logic voltage source and this reading voltage source, grid are this second bias control circuit and be connected to this voltage switcher circuit input, drain be this second bias control circuit output and be connected to this node a.
17. 1 kinds of voltage switcher circuit, have one first pressure drop path, comprise a node a, and one second pressure drop path has a node b, and this voltage switcher circuit also comprises:
One output circuit, is connected to a high voltage source, and has one first output and be connected to this first pressure drop path and one second output is connected to this second pressure drop path;
Multiple pressure drop control circuit, be connected between this first output and this node a and be connected between this second output and this node b;
One input circuit, is connected to this node a and this node b, and this input circuit has a first input end and one second input;
Wherein, when this first input end receives a high logic level and this second input receives a low logic level, the voltage of this node a equals an earth terminal, this first output produces voltage level in, and this node b produces this high logic level, and this second output produces the voltage of this high voltage source, wherein, the voltage of this high voltage source is greater than voltage level in this, and in this, voltage level is greater than this high logic level
Wherein, this input circuit comprises one the 5th nmos pass transistor, one the 6th nmos pass transistor, one the 3rd bias control circuit, with one the 4th bias control circuit; Wherein, the 5th nmos pass transistor, drain electrode is connected to the output of this node a and the 3rd bias control circuit, and grid is connected to the input of this voltage switcher circuit, and substrate and source electrode are connected to this earth terminal; And the 6th nmos pass transistor, drain electrode is connected to the output of this node b and the 4th bias control circuit, and grid is connected to the inverting input of this voltage switcher circuit, and substrate and source electrode are connected to this earth terminal.
18. voltage switcher circuit according to claim 17, wherein the voltage of this high voltage source is 18V, and in this, the voltage of voltage level is 10V, and the voltage in this logic voltage source is 6V.
19. voltage switcher circuit according to claim 17, wherein, this output circuit, comprises one first PMOS transistor, and source electrode and substrate are connected to this high voltage source, and drain electrode is connected to this second output, and grid is connected to this first output; And one second PMOS transistor, source electrode and substrate are connected to this high voltage source, and drain electrode is connected to this first output, grid is connected to this second output.
20. voltage switcher circuit according to claim 17, wherein, this first pressure drop path, also comprises an a node c and node e; This second pressure drop path has an a node d and node f, and one first pressure drop control circuit in the plurality of pressure drop control circuit comprises: one the 3rd PMOS transistor, substrate is connected to this high voltage source, source electrode is connected to this second output, drain electrode is connected to this node e, and grid is connected to a reference voltage source; And, one the 4th PMOS transistor, substrate is connected to this high voltage source, and source electrode is connected to this first output, and drain electrode is connected to this node f, and grid is connected to this reference voltage source; Wherein, the voltage of this reference voltage source is less than voltage level in this, and the voltage of this reference voltage source is greater than the voltage in this logic voltage source.
21. voltage switcher circuit according to claim 20, wherein the voltage of this reference voltage source is 9V.
22. voltage switcher circuit according to claim 20, wherein, this output circuit, comprises one first PMOS transistor, and source electrode and substrate are connected to this high voltage source, and drain electrode is connected to this second output, and grid is connected to this first output; And, one second PMOS transistor, source electrode and substrate are connected to this high voltage source, drain electrode is connected to this first output, grid is connected to this second output, and wherein this first PMOS transistor, this second PMOS transistor, the 3rd PMOS transistor, be high voltage bearing low-doped PMOS transistor with the 4th PMOS transistor.
23. voltage switcher circuit according to claim 20, wherein, one second pressure drop control circuit in the plurality of pressure drop control circuit comprises: one first nmos pass transistor, one second nmos pass transistor, one first bias control circuit and one second bias control circuit; Wherein, the drain electrode of this first nmos pass transistor is connected to the control end of this node e and this first bias control circuit, and grid is connected to the output of this first bias control circuit, and substrate and source electrode are connected to this node c; And this second nmos pass transistor, drain electrode is connected to the control end of this node f and this second bias control circuit, and grid is connected to the output of this second bias control circuit, and substrate and source electrode are connected to this node d.
24. voltage switcher circuit according to claim 23, wherein, this first bias control circuit comprises: one the 5th PMOS transistor and one the 6th PMOS transistor; Wherein, the 5th PMOS transistor source electrode is the input of this first bias control circuit and is connected to this node b, and grid is connected to this reference voltage source, substrate and drain electrode and is interconnected and as the output of this first bias control circuit; And the 6th PMOS transistor, source electrode is connected to this logic voltage source, and grid is the control end of this first bias control circuit and is connected to this node e, and substrate and drain electrode are interconnected and are connected to the output of this first bias control circuit.
25. voltage switcher circuit according to claim 24, wherein the 5th PMOS transistor, with the 6th PMOS transistor be high voltage bearing low-doped PMOS transistor.
26. voltage switcher circuit according to claim 23, wherein, this second bias control circuit comprises: one the 7th PMOS transistor and one the 8th PMOS transistor; Wherein, the 7th PMOS transistor source electrode is the input of this second bias control circuit and is connected to this node a, and grid is connected to this reference voltage source, substrate and drain electrode and is interconnected and as the output of this second bias control circuit; And the 8th PMOS transistor source electrode is connected to this logic voltage source, grid is the control end of this second bias control circuit and is connected to this node f, and substrate and drain electrode are interconnected and are connected to the output of this second bias control circuit.
27. voltage switcher circuit according to claim 26, wherein the 7th PMOS transistor, with the 8th PMOS transistor be high voltage bearing low-doped PMOS transistor.
28. voltage switcher circuit according to claim 23, wherein, one the 3rd pressure drop control circuit in the plurality of pressure drop control circuit comprises: one the 3rd nmos pass transistor, and drain electrode is connected to this node c, grid is connected to this logic voltage source, substrate and source electrode and is connected to this node a; And one the 4th nmos pass transistor, drain electrode is connected to this node d, grid is connected to this logic voltage source, substrate and source electrode and is connected to this node b.
29. voltage switcher circuit according to claim 17, wherein the 3rd bias control circuit comprises: one the 9th PMOS transistor, source electrode and substrate be the input of the 3rd bias control circuit and be connected to this logic voltage source, control end that grid is the 3rd bias control circuit and be connected to this first input end, drain for the 3rd bias control circuit output and be connected to this node a.
30. voltage switcher circuit according to claim 17, wherein the 4th bias control circuit comprises: 1 the tenth PMOS transistor, source electrode and substrate be the input of the 4th bias control circuit and be connected to this logic voltage source, control end that grid is the 4th bias control circuit and be connected to this second input, drain for the 4th bias control circuit output and be connected to this node b.
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| CN201110329202.7A CN103078618B (en) | 2011-10-26 | 2011-10-26 | Voltage switcher circuit |
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| US9847133B2 (en) * | 2016-01-19 | 2017-12-19 | Ememory Technology Inc. | Memory array capable of performing byte erase operation |
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