CN103094317A - Isolation type high voltage resistance field effect transistor (FET) and layout structure - Google Patents
Isolation type high voltage resistance field effect transistor (FET) and layout structure Download PDFInfo
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Abstract
The invention discloses an isolation type high voltage resistance field effect transistor (FET). A drift area of a drain region on a silicon substrate is extended to cover a whole source region, the isolation of a substrate of the source region and the silicon substrate is realized, and therefore the effects that the substrate electric potential of the FET cannot be affected by the electric potential of the silicon substrate, and the electric potential can be added independently can be achieved. The invention further provides a layout structure of the isolation type high voltage resistance FET. The layout structure of the isolation type high voltage resistance FET comprises the drain region, the source region, the drain region drift area, a drift region, a source region poly silicon field plate, grid electrodes and a drain region poly silicon field plate, wherein the source region poly silicon field plate, the grid electrodes and the drain region poly silicon field plate are all in U-shaped enclosed structures, and the drain region poly silicon field plate is located inside the source region poly silicon field plate and the grid electrodes. Due to the structure that the source region completely surrounds the drain region, and meanwhile, the substrate, drift region implantation and a doped region are adopted at a circular arc position at the bottom of a U-shaped inner layer to form an isolation voltage resistance ring, the situation that high voltage electric potential is located outside the position, and low voltage electric potential is located inside the position is avoided, breakdown voltage can be affected in a concentrative mode by a power line, and therefore the high voltage resistant capacity is achieved, and the area of a device is reduced at the same time.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly the high withstand voltage field effect transistor of a kind of isolated form and domain structure.
Background technology
The high withstand voltage N-type field effect transistor of the non-isolation type that the high withstand voltage field effect transistor of using at present normally forms on P type silicon substrate substrate 301, the cross section as shown in Figure 2, P type silicon substrate substrate 301 carries out N-type and injects and to be formed with N-type drift region 302, the source region is positioned at outside N-type drift region 302, makes the substrate P type trap 303 of field effect transistor connect together with P type silicon substrate substrate 301.Drift region, drain region 403 use N+ active areas 307 are drawn, and form drain region 401, and generating in drift region, drain region 403 has an oxygen isolation 305, and the below of an oxygen isolation 305 is formed with the P type doped region 304 different from drift region, drain region 403 Implantation types.Source is formed by N+ active area 306, and the substrate P type trap 303 of field effect transistor is drawn P+ active area 308, and N+ active area 306 and P+ active area 308 use metals connect together, and forms source region 402.The source region also is formed with P type doped region for 402 times, and the P type doping 304 under field, drain region oxygen isolation 305 keeps certain distance.Above field, drain region oxygen isolation 305, be coated with polysilicon field plate 309, this field plate and grid polycrystalline silicon are that same polysilicon forms grid, and cover on P type doped region in drain region P type doped region 304 and source region.Be coated with polysilicon 310 in the field oxygen isolation 305 near the drain region, the N+ active area 307 of drawing with metallic aluminium 312 and drain region 401 connects together, and forms the drain region field plate.On Metal field plate 311 limits in source region, with a certain distance from placing another root Metal field plate 313, Metal field plate 313 and grid polycrystalline silicon connect together.
The surface plate graph structure of above-mentioned non-isolation type field effect transistor as shown in Figure 1, source region polysilicon field plate and grid 309 are non-closing structure, cross section such as Fig. 2 structure at B-B and C-C place.
The substrate of the high withstand voltage field effect transistor of above-mentioned non-isolation type can't be opened with the silicon substrate substrate isolation, in some circuit design, require the source region to connect in the situation of certain potentials and just can't use, and said structure can't be realized.Improve withstand voltage aspect, in the high withstand voltage field-effect tube structure of existing non-isolation type, structure shown in Figure 3 is adopted in drift region position A-A cross section, drain region shown in Figure 1, be that P type silicon substrate substrate substrate 301 and N-type drift region 302 are carried out withstand voltage, owing to being that complete PN junction exhausts to tolerate high pressure, enough withstand voltage in order to provide enough depletion regions to bear, the P type substrate zone that needs is larger, can cause the area of whole device bigger than normal.
Summary of the invention
The technical problem to be solved in the present invention is to provide the high withstand voltage field effect transistor of a kind of isolated form, can realize the isolation of substrate and the silicon substrate substrate of field effect transistor, and solving needs the source region to connect the application of certain potentials in some circuit design.
For solving the problems of the technologies described above, the technical scheme of the high withstand voltage field effect transistor of isolated form of the present invention is: form a drift region that has with the second conduction type of the first conductivity type opposite on the silicon substrate substrate of the first conduction type having, described drift region comprises the drift region, drain region, drift region, described drain region is drawn by the first active area with second conduction type and is formed the drain region, generating in the drift region, drain region has an oxygen isolation, and the below of an oxygen isolation forms the first doped region with first conduction type; Form the well region with first conduction type in described silicon substrate substrate, well region is drawn by the 3rd active area with first conduction type, source is formed by the second active area with second conduction type, the second active area is connected with the 3rd active area and forms the source region, the below, source region is formed with the second doped region with first conduction type, between the first doped region under the second doped region and an oxygen isolation, a segment distance is arranged; Described source region is positioned at the inside of drift region, and well region and silicon substrate substrate are by separated drift regions.
Further, be coated with source region polysilicon field plate above the end of described oxygen isolation near the source region, described source region polysilicon field plate and grid polycrystalline silicon are that same polysilicon forms grid, the one end covers the first doped region near on the zone in source region, and the other end covers on the zone of drift region, the close drain region of the second doped region; Be coated with drain region polysilicon field plate above the end of described oxygen isolation near the drain region, described drain region polysilicon field plate is connected with the first active area by Metal field plate; Be provided with Metal field plate with Metal field plate at a distance of a segment distance place, described Metal field plate is connected with grid polycrystalline silicon.
In said structure, described the first conduction type is the P type, and the second conduction type is N-type, and perhaps described the first conduction type is N-type, and the second conduction type is the P type.
The technical problem that the present invention also will solve is to provide the domain structure of the high withstand voltage field effect transistor of a kind of isolated form, can provide high withstand voltage, reduces simultaneously the area in high withstand voltage zone.
for solving the problems of the technologies described above, the technical scheme of the high withstand voltage field effect transistor domain structure of isolated form of the present invention is: comprise the drain region, the source region, the drift region, drain region, the drift region, source region polysilicon field plate and grid polycrystalline silicon and drain region polysilicon field plate, described source region polysilicon field plate, grid polycrystalline silicon and drain region polysilicon field plate are closed polygonized structure, and drain region polysilicon field plate is positioned at the inside of source region polysilicon field plate and grid polycrystalline silicon, described drain region is positioned at closed drain region polysilicon field plate, the drift region, drain region is between source region polysilicon field plate and grid polycrystalline silicon and drain region polysilicon field plate, the source region is positioned at outside closed source region polysilicon field plate and grid polycrystalline silicon, described source region and drain region are positioned at the drift region, source region and silicon substrate substrate are by separated drift regions.
Further, described source region polysilicon field plate and grid polycrystalline silicon are the U-shaped structure of inside and outside bilayer, and inside and outside bilayer connects by the circular arc field plate; Described drain region polysilicon field plate is also the U-shaped structure of inside and outside bilayer, and inside and outside bilayer connects by the circular arc field plate, and drain region polysilicon field plate is between the U-shaped structure of inside and outside bilayer of source region polysilicon field plate and grid polycrystalline silicon.
wherein, be positioned at the field effect transistor at the circular arc place, U-shaped internal layer bottom of source region polysilicon field plate and grid polycrystalline silicon and drain region polysilicon field plate, form the well region with first conduction type in described silicon substrate substrate, well region is drawn by the 3rd active area with first conduction type, source is formed by the second active area with second conduction type, the second active area is connected with the 3rd active area and forms the source region, and the below, source region is formed with the second doped region with first conduction type, have and form a drift region that has with the second conduction type of the first conductivity type opposite on the silicon substrate substrate of the first conduction type, described drift region comprises the drift region, drain region, drift region, described drain region is drawn by the first active area with second conduction type and is formed the drain region, generate in the drift region, drain region an oxygen isolation is arranged, the below of field oxygen isolation forms the first doped region with first conduction type, between the first doped region and the second doped region, a segment distance is arranged, described drift region is positioned at source region and below, drain region, one end of field oxygen isolation is positioned on the drift region of below, drain region, the other end is positioned on the drift region of below, source region, the first doped region is positioned at outside the drift region of below, drain region away from an end in drain region, and be connected with the silicon substrate substrate, described source region is positioned at the inside of drift region, and well region and the second doped region are positioned at the drift region of below, source region, and pass through separated drift regions between the silicon substrate substrate, the oxygen isolation below, field of not injecting the drift region is formed with a plurality of isolation pressure rings.
Further, described isolation pressure ring comprises the 3rd doped region with first conduction type and the drift region with second conduction type, and the 3rd doped region is connected with an oxygen isolation, is the silicon substrate substrate between below, drift region and isolation pressure ring.Spacing between described isolation pressure ring is 1um～20um.
Described the first conduction type is the P type, and the second conduction type is N-type, and perhaps described the first conduction type is N-type, and the second conduction type is the P type.
Beneficial effect of the present invention is:
1. the high withstand voltage field effect transistor of isolated form of the present invention can realize the substrate isolation of substrate and the silicon substrate of field effect transistor, and the current potential of the substrate of field effect transistor will not be affected by the current potential of silicon substrate substrate can, independently add current potential;
2. in domain structure of the present invention, utilize whole encirclement drain region, source region, and connect with circular arc around the corner, also increase a plurality of high withstand voltage isolation pressure rings, can provide far above the withstand voltage field effect transistor of height puncture withstand voltage, avoid this place's high-voltage outside, the low pressure current potential is interior, power line is concentrated the problem that affects puncture voltage, guarantees to bear high withstand voltage when reducing device area.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the surface plate figure structure schematic representation of the high withstand voltage field effect transistor of existing non-isolation type;
Fig. 2 is the schematic cross-section of the high withstand voltage field effect transistor of non-isolation type at B-B place and C-C place in Fig. 1;
Fig. 3 is the schematic cross-section of the high withstand voltage field effect transistor of non-isolation type at A-A place in Fig. 1;
Fig. 4 is the surface plate figure structure schematic representation of the high withstand voltage field effect transistor of isolated form of the present invention;
Fig. 5 is the schematic cross-section of the high withstand voltage field effect transistor of isolated form that B ' in Fig. 4-B ' locates and C '-C ' locates;
Fig. 6 is the schematic cross-section of the high withstand voltage field effect transistor of the isolated form located of A ' in Fig. 4-A '.
Embodiment
the high withstand voltage field effect transistor of isolated form of the present invention, as shown in Figure 5, form the drift region 102 of N-type on P type silicon substrate substrate 101, described drift region 102 comprises drift region, drain region 203, drift region 203, described drain region is drawn by the first active area 107 of N-type and is formed drain region 201, generate in drift region, drain region 203 an oxygen isolation 105 is arranged, the below of field oxygen isolation 105 forms the first doped region 104 of P type, 201 when adding high pressure in the drain region, P type the first doped region 104 provides the neutralization of the electronics in easier and drift region, drain region 203, hole, produce depletion region to improve the withstand voltage of drain region 201.
Form the well region 103 of P type in P type silicon substrate substrate 101, well region 103 is drawn by the 3rd active area 108 of P type, source is formed by the second active area 106 of N-type, the second active area 106 is connected with the 3rd active area 108 and forms source region 202,202 belows, source region are formed with the second doped region 104a of P type, between the first doped region 104 under the second doped region 104a and an oxygen isolation 105, a segment distance are arranged.
Described source region 202 is positioned at the inside of drift region 102, and well region 103 and P type silicon substrate substrate 101 are by N-type drift region 102 isolation.
Be coated with source region polysilicon field plate 109 above the end of field oxygen isolation 105 near source regions 202, source region polysilicon field plate 109 and grid polycrystalline silicon 109a are that same polysilicon forms grid, the one end covers the first doped region 104 near on the zone in source region 202, and the other end covers on the zone of drift region, the close drain region of the second doped region 104a 203.
Be coated with drain region polysilicon field plate 110 above the end of field oxygen isolation 105 near drain regions 201, described drain region polysilicon field plate 110 is connected with the first active area 107 by Metal field plate 112.
Be provided with Metal field plate 113 with Metal field plate 111 at a distance of a segment distance place, described Metal field plate 113 is connected with grid polycrystalline silicon, has both formed Metal field plate, again because and the in parallel and reduction resistance of grid.
The domain structure of the high withstand voltage field effect transistor of isolated form of the present invention, as shown in Figure 4, comprise drain region 201, source region 202, drift region, drain region 203, drift region 102, source region polysilicon field plate 109 and grid polycrystalline silicon 109a and drain region polysilicon field plate 110, described source region polysilicon field plate 109 and grid polycrystalline silicon 109a are the U-shaped structure of inside and outside bilayer, and inside and outside bilayer connects by the circular arc field plate; Described drain region polysilicon field plate 110 is also the U-shaped structure of inside and outside bilayer, and inside and outside bilayer connects by the circular arc field plate, and drain region polysilicon field plate 110 is between the U-shaped structure of inside and outside bilayer of source region polysilicon field plate 109 and grid polycrystalline silicon 109a.Described drain region 201 is positioned at closed drain region polysilicon field plate 110, drift region, drain region 203 is between source region polysilicon field plate 109 and grid polycrystalline silicon 109a and drain region polysilicon field plate 110, source region 202 is positioned at outside closed source region polysilicon field plate 109 and grid polycrystalline silicon 109a, described source region 202 and drain region 201 are positioned at drift region 102, and source region 202 is isolated by drift region 102 with silicon substrate substrate 101.
Wherein, the structure that is positioned at the field effect transistor at the U-shaped internal layer bottom A ' of source region polysilicon field plate 109 and grid polycrystalline silicon 109a and drain region polysilicon field plate 110-A ' circular arc place is:
Form the well region 103 of P type in described P type silicon substrate substrate 101, well region 103 is drawn by the 3rd active area 108 of P type, source is formed by the second active area 106 of N-type, the second active area 106 is connected with the 3rd active area 108 and forms source region 202, and 202 belows, source region are formed with the second doped region 104a of P type;
Form a N-type drift region 102 on P type silicon substrate substrate 101, described drift region 102 comprises drift region, drain region 203, drift region, drain region 203 is drawn by the first active area 107 of N-type and is formed drain region 201, generate in drift region, drain region 203 an oxygen isolation 105 is arranged, between the first doped region 104, the first doped regions 104 of the below formation P type of field oxygen isolation 105 and the second doped region 104a, a segment distance is arranged.Described drift region 102 is positioned at source region 202 and 201 belows, drain region, one end of field oxygen isolation 105 is positioned on the drift region 102 of 201 belows, drain region, the other end is positioned on the drift region 102 of 202 belows, source region, the first doped region 104 is positioned at outside the drift region 102 of 201 belows, drain region away from an end in drain region 201, and is connected with silicon substrate substrate 101;
Described source region 202 is positioned at the inside of drift region 102, and well region 103 and the second doped region 104a are positioned at the drift region 102 of 202 belows, source region, and isolates by drift region 102 between silicon substrate substrate 101;
In the high withstand voltage field effect transistor of above-mentioned N-type, each implanted layer ionic type of conversion can form the high withstand voltage field effect transistor of P type.
The high withstand voltage field effect transistor of isolated form of the present invention can realize the substrate isolation of substrate and the silicon substrate of field effect transistor, and the current potential of the substrate of field effect transistor will not be affected by the current potential of silicon substrate substrate can, independently add current potential; In domain structure of the present invention, utilize whole encirclement drain region, source region, and connect with circular arc around the corner, also increase a plurality of high withstand voltage isolation pressure rings, can provide far above the withstand voltage field effect transistor of height puncture withstand voltage, avoid this place's high-voltage outside, the low pressure current potential is interior, power line is concentrated the problem that affects puncture voltage, guarantees to bear high withstand voltage when reducing device area.
Abovely by specific embodiment, the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. the high withstand voltage field effect transistor of isolated form, is characterized in that,
in the upper drift region (102) that has with the second conduction type of the first conductivity type opposite that forms of the silicon substrate substrate (101) with first conduction type, described drift region (102) comprises drift region, drain region (203), drift region, described drain region (203) is drawn by the first active area (107) with second conduction type and is formed drain region (201), generate in drift region, drain region (203) an oxygen isolation (105) is arranged, the below of field oxygen isolation (105) forms the first doped region (104) with first conduction type,
form the well region (103) with first conduction type in described silicon substrate substrate (101), well region (103) is drawn by the 3rd active area (108) with first conduction type, source is formed by the second active area (106) with second conduction type, the second active area (106) is connected with the 3rd active area (108) and forms source region (202), below, source region (202) is formed with the second doped region (104a) with first conduction type, between the first doped region (104) under the second doped region (104a) and an oxygen isolation (105), a segment distance is arranged,
Described source region (202) is positioned at the inside of drift region (102), and well region (103) is isolated by drift region (102) with silicon substrate substrate (101).
2. the high withstand voltage field effect transistor of isolated form according to claim 1, is characterized in that,
Be coated with source region polysilicon field plate (109) above the end of described oxygen isolation (105) near source region (202), described source region polysilicon field plate (109) and grid polycrystalline silicon (109a) are that same polysilicon forms grid jointly, the one end covers the first doped region (104) near on the zone in source region (202), and the other end covers the second doped region (104a) near on the zone of drift region, drain region (203);
Be coated with drain region polysilicon field plate (110) above the end of described oxygen isolation (105) near drain region (201), described drain region polysilicon field plate (110) is connected with the first active area (107) by Metal field plate (112);
Be provided with Metal field plate (113) with Metal field plate (111) at a distance of a segment distance place, described Metal field plate (113) is connected with grid polycrystalline silicon.
3. the high withstand voltage field effect transistor of isolated form according to claim 1 and 2, is characterized in that, described the first conduction type is the P type, and the second conduction type is N-type, and perhaps described the first conduction type is N-type, and the second conduction type is the P type.
4. the domain structure of the high withstand voltage field effect transistor of an isolated form, it is characterized in that, comprise drain region (201), source region (202), drift region, drain region (203), drift region (102), source region polysilicon field plate (109) and grid polycrystalline silicon (109a) and drain region polysilicon field plate (110), described source region polysilicon field plate (109), grid polycrystalline silicon (109a) and drain region polysilicon field plate (110) are closed polygonized structure, and drain region polysilicon field plate (110) is positioned at the inside of source region polysilicon field plate (109) and grid polycrystalline silicon (109a), described drain region (201) is positioned at closed drain region polysilicon field plate (110), drift region, drain region (203) is positioned between source region polysilicon field plate (109) and grid polycrystalline silicon (109a) and drain region polysilicon field plate (110), source region (202) is positioned at outside closed source region polysilicon field plate (109) and grid polycrystalline silicon (109a), described source region (202) and drain region (201) are positioned at drift region (102), source region (202) is isolated by drift region (102) with silicon substrate substrate (101).
5. the high withstand voltage field effect transistor domain structure of isolated form according to claim 1, is characterized in that, described source region polysilicon field plate (109) and grid polycrystalline silicon (109a) are the U-shaped structure of inside and outside bilayer, and inside and outside bilayer connects by the circular arc field plate; Described drain region polysilicon field plate (110) is also the U-shaped structure of inside and outside bilayer, inside and outside double-deck by the connection of circular arc field plate, and drain region polysilicon field plate (110) is positioned between the U-shaped structure of inside and outside bilayer of source region polysilicon field plate (109) and grid polycrystalline silicon (109a).
6. the high withstand voltage field effect transistor domain structure of isolated form according to claim 5, it is characterized in that, the field effect transistor that is positioned at the circular arc place, U-shaped internal layer bottom of source region polysilicon field plate (109) and grid polycrystalline silicon (109a) and drain region polysilicon field plate (110) is:
Form the well region (103) with first conduction type in described silicon substrate substrate (101), well region (103) is drawn by the 3rd active area (108) with first conduction type, source is formed by the second active area (106) with second conduction type, the second active area (106) is connected with the 3rd active area (108) and forms source region (202), and source region (202) below is formed with the second doped region (104a) with first conduction type;
has the silicon substrate substrate (101) of the first conduction type upper drift region (102) that has with the second conduction type of the first conductivity type opposite that forms, described drift region (102) comprises drift region, drain region (203), drift region, described drain region (203) is drawn by the first active area (107) with second conduction type and is formed drain region (201), generate in drift region, drain region (203) an oxygen isolation (105) is arranged, the below of field oxygen isolation (105) forms the first doped region (104) with first conduction type, between the first doped region (104) and the second doped region (104a), a segment distance is arranged, described drift region (102) is positioned at source region (202) and drain region (201) below, one end of field oxygen isolation (105) is positioned on the drift region (102) of below, drain region (201), the other end is positioned on the drift region (102) of below, source region (202), the first doped region (104) is positioned at outside the drift region (102) of below, drain region (201) away from an end of drain region (201), and be connected with silicon substrate substrate (101),
Described source region (202) is positioned at the inside of drift region (102), well region (103) and the second doped region (104a) are positioned at the drift region (102) of below, source region (202), and isolate by drift region (102) between silicon substrate substrate (101);
Field oxygen isolation (105) below of not injecting drift region (102) is formed with a plurality of isolation pressure rings (204).
7. the high withstand voltage field effect transistor domain structure of isolated form according to claim 6, it is characterized in that, described isolation pressure ring (204) comprises the 3rd doped region (104c) with first conduction type and the drift region with second conduction type, described the 3rd doped region (104c) is connected with an oxygen isolation (105), is silicon substrate substrate (101) between below, drift region and isolation pressure ring (204).
8. the according to claim 6 or 7 high withstand voltage field effect transistor domain structures of described isolated form, is characterized in that, described the first conduction type is the P type, and the second conduction type is N-type, and perhaps described the first conduction type is N-type, and the second conduction type is the P type.
9. the high withstand voltage field effect transistor domain structure of isolated form according to claim 7, is characterized in that, the spacing between described isolation pressure ring (204) is 1um～20um.
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| CN104465722B (en) * | 2014-12-09 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | High-voltage isolating ring structure |
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| CN112271210A (en) * | 2020-10-22 | 2021-01-26 | 吉林华微电子股份有限公司 | Semiconductor power and manufacturing method thereof |
| CN112909083A (en) * | 2021-02-26 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | High-voltage JFET device structure capable of improving voltage-withstanding reliability and manufacturing method thereof |
| CN112909083B (en) * | 2021-02-26 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | High-voltage JFET device structure for improving withstand voltage reliability and manufacturing method thereof |
| CN113851521A (en) * | 2021-08-20 | 2021-12-28 | 上海华虹宏力半导体制造有限公司 | High-voltage field effect tube structure for improving on-resistance characteristic and manufacturing method |
| CN113851521B (en) * | 2021-08-20 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | High-voltage field effect transistor structure for improving on-resistance characteristic and manufacturing method thereof |
| CN113948571A (en) * | 2021-10-18 | 2022-01-18 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN113948571B (en) * | 2021-10-18 | 2023-08-25 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
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