CN103095254A

CN103095254A - Pulse slide change signal generation circuit based on field programmable gate array (FPGA)

Info

Publication number: CN103095254A
Application number: CN2012105942626A
Authority: CN
Inventors: 王娜; 樊晓腾; 李增红; 左永峰; 刘亮; 周俊杰
Original assignee: CETC 41 Institute
Current assignee: CETC 41 Institute
Priority date: 2012-12-31
Filing date: 2012-12-31
Publication date: 2013-05-08

Abstract

The invention discloses a pulse slide change signal generation circuit based on a field programmable gate array (FPGA). The pulse slide change signal generation circuit solves the problems that an existing pulse circuit is limited by simulation circuit elements and cannot output high-accuracy and high-frequency pulse signals. The pulse slide change signal generation circuit based on the FPGA comprises a pulse sequence table random access memory (RAM) which is sued for set parameters, a pulse period counter, a pulse width counter and a pulse sequence generator. The pulse slide change signal generation circuit based on the FPGA can flexibly arrange various parameters of signals. An internal circuit of the FPGA is small in size, short in connection lines, small in distributed capacitance, so that power loss of a driving circuit is greatly reduced. Furthermore, external interference on the inside of an FPGA chip is small, and small work voltage can be utilized to reduce power loss. A core circuit is integrated in the FPGA so as to greatly improve product security degree.

Description

The sliding varying signal of a kind of pulse based on FPGA produces circuit

Technical field

The present invention relates to technical field of signal generation, particularly the sliding varying signal of a kind of pulse based on FPGA produces circuit.

Background technology

The sliding varying signal of pulse is widely used in the radar test technical field, than traditional simple pulse signal, the characteristics of the sliding varying signal of pulse are the pulse repetition period of signal to repeat lentamente to change with certain cycle, and this variation can be monotonic increase or monotone decreasing.The signal that the paired pulses repetition period increases progressively is that kick is to minimum value when the repetition period variation reaches maximum; And the signal that the pulse repetition period successively decreases, when the repetition period change reach minimum value be kick to maximum, restart afterwards a new period of change, this process constantly repeated with the fixing cycle.According to the demand that the radar test of different model is used, the pulse duration of the sliding varying signal of pulse and cycle and sliding change pattern are flexibility and changeabilities.

Traditional impulse circuit mainly is comprised of transistor and resistance capacitance, and its feature is: the transistor in impulse circuit is operated on off state.Another characteristics of impulse circuit are necessarily to have capacitor to make key element, and the generation of pulse, the conversion of waveform all be unable to do without discharging and recharging of capacitor.In most cases, transistor is operated in characteristic saturation region or cut-off region, in order to make transistor switch speed faster, also is added with speed-up capacitor on base stage, produces the forward spike at pulse front edge and can make transistor enter fast conducting and saturated; Producing the negative sense spike at pulse back edge makes transistor enter fast cut-off state.Therefore, traditional impulse circuit also is astatic multivibrator or is called for short multivibrator, but such circuit form is comparatively simple, the pulse signal underaction of generation; Be subjected to the restriction of analog circuit components and parts, also can't export high accuracy, high-frequency pulse signal, clearly can't satisfy the requirement of the sliding varying signal of pulse.

Summary of the invention

The present invention proposes the sliding varying signal of a kind of pulse based on FPGA and produces circuit, has solved the restriction that existing impulse circuit is subjected to the analog circuit components and parts, can't export the problem of high accuracy, high-frequency pulse signal.

Technical scheme of the present invention is achieved in that

The sliding varying signal of a kind of pulse based on FPGA produces circuit, comprising: the pulse train table RAM that parameter is set is generated by the MegaWizrd manager customization of QUARTUS II 7.2; Pulse period counter, its input load the cycle data of described pulse train table RAM output, and the meter spill-over goes out the spill over of a low pulse of rear generation, and with the reverse rear reference clock as its pulse number counter of this spill over; Pulse width counter, its input loads the pulse-width data of described pulse train table RAM output, its data clear terminal is by the RESET signal controlling of system, and the high impulse by the spill over of described pulse period counter output after is oppositely controlled and reloaded and begin to carry out once new counting process; Pulse-series generator, its reference clock is the reverse rear high impulse that produces of the spill over of described pulse period counter, its clear terminal arranges a decoding address co-controlling by RESET signal and the inside of system, and its output 10 bit data are as the address of described pulse train table RAM addressing; The external reference clock, the output reference clock is to the clock end of described pulse period counter, pulse width counter and pulse train table RAM.

Alternatively, described pulse train table RAM is read only memory ROM.

Alternatively, described pulse period counter is 32 digit counters, comprises trigger 74273, arithmetic unit 74181 and look ahead carry generator 74182.

Alternatively, described pulse width counter is 32 subtract counters, comprises trigger 74273 sum counters 74169.

Alternatively, pulse-series generator is to adopt the mould 10 of VHDL language design with interior Arbitrary Value Counter.

Alternatively, described external reference clock is the 100MHz reference clock.

The invention has the beneficial effects as follows:

(1) the various parameters of signal can arrange flexibly, can arrange arbitrarily in its scope separately such as the pulse duration of signal, repetition period etc.;

(2) the FPGA internal circuit is small-sized, and interconnection line is short, and distributed capacitance is little, and the required power consumption of drive circuit just reduces greatly, and fpga chip inside is subjected to extraneous interference very little, can adopt less operating voltage to reduce power consumption;

(3) the core circuit part all is integrated in FPGA inside, will greatly improve the privacy degrees of product;

(4) shorten the lead time, reduce design cost, come the Design ﹠ reform electronic product can reduce significantly area and the connector of printed board with FPGA, reduce assembling and debugging cost;

(5) use FPGA to improve design flexibility and reliability, avoided because the fault that causes due to rosin joint or loose contact occurs when assembling in printed board a large amount of discrete components and parts.

Description of drawings

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is the control block diagram that the sliding varying signal of a kind of pulse based on FPGA of the present invention produces circuit.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.

Traditional impulse circuit based on transistor and resistance capacitance composition, its central principle is to utilize discharging and recharging and transistorized conducting cut-off characteristics of capacitor, the major defect of this circuit is to use a large amount of analogue devices, circuit form is complicated, cost is high, and power consumption is high, and signal accuracy is low, index error.

The FPGA(field programmable gate array) by mask-programmable gate array and PLD(programmable logic device) develop, and characteristic is both combined, make high logic density and the versatility of the existing mask-programmable gate array of FPGA, the programmable features of PLD is arranged again.The development of FPAG technology makes logic gate number integrated on one single chip more and more, and the function that can realize becomes increasingly complex.Method design and development ASIC(application-specific integrated circuit (ASIC) that can be by hardware programming) chip, greatly improve chip development efficiency, reduce development cost.

The invention discloses the sliding varying signal of a kind of pulse based on FPGA and produce circuit, as shown in Figure 1, comprising: pulse-series generator 10, pulse train table RAM20, pulse period counter 30 and pulse width counter 40.

Pulse train table RAM20 is the MegaWizrd manager customization generation by QUARTUS II 7.2, can carry out setting parameter when production burst sequence table RAM20, comprise width, the degree of depth, same/asynchronous, Enable Pin, I/O is latched etc., pulse train table RAM20 supports initialize, initialization files are the .Mif file, so just can make a read only memory ROM to pulse sequence table RAM20, the data inside convenient change at any time.Pulse train table RAM20 be 32bit * 1024 with input end of clock, with the synchronous random access memory of read-write end, tape input output latch.The loading data of pulse train table RAM20 are to be generated by the impulse smaple maker of Software for Design, and it is determining the output of dissimilar guinea pig pulse signal.

Pulse period counter 30 is 32 digit counters, comprises trigger 74273, arithmetic unit 74181 and look ahead carry generator 74182.From the 100M reference clock 50 of outside input, be input to the clock end CLK of pulse period counter 30 and pulse width counter 40 as the reference clock after controlling selection.The input that 32 bit period data 80 in pulse train table RAM20 are loaded into the trigger 74273 of pulse period counter 30 latchs.Under next clock signal effect, pulse period counter 30 begins counting, and the meter spill-over goes out the spill over of a low pulse of rear generation, and this low pulse outputs to pulse width counter 40, as the loading enable signal LD of pulse width counter 40.When loading enable signal LD when low, pulse width counter 40 begins to load counting.The high impulse that produces after the spill over of low pulse is reverse often overflows once as the reference clock CLR of the pulse number counter (not shown in figure 1) in pulse period counter 30, and pulse number rolling counters forward value accumulates once.

Pulse width counter 40 is 32 subtract counters, comprises trigger 74273 sum counters 74169.FPGA inside arranges a decoding address as the data input latch signal, and gating this address is data input latch, and the input that 32 pulse-width datas 70 in pulse train table RAM20 is loaded into the trigger 74273 of pulse width counter 40 latchs.The data clear terminal of pulse width counter 40 is by the RESET signal controlling of system.Whenever pulse period counter 30 is completed a count cycle, the spill over of generation is low, and this spill over control impuls width counter 40 is completed the loading of data, and pulse width counter 40 reloaded and began to carry out once new counting process this moment.

Pulse-series generator 10 is to adopt the mould 10 of VHDL language design with interior Arbitrary Value Counter, than the graphic designs mode, the counter of design is more flexible in debugging and compiling like this, the input data of this counter are the count value of counter, reference clock CLK is the reverse rear high impulse that produces of the spill over of pulse period counter 30, and clear terminal arranges a decoding address co-controlling by RESET signal and inside.The every meter spill-over of pulse period counter 30 goes out once, the spill over that produces is oppositely rear completes the once cumulative process of counting as reference clock CLK

control impuls sequencer

10,10 bit data of pulse-series generator 10 output are as the address 60 of pulse train table RAM addressing, thus performance period, the controlled pulse output of pulse number.

requirement according to pulse train, pre-deposit the frequency word (being the pulse period) of each sequence that is drawn by the sliding algorithm that becomes of pulse in pulse train table RAM20, pulse duration, when analog pulse FPGA automatically from pulse train table RAM20 calling data to pulse period counter 30 and pulse width counter 40, pulse period counter 30 overflows and once is one-period, the spill over that produces control impuls width counter 40 is respectively counted, and the output valve of control impuls sequencer 10 adds up, make the address of pulse train table RAM20 addressing add 1, thereby read the cycle of next pulse, the pulsewidth parameter value, realize the sliding output of pulse signal that becomes of control able to programme.The pulsewidth scope that the sliding varying signal of pulse of the present invention produces the circuit generation is 20ns-42s, stepping 10ns, and the pulse period scope is 100ns-2s+10ns, stepping 10ns.Because external reference clock 50 is selected the 100MHz reference clock, the output reference clock signal is to the clock end CLK of pulse period counter 30, pulse width counter 40 and pulse train table RAM20, and the pulse signal precision of output can reach 10ns.

The sliding varying signal of pulse based on FPGA of the present invention produces circuit, and the various parameters of signal can arrange flexibly, and such as the pulse duration of signal, repetition period etc. can arrange arbitrarily in its scope separately; The FPGA internal circuit is small-sized, and interconnection line is short, and distributed capacitance is little, and the required power consumption of drive circuit just reduces greatly; Fpga chip inside is subjected to extraneous interference very little, can adopt less operating voltage to reduce power consumption; The core circuit part all is integrated in FPGA inside, will greatly improve the privacy degrees of product; Shorten the lead time; Reduce design cost, come the Design ﹠ reform electronic product can reduce significantly area and the connector of printed board with FPGA, reduce assembling and debugging cost; Use FPGA to improve design flexibility and reliability, avoided a large amount of discrete components and parts that the fault that causes due to rosin joint or loose contact occurs when assembling in printed board.

The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims

1. the sliding varying signal of the pulse based on FPGA produces circuit, it is characterized in that, comprising:

The pulse train table RAM that parameter is set is generated by the MegaWizrd manager customization of QUARTUS II 7.2;

Pulse period counter, its input load the cycle data of described pulse train table RAM output, and the meter spill-over goes out the spill over of a low pulse of rear generation, and with the reverse rear reference clock as its pulse number counter of this spill over;

Pulse width counter, its input loads the pulse-width data of described pulse train table RAM output, its data clear terminal is by the RESET signal controlling of system, and the high impulse by the spill over of described pulse period counter output after is oppositely controlled and reloaded and begin to carry out once new counting process;

Pulse-series generator, its reference clock is the reverse rear high impulse that produces of the spill over of described pulse period counter, its clear terminal arranges a decoding address co-controlling by RESET signal and the inside of system, and its output 10 bit data are as the address of described pulse train table RAM addressing;

The external reference clock, the output reference clock is to the clock end of described pulse period counter, pulse width counter and pulse train table RAM.

2. the sliding varying signal of the pulse based on FPGA as claimed in claim 1 produces circuit, it is characterized in that, described pulse train table RAM is read only memory ROM.

3. the sliding varying signal of the pulse based on FPGA as claimed in claim 1 produces circuit, it is characterized in that, described pulse period counter is 32 digit counters, comprises trigger 74273, arithmetic unit 74181 and look ahead carry generator 74182.

4. the sliding varying signal of the pulse based on FPGA as claimed in claim 1 produces circuit, it is characterized in that, described pulse width counter is 32 subtract counters, comprises trigger 74273 sum counters 74169.

5. the sliding varying signal of the pulse based on FPGA as claimed in claim 1 produces circuit, it is characterized in that, pulse-series generator is to adopt the mould 10 of VHDL language design with interior Arbitrary Value Counter.

6. the sliding varying signal of the pulse based on FPGA as described in claim 1 to 5 any one produces circuit, it is characterized in that, described external reference clock is the 100MHz reference clock.