CN103175614A - Sequential integrating two-color infrared focal plane reading circuit - Google Patents
Sequential integrating two-color infrared focal plane reading circuit Download PDFInfo
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- CN103175614A CN103175614A CN2013100891815A CN201310089181A CN103175614A CN 103175614 A CN103175614 A CN 103175614A CN 2013100891815 A CN2013100891815 A CN 2013100891815A CN 201310089181 A CN201310089181 A CN 201310089181A CN 103175614 A CN103175614 A CN 103175614A
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Abstract
The invention discloses a sequential integrating two-color infrared focal plane reading circuit which comprises an infrared detector, a pixel unit circuit, a medium and short wave column readout stage circuit and a medium and short wave output buffer. The pixel unit circuit comprises a medium and short wave two-way integral circuit and an M*N two-color pixel unit array of an integral capacitance selectable circuit; an integral signal generating circuit is arranged at the input terminal of the two-color pixel unit array; input signals of the integrating signal generating circuit comprise integral control signals INT and reset signals RST, and output signals of the integrating signal generating circuit comprise medium wave integral control signals INT1 and short wave integral control signals INT2 which are input into the two-color pixel unit array; the output terminal of the two-color pixel unit array is respectively connected with the medium and short wave column readout stage circuit; output signals of the medium and short wave column readout stage circuit are respectively connected with the input terminal of the medium and short wave output buffer; and the medium and short wave output buffer respectively outputs system serial output medium and short wave signals Vout1 and Vout2 to be served as medium and short wave detection information to be displayed, of a system.
Description
Technical field
The present invention relates to obtain in double-colored detection infrared imagery technique the technology of infrared image signal, relate in particular to a kind of order integral form Dual band IR circuit of focal plane readout, belong to photoelectron technology and microelectronics technology.
Background technology
Infrared imagery technique is just obtaining increasingly extensive application in military affairs, space technology, medical science and national economy association area.The infrared focal plane array assembly is the core light electrical part that obtains infrared image signal in infrared imagery technique.This assembly is comprised of infrared eye and infrared focal plane read-out circuit (ROIC:readout integrated circuits).
The ROIC circuit is that each function of focal plane is integrated in highly integrated circuit in single semi-conductor chip, and its basic function is to carry out the conversion of infrared acquisition signal, amplification and multipath transmission, is about to data and is transferred to successively output terminal from many detector ends.Each pixel cell of ROIC has specific detector, amplifier and switch.Existing ROIC circuit comprises that row selection signal produces circuit, array selecting signal and produces circuit, pixel unit circuit, row and read grade circuit and output buffer stage.Pixel unit circuit is the interface circuit of ROIC territory detector, for detector provides fixed-bias transistor circuit, and the current signal that detector collects is carried out photocurrent integration (changing into voltage as electric charge).
Existing infrared imaging system can only be obtained target information at a wave band, yet target object and environment take on a different character on radiation spectrum, so existing infrared imaging system is certainly existing a lot of deficiencies to the adaptation of complex environment and to the examination of decoy.Double-colored Detection Techniques are putting forward under such background just.The problem that how to design the Dual band IR circuit of focal plane readout corresponding with double-colored detection is also following.
Summary of the invention
The object of the invention is to address the above problem, a kind of order integral form Dual band IR circuit of focal plane readout is provided, it can be processed the detectable signal of medium short wave two-way detector output again and read.
The present invention adopts following technical scheme:
a kind of order integral form Dual band IR circuit of focal plane readout, comprise infrared eye, pixel unit circuit, row are read grade circuit and output buffer, it is characterized in that: pixel unit circuit is in comprising, the double-colored pixel unit array of the M*N of shortwave two-way integrating circuit and the optional circuit of integrating capacitor, row are read grade circuit and output buffer to be divided into the middle wave train and to read a grade circuit, the shortwave row are read a grade circuit, medium wave output buffer and shortwave output buffer, the input end of double-colored pixel unit array is provided with integrated signal and produces circuit, the input signal that integrated signal produces circuit is integral control signal INT and reset signal RST, the output signal that integrated signal produces circuit is that medium wave integral control signal INT1 and shortwave integral control signal INT2 all input to double-colored pixel unit array, the output of double-colored pixel unit array is connected respectively to the middle wave train and reads the input end that grade circuit and shortwave row are read grade circuit, the middle wave train is read the input end of the output signal connection medium wave output buffer of grade circuit, the shortwave row are read the input end of the output signal connection shortwave output buffer of grade circuit, medium wave output buffer output system serial output medium wave signal Vout1 shows as the medium wave detection information of system, shortwave output buffer output system serial output short-wave signal Vout2 shows as the shortwave detection information of system, wherein:
Integrated signal produces circuit and comprises three counters, be designated as respectively counter A, counter B, counter C, integral control signal INT, reset signal RST be the input end of linkage counter A respectively, the reset signal CLR difference linkage counter B of counter A output and the input end of counter C, reset signal RST, integral control signal INT be another two input ends of linkage counter B, counter C respectively, counter B output medium wave integral control signal INT1, counter C output shortwave integral control signal INT2;
counter A is the asynchronous counter of 2, comprise low, high-order two d type flip flops, two phase inverters and one two input and door, integral control signal INT connects the clock end of low level d type flip flop through a phase inverter, reset signal RST connects respectively low, the reset terminal of high-order two d type flip flops, the inverse output terminal of low level d type flip flop and data input pin interconnect and are connected to the clock end of high-order d type flip flop, the forward output terminal of low level d type flip flop is through connecting an input end of two inputs and door after another phase inverter, the inverse output terminal of high-order d type flip flop and data input pin interconnection, the forward output terminal of high-order d type flip flop connects another input end of two inputs and door, two inputs are output as reset signal CLR with door,
counter B is also the asynchronous counter of 2, comprise low, high-order two d type flip flops, three phase inverters, input and door and a three value and gate for one two, the reset signal CLR of reset signal RST sum counter A output inputs to two inputs and door simultaneously, two inputs with output be connected respectively after through a phase inverter low, the reset terminal of high-order two d type flip flops, integral control signal INT connects the clock end of low level d type flip flop, the inverse output terminal of low level d type flip flop and data input pin interconnect and are connected to the clock end of high-order d type flip flop, the forward output terminal of low level d type flip flop connects an input end of three value and gate, another input end of three value and gate connects integral control signal INT, the forward output terminal of high-order d type flip flop is through connecting the 3rd input end of three value and gate after another phase inverter, the inverse output terminal of high-order d type flip flop and data input pin interconnection, the output of three value and gate through the 3rd each and every one phase inverter after output medium wave integral control signal INT1,
counter C is also the asynchronous counter of 2, comprise low, high-order two d type flip flops, three phase inverters, input and door and a three value and gate for one two, the reset signal CLR of reset signal RST sum counter A output inputs to two inputs and door simultaneously, two inputs with output be connected respectively after through a phase inverter low, the reset terminal of high-order two d type flip flops, integral control signal INT connects the clock end of low level d type flip flop, the inverse output terminal of low level d type flip flop and data input pin interconnect and are connected to the clock end of high-order d type flip flop, the forward output terminal of low level d type flip flop is through connecting an input end of three value and gate after another phase inverter, another input end of three value and gate connects integral control signal INT, the 3rd input end of three value and gate connects the forward output terminal of high-order d type flip flop, the inverse output terminal of high-order d type flip flop and data input pin interconnection, the output of three value and gate through the 3rd each and every one phase inverter after output shortwave integral control signal INT2,
double-colored pixel unit array is provided with the capable * N row of a M pixel unit circuit, and medium wave the first every trade is selected signal HSEL1 (1), the second every trade is selected signal HSEL1(2) ... the M every trade is selected signal HSEL1(M) and shortwave the first every trade select signal HSEL2(1), the second every trade is selected signal HSEL2(2) ... the M every trade selects signal HSEL2 (M) to connect respectively the medium wave of the pixel unit circuit of corresponding row in the double-colored pixel unit array of M*N and the grid of shortwave line EAC, medium wave test signal TEST1, shortwave test signal TEST2, produced the medium wave integral control signal INT1 of circuit output by integrated signal, produced the shortwave integral control signal INT2 of circuit output by integrated signal, medium wave the first reset signal RESET1, shortwave the first reset signal RESET2, the optional signal ADDC1 of medium wave integrating capacitor, the optional signal ADDC2 of shortwave integrating capacitor connects respectively and comprises all medium wave test leads of each pixel unit circuit of optional double-colored pixel unit array of two-way integrating circuit and integrating capacitor, the shortwave test lead, medium wave integration control end, shortwave integration control end, the medium wave reset terminal, the shortwave reset terminal, the optional Capacity control end of medium wave integration and the optional Capacity control end of shortwave integration,
each pixel unit circuit comprises medium wave testing tube M11, medium wave ascending pipe M12, medium wave reset transistor M13, the optional pipe M14 of medium wave integrating capacitor, medium wave line EAC M15, medium wave integrating capacitor C11, C12, shortwave testing tube M21, shortwave ascending pipe M22, shortwave reset transistor M23, the optional pipe M24 of shortwave integrating capacitor, shortwave line EAC M25, shortwave integrating capacitor C21, C22 and Two-color Infrared Detectors, in each pixel unit circuit, power vd D connects the drain electrode of medium wave testing tube M11, and earth terminal GND connects the source electrode of shortwave testing tube M21, medium wave test signal TEST1, medium wave integral control signal INT1, medium wave the first reset signal RESET1, the optional signal ADDC1 of medium wave integrating capacitor connects respectively medium wave testing tube M11, medium wave ascending pipe M12, medium wave reset transistor M13, the grid of the optional pipe M14 of medium wave integrating capacitor, shortwave test signal TEST2, shortwave integral control signal INT2, shortwave the first reset signal RESET2, the optional signal ADDC2 of shortwave integrating capacitor connects respectively shortwave testing tube M21, shortwave ascending pipe M22, shortwave reset transistor M23, the grid of the optional pipe M24 of shortwave integrating capacitor, the capable gating signal HSEL1 of medium wave connects the grid of medium wave line EAC M15, the capable gating signal HSEL2 of shortwave connects the grid of shortwave line EAC M25, the source electrode of medium wave testing tube M11 connects the source electrode of medium wave ascending pipe M12, the drain electrode of shortwave testing tube M21 connects the source electrode of shortwave ascending pipe M22, the source electrode of the source electrode of medium wave ascending pipe M12 and shortwave ascending pipe M22 is connected to an end of Two-color Infrared Detectors jointly, the other end of Two-color Infrared Detectors connects common electric voltage Vcom, the drain electrode of medium wave ascending pipe M12 connects respectively medium wave reset transistor M13, the optional pipe M14 of medium wave integrating capacitor, the drain electrode of medium wave line EAC M15 and the end of integrating capacitor C11, the other end ground connection of integrating capacitor C11, the drain electrode of shortwave ascending pipe M22 connects respectively shortwave reset transistor M23, shortwave integrating capacitor choosing pipe M24, the drain electrode of shortwave line EAC M25 and the end of integrating capacitor C21, medium wave reset transistor M13 source ground, the other end of shortwave reset transistor M23 source electrode and capacitor C 21 all connects power vd D, the source electrode of the optional pipe M14 of medium wave integrating capacitor is through integrating capacitor C12 ground connection, the source electrode of the optional pipe M24 of shortwave integrating capacitor meets power vd D through integrating capacitor C22, the source electrode output medium wave integrated signal of medium wave line EAC M15, the source electrode output shortwave integrated signal of shortwave line EAC M25,
the middle wave train is read a grade circuit, the shortwave row are read a grade circuit, medium wave output buffer and shortwave output buffer are known circuits, the middle wave train is read grade circuit and is contained N identical middle wave train sensing element, the shortwave row are read grade circuit and are contained N identical shortwave row sensing element, the medium wave integrated signal of the medium wave line EAC source electrode output of all pixel unit circuits of same row is linked together and be connected to the middle wave train read grade circuit corresponding in wave train sensing element, the shortwave integrated signal of the shortwave line EAC source electrode output of all pixel unit circuits of same row is linked together and is connected to the shortwave row read the corresponding shortwave row of grade circuit sensing element, in all, the output terminal of wave train sensing element links together and is connected to the input end of medium wave output buffer, medium wave output buffer output system serial output medium wave signal Vout1, the output terminal of all shortwave row sensing elements links together and is connected to the input end of shortwave output buffer, shortwave output buffer output system serial output short-wave signal Vout2, during the optional signal ADDC1 of medium wave the second reset signal RESET11, medium wave integrating capacitor connects the wave train read each medium wave sensing element of grade circuit the optional Capacity control end of medium wave the second reset terminal, medium wave integration, shortwave the second reset signal RESET22, the optional signal ADDC1 of shortwave integrating capacitor connect the optional Capacity control end of shortwave the second reset terminal, shortwave integration that the shortwave row are read each shortwave sensing element of grade circuit.
Compared with prior art, the present invention has the following advantages:
1, circuit of the present invention can be processed the detectable signal of two wave bands simultaneously, has improved imaging system and screen the ability of target in the complicated applications environment.
2, the unique processing mode on circuit design of the present invention makes the two-way detectable signal of order integration can share an integral control signal, and this has improved the convenience of chip in system applies, has also improved the reliability of system simultaneously.
Description of drawings
Fig. 1 is the schematic block circuit diagram of order integral form Dual band IR circuit of focal plane readout of the present invention;
Fig. 2 is a pixel unit circuit figure;
Fig. 3 is the block diagram that integrated signal of the present invention produces circuit;
Fig. 4 is the circuit diagram that produces the counter A of reset signal;
Fig. 5 is the circuit diagram that produces the counter B of medium wave integrated signal;
Fig. 6 is the circuit diagram that produces the counter C of shortwave integrated signal;
Fig. 7 is that the present invention comprises the two-way pixel unit circuit, two-way is listed as the circuit diagram of reading grade circuit and two-way impact damper;
Fig. 8 is the sequential chart of the two-way integrated signal that produces under input integral control signal of the present invention;
Fig. 9 is a frame readout sequence figure of embodiment of the present invention 128*128 array;
Figure 10 is the readout sequence figure of delegation of embodiment of the present invention 128*128 array.
Embodiment
referring to Fig. 1, a kind of order integral form Dual band IR circuit of focal plane readout comprises the double-colored pixel unit array 1 that scale is M*N, integrated signal produces circuit 2, the middle wave train is read grade circuit 3, the shortwave row are read grade circuit 4, medium wave output buffer 5 and shortwave output buffer 6, medium wave the first every trade is selected signal HSEL1 (1), the second every trade is selected signal HSEL1(2) ... the M every trade is selected signal HSEL1(M), shortwave the first every trade is selected signal HSEL2(1), the second every trade is selected signal HSEL2(2) ... the M every trade selects signal HSEL2 (M) to meet respectively the capable choosing of medium wave and the capable input end that selects of shortwave that scale is the double-colored pixel unit circuit of M*N, medium wave test signal TEST1, shortwave test signal TEST2, medium wave integral control signal INT1, shortwave integral control signal INT2, medium wave the first reset signal RESET1, shortwave the first reset signal RESET2, the optional signal ADDC1 of medium wave integrating capacitor, the optional signal ADDC2 of shortwave integrating capacitor connects respectively and comprises all medium wave test leads of optional pixel unit circuit of two-way integrating circuit and integrating capacitor, the shortwave test lead, medium wave integration control end, shortwave integration control end, medium wave the first reset terminal, shortwave the first reset terminal, the optional Capacity control end of medium wave integration and the optional Capacity control end of shortwave integration, integral control signal INT, integrated signal produces circuit reset signal RST and meets respectively integral control signal end and the integrated signal generation circuit reset end that integrated signal produces circuit, medium wave the second reset signal RESET11, the optional signal ADDC1 of medium wave integrating capacitor connects medium wave the second reset terminal that the middle wave train is read grade circuit, the optional Capacity control end of medium wave integration, shortwave the second reset signal RESET22, the optional signal ADDC1 of shortwave integrating capacitor connects shortwave the second reset terminal that the shortwave row are read grade circuit, the optional Capacity control end of shortwave integration, the pixel cell voltage of N road column selection signal and double-colored pixel unit circuit output also connects the middle wave train and reads the input end that grade circuit and shortwave row are read grade circuit, the output signal that the middle wave train is read grade circuit connects the input end of medium wave output buffer, shortwave is listed as the input end that the output signal of reading grade circuit connects the shortwave output buffer, and medium wave output buffer output system serial output medium wave signal Vout1 shows as the medium wave detection information of system, shortwave output buffer output system serial output short signal Vout2 shows as the shortwave detection information of system.Two-way reset transistor in double-colored pixel unit array 1 respectively its separately reset signal RESET1 and the effect of RESET2 under to pixel unit circuit in M*N pixel cell carry out reset operation, guarantee the consistance of unit.The two-way integrating circuit of the pixel unit array 1 after resetting carries out integration operation in order under the control of separately integral control signal INT2 and INT2.After integration finishes, the 1st to walk to M capable of the capable two-way gating signal of i HSEL1(i), HSEL2(i) control under gating is effective successively, signal in the unit is transferred to row to be read grade circuit and carries out electric charge and distribute, at i row column selection messenger LSEL(i) control under, the middle wave train read grade circuit 3, shortwave row read grade circuit 4 respectively serial export medium wave output buffer 5 and shortwave output buffer 6 to, every row is read rear two-way column amplifier all will carry out one time reset operation.Medium wave output buffer 5 and shortwave output buffer 6 are the output amplifier, the two-way row are read the output signal serial output of level, improve simultaneously the drives ability.
Referring to Fig. 2, comprise two-way integrating circuit and integrating capacitor all optional pixel unit array 1 formed by M*N pixel cell, each pixel cell is made of medium wave testing tube M11, medium wave ascending pipe M12, medium wave reset transistor M13, the optional pipe M14 of medium wave integrating capacitor, medium wave line EAC M15, medium wave integrating capacitor C11, C12, shortwave testing tube M21, shortwave ascending pipe M22, shortwave reset transistor M23, the optional pipe M24 of shortwave integrating capacitor, shortwave line EAC M25, shortwave integrating capacitor C21, C22 and double-color detector each pixel cell.The test signal TEST1 of medium wave testing tube M11 connects noble potential when system works, and medium wave testing tube M11 closes, and shortwave test signal TEST2 is electronegative potential simultaneously, and shortwave testing tube M21 also closes.The electric current that medium wave integrating capacitor C11, C12 and shortwave integrating capacitor C21, C22 detect detector by the order of ascending pipe separately respectively under the control of digital controlled signal carries out integration.First work as example take medium wave and introduce integral process, medium wave ascending pipe M12 first opens under the control of medium wave integral control signal INT1, the electric current that detector detects is injected into medium wave integrating capacitor C11, C12 by medium wave ascending pipe M12, this moment, shortwave ascending pipe M22 closed, when the medium wave integration is complete, medium wave ascending pipe M12 can close under the control of INT1, open under the control of shortwave integral control signal INT2 every shortwave ascending pipe M22 after several clock period, shortwave integrating capacitor C21, C22 begin integration.Need to prove, the integral process of shortwave is a discharge process.In the image element circuit of the present invention's design, the two-way integrating circuit all has optional integrating capacitor, is in order to satisfy the requirement of different background like this.Medium wave reset transistor M13 and shortwave reset transistor M23 are controlled by medium wave reset signal RESET1 and shortwave reset signal RESET2 respectively, medium wave reset signal RESET1 and shortwave reset signal RESET2 are all pulse signals, in every frame readout, medium wave reset signal RESET1 and shortwave reset signal RESET2 are respectively electronegative potential and noble potential, after every frame data are read, reset signal RESET1 and shortwave reset signal RESET2 are respectively noble potential and electronegative potential, with all integrating capacitor zero clearings.Medium wave line EAC M15 and shortwave line EAC M25 read by row the capable two-way gating signal of the i HSEL1(i that select progressively and row selection signal produce circuit output) and HSEL2(i) control.Medium wave testing tube M11 and shortwave testing tube M21 are that functional test of the present invention has designed a kind of method of testing that a kind of analog photoelectricity stream injects, in the situation that system does not connect detector, the electric current shortwave test signal TEST2 that has medium wave test signal TEST1 to control medium wave testing tube M11 controls the electric current of shortwave testing tube M21, the electric current that analog prober is introduced greatly facilitates functional test.
Referring to Fig. 3-6, integrated signal produces circuit 2 and is comprised of 3 counters, be designated as respectively counter A, counter B, counter C, integral control signal INT, integrated signal produce the input end that circuit reset signal RST meets respectively counter A, the reset signal CLR of counter A output connects respectively the input end of counter B and counter C, and integrated signal produces the input end that circuit reset signal RST, control signal INT meet counter B, counter C respectively simultaneously.Counter B output medium wave integrated signal INT1, counter C output shortwave integrated signal INT2.counter A is the asynchronous counter of 2, consisted of the core of counting by two d type flip flops, integral control signal INT connects the clock end of low level d type flip flop through a phase inverter, the reverse output of low level d type flip flop meets the data input D of low level d type flip flop, the reverse output of high-order d type flip flop meets the data input D of high-order d type flip flop, the reverse output of low level d type flip flop connects the input end of clock of high-order d type flip flop, integrated signal produces the reset terminal that circuit reset signal RST connects low level d type flip flop and high-order d type flip flop simultaneously, the forward output of low level d type flip flop is carried out and the non-reset signal CLR that produces counter A output afterwards through the forward output of a phase inverter and high-order trigger, counter B is also the asynchronous counter of two, two d type flip flops consist of the core of counting, integrated signal produces the reset signal CLR phase of circuit reset signal RST and counter A output and the signal that obtains afterwards connects the reset terminal of two d type flip flops, the reverse output of low level d type flip flop meets the data input D of low level d type flip flop, the reverse output of high-order d type flip flop meets the data input D of high-order d type flip flop, the reverse output of low level d type flip flop connects the input end of clock of high-order d type flip flop, integral control signal INT connects the clock input of low level d type flip flop, the output of low level d type flip flop, the output of high-order d type flip flop is through phase inverter, three signal phases of integral control signal INT with obtain afterwards medium wave integral control signal INT1, counter C is also the asynchronous counter of two, two d type flip flops consist of the core of counting, integrated signal produces the reset terminal that reset signal CLR phase and the signal afterwards of circuit reset signal RST and counter A output connect two d type flip flops, the reverse output of low level d type flip flop meets the data input D of low level d type flip flop, the reverse output of high-order d type flip flop meets the data input D of high-order d type flip flop, the reverse output of low level d type flip flop connects the input end of clock of high-order d type flip flop, integral control signal INT connects the clock input of low level d type flip flop, the output of low level d type flip flop is through phase inverter, the output of high-order d type flip flop, three signal phases of integral control signal INT with obtain afterwards shortwave integral control signal INT2.
Referring to Fig. 7, with M=128, the pixel unit array of N=128 is that example further illustrates this working of an invention mode.
Scale is that the double-colored pixel unit circuit 1 of M*N is comprised of 128*128 pixel cell, and each pixel cell is made of medium wave testing tube M11, medium wave ascending pipe M12, medium wave reset transistor M13, the optional pipe M14 of medium wave integrating capacitor, medium wave line EAC M15, medium wave integrating capacitor C11, C12, shortwave testing tube M21, shortwave ascending pipe M22, shortwave reset transistor M23, the optional pipe M24 of shortwave integrating capacitor, shortwave line EAC M25, shortwave integrating capacitor C21, C22 and double-color detector (sensor).The test signal TEST1 of medium wave testing tube M11 connects noble potential when system works, and medium wave testing tube M11 closes, and shortwave test signal TEST2 is electronegative potential simultaneously, and shortwave testing tube M21 also closes.medium wave integrating capacitor C11, C12 and shortwave integrating capacitor C21, the electric current that C22 detects detector by the order of ascending pipe separately respectively under the control of digital controlled signal carries out integration, first work as example take medium wave and introduce integral process, medium wave ascending pipe M12 first opens under the control of medium wave integral control signal CHARGE1, the electric current that detector detects is injected into medium wave integrating capacitor C11 by medium wave ascending pipe M12, C12, this moment, shortwave ascending pipe M22 closed, when the medium wave integration is complete, medium wave ascending pipe M12 will close under the control of INT1, open under the control of shortwave integral control signal INT2 every shortwave ascending pipe M22 after several clock period, shortwave integrating capacitor C21, C22 begins integration.Need to prove, the integral process of shortwave is a discharge process.In the image element circuit of the present invention's design, the two-way integrating circuit all has optional integrating capacitor, is in order to satisfy the requirement of different background like this.Medium wave reset transistor M13 and shortwave reset transistor M23 are controlled by medium wave reset signal RESET1 and shortwave reset signal RESET2 respectively, medium wave reset signal RESET1 and shortwave reset signal RESET2 are all pulse signals, in every frame readout, medium wave reset signal RESET1 and shortwave reset signal RESET2 are respectively electronegative potential and noble potential, after every frame data are read, reset signal RESET1 and shortwave reset signal RESET2 are respectively noble potential and electronegative potential, with all integrating capacitor zero clearings.Medium wave line EAC M15 and shortwave line EAC M25 read by row the capable two-way gating signal of the i HSEL1(i that select progressively and row selection signal produce circuit output) and HSEL2(i) control.Medium wave testing tube M11 and shortwave testing tube M21 are that functional test of the present invention has designed a kind of method of testing that a kind of analog photoelectricity stream injects, in the situation that system does not connect detector, the electric current shortwave test signal TEST2 that has medium wave test signal TEST1 to control medium wave testing tube M11 controls the electric current of shortwave testing tube M21, the electric current that analog prober is introduced greatly facilitates functional test.
The middle wave train is read grade circuit 3, the shortwave row are read grade circuit 4, medium wave output buffer 5 and shortwave output buffer 6 and are known circuits.the middle wave train is read grade circuit and is made of N identical sensing element, each sensing element is by medium wave column operations amplifier, the medium wave feedback capacity, medium wave feedback capacity reset transistor, the optional electric capacity of medium wave, the optional electric capacity gate tube of medium wave, the two ends of medium wave feedback capacity are connected on respectively inverting input and the output terminal of medium wave column operations amplifier, the drain electrode of medium wave feedback capacity reset transistor and source electrode are connected on respectively inverting input and the output terminal of medium wave column operations amplifier, the drain electrode of the optional electric capacity gate tube of medium wave is connected on the inverting input of medium wave column operations amplifier, the source electrode of the optional electric capacity gate tube of medium wave connects a section of the optional electric capacity of medium wave, the output terminal of another termination medium wave column operations amplifier of the optional electric capacity of medium wave.
the shortwave row are read grade circuit and are made of N identical sensing element, each sensing element is by shortwave column operations amplifier, the shortwave feedback capacity, shortwave feedback capacity reset transistor, the optional electric capacity of shortwave, the optional electric capacity gate tube of shortwave, the two ends of shortwave feedback capacity are connected on respectively inverting input and the output terminal of shortwave column operations amplifier, the drain electrode of shortwave feedback capacity reset transistor and source electrode are connected on respectively inverting input and the output terminal of shortwave column operations amplifier, the drain electrode of the optional electric capacity gate tube of shortwave is connected on the inverting input of shortwave column operations amplifier, the source electrode of the optional electric capacity gate tube of shortwave connects a section of the optional electric capacity of shortwave, the output terminal of another termination operational amplifier of the optional electric capacity of shortwave.
Medium wave output buffer and shortwave output buffer consist of by the operational amplifier of an input end and output terminal short circuit.
The output terminal that the middle wave train is read the medium wave column operations amplifier of the identical sensing element of the N of grade circuit connects the input end of medium wave output buffer separately through a switching tube.
The output terminal that the middle wave train is read the shortwave column operations amplifier of the identical sensing element of the N of grade circuit connects the input end of shortwave output buffer separately through a switching tube.
In all pixel unit circuits of same row, the drain electrode of medium wave line EAC connects the middle wave train and reads the first reverse input end of calculating amplifier of the middle wave train in row sensing element corresponding to these row of grade circuit, and the first positive input of calculating amplifier of the middle wave train connects reference level Vref 1.
In all pixel unit circuits of same row, the drain electrode of shortwave line EAC connects the first reverse input end of calculating amplifier of the short-and-medium wave train of row sensing element that the shortwave row are read this row correspondence of grade circuit, and the positive input that shortwave is listed as unit's calculation amplifier connects reference level Vref 2.
The middle wave train is read grade circuit 3 and shortwave row and is read grade circuit 4 and complete the process that the electric signal in pixel cell shifts and reads.At the capable gating signal HSEL1(i of the capable two-way of i), HSEL2(i) effectively the time, the electric capacity that the electric charge of collecting between two-way integrating capacitor integration period in this row pixel cell and two-way row are read in grade circuit carries out the electric charge reallocation, reads grade circuit and shortwave row by the middle wave train and reads grade circuit and realize that electric charge is to the conversion of voltage.Two-way row amplifier reset signal is controlled respectively the reset transistor that the two-way row are read grade circuit, after every delegation reads, all row amplifiers is carried out reset operation, and resetting voltage is the reference voltage Vref of row amplifier.Medium wave output buffer 5 and shortwave output buffer 6 are the output amplifier, row are read the output signal serial output of level, improve simultaneously the driving force of circuit.
The working condition of Fig. 7 is as follows:
Scale be the double-colored pixel unit circuit 1 of M*N medium wave reset transistor, shortwave reset transistor respectively under the effect of reset signal RESET1 and RESET2 separately to pixel unit circuit in 128*128 pixel cell carry out reset operation, guarantee the consistance of unit.The rear scale that resets is that two-way integrating circuit order under the control of integral control signal INT1 and INT2 separately of the double-colored pixel unit circuit 1 of M*N is carried out integration, and whether the two-way integrating circuit all can select to allow the optional electric capacity of integration participate in integration operation as required in this process of integration operation.After integration finishes, at the capable two-way gating signal HSEL1(i of i), HSEL2(i) control under the 1st walk to the 128th row gating be effective successively, two paths of signals in the unit is transferred to respectively two-way row to be read grade circuit and carries out the electric charge reallocation, at j column selection messenger LSEL(j) control under, two-way row read that in grade circuit, output signal exports respectively two-way output buffer stage to from the 1st row to the 128th row serial, and every row is read rear two-way column amplifier all will carry out one time reset operation.Medium wave output buffer 5 and shortwave output buffer 6 are the output amplifier, row are read the output signal serial output of level, improve simultaneously driving force.So far complete the operation of a frame, next constantly repeated said process.
Fig. 8 has provided the sequential chart of the two-way integrated signal that produces under input integral control signal of the present invention; Fig. 9 has provided a frame readout sequence figure of order integral form Dual band IR circuit of focal plane readout 128*128 array of the present invention; Figure 10 is the readout sequence figure of delegation of order integral form Dual band IR circuit of focal plane readout 128*128 array of the present invention.
Claims (1)
1. order integral form Dual band IR circuit of focal plane readout, comprise infrared eye, pixel unit circuit, row are read grade circuit and output buffer, it is characterized in that: pixel unit circuit is in comprising, the double-colored pixel unit array of the M*N of shortwave two-way integrating circuit and the optional circuit of integrating capacitor, row are read grade circuit and output buffer to be divided into the middle wave train and to read a grade circuit, the shortwave row are read a grade circuit, medium wave output buffer and shortwave output buffer, the input end of double-colored pixel unit array is provided with integrated signal and produces circuit, the input signal that integrated signal produces circuit is integral control signal INT and reset signal RST, the output signal that integrated signal produces circuit is that medium wave integral control signal INT1 and shortwave integral control signal INT2 all input to double-colored pixel unit array, the output of double-colored pixel unit array is connected respectively to the middle wave train and reads the input end that grade circuit and shortwave row are read grade circuit, the middle wave train is read the input end of the output signal connection medium wave output buffer of grade circuit, the shortwave row are read the input end of the output signal connection shortwave output buffer of grade circuit, medium wave output buffer output system serial output medium wave signal Vout1 shows as the medium wave detection information of system, shortwave output buffer output system serial output short-wave signal Vout2 shows as the shortwave detection information of system, wherein:
Integrated signal produces circuit and comprises three counters, be designated as respectively counter A, counter B, counter C, integral control signal INT, reset signal RST be the input end of linkage counter A respectively, the reset signal CLR difference linkage counter B of counter A output and the input end of counter C, reset signal RST, integral control signal INT be another two input ends of linkage counter B, counter C respectively, counter B output medium wave integral control signal INT1, counter C output shortwave integral control signal INT2;
counter A is the asynchronous counter of 2, comprise low, high-order two d type flip flops, two phase inverters and one two input and door, integral control signal INT connects the clock end of low level d type flip flop through a phase inverter, reset signal RST connects respectively low, the reset terminal of high-order two d type flip flops, the inverse output terminal of low level d type flip flop and data input pin interconnect and are connected to the clock end of high-order d type flip flop, the forward output terminal of low level d type flip flop is through connecting an input end of two inputs and door after another phase inverter, the inverse output terminal of high-order d type flip flop and data input pin interconnection, the forward output terminal of high-order d type flip flop connects another input end of two inputs and door, two inputs are output as reset signal CLR with door,
counter B is also the asynchronous counter of 2, comprise low, high-order two d type flip flops, three phase inverters, input and door and a three value and gate for one two, the reset signal CLR of reset signal RST sum counter A output inputs to two inputs and door simultaneously, two inputs with output be connected respectively after through a phase inverter low, the reset terminal of high-order two d type flip flops, integral control signal INT connects the clock end of low level d type flip flop, the inverse output terminal of low level d type flip flop and data input pin interconnect and are connected to the clock end of high-order d type flip flop, the forward output terminal of low level d type flip flop connects an input end of three value and gate, another input end of three value and gate connects integral control signal INT, the forward output terminal of high-order d type flip flop is through connecting the 3rd input end of three value and gate after another phase inverter, the inverse output terminal of high-order d type flip flop and data input pin interconnection, the output of three value and gate through the 3rd each and every one phase inverter after output medium wave integral control signal INT1,
counter C is also the asynchronous counter of 2, comprise low, high-order two d type flip flops, three phase inverters, input and door and a three value and gate for one two, the reset signal CLR of reset signal RST sum counter A output inputs to two inputs and door simultaneously, two inputs with output be connected respectively after through a phase inverter low, the reset terminal of high-order two d type flip flops, integral control signal INT connects the clock end of low level d type flip flop, the inverse output terminal of low level d type flip flop and data input pin interconnect and are connected to the clock end of high-order d type flip flop, the forward output terminal of low level d type flip flop is through connecting an input end of three value and gate after another phase inverter, another input end of three value and gate connects integral control signal INT, the 3rd input end of three value and gate connects the forward output terminal of high-order d type flip flop, the inverse output terminal of high-order d type flip flop and data input pin interconnection, the output of three value and gate through the 3rd each and every one phase inverter after output shortwave integral control signal INT2,
double-colored pixel unit array is provided with the capable * N row of a M pixel unit circuit, and medium wave the first every trade is selected signal HSEL1 (1), the second every trade is selected signal HSEL1(2) ... the M every trade is selected signal HSEL1(M) and shortwave the first every trade select signal HSEL2(1), the second every trade is selected signal HSEL2(2) ... the M every trade selects signal HSEL2 (M) to connect respectively the medium wave of the pixel unit circuit of corresponding row in the double-colored pixel unit array of M*N and the grid of shortwave line EAC, medium wave test signal TEST1, shortwave test signal TEST2, produced the medium wave integral control signal INT1 of circuit output by integrated signal, produced the shortwave integral control signal INT2 of circuit output by integrated signal, medium wave the first reset signal RESET1, shortwave the first reset signal RESET2, the optional signal ADDC1 of medium wave integrating capacitor, the optional signal ADDC2 of shortwave integrating capacitor connects respectively and comprises all medium wave test leads of each pixel unit circuit of optional double-colored pixel unit array of two-way integrating circuit and integrating capacitor, the shortwave test lead, medium wave integration control end, shortwave integration control end, the medium wave reset terminal, the shortwave reset terminal, the optional Capacity control end of medium wave integration and the optional Capacity control end of shortwave integration,
each pixel unit circuit comprises medium wave testing tube M11, medium wave ascending pipe M12, medium wave reset transistor M13, the optional pipe M14 of medium wave integrating capacitor, medium wave line EAC M15, medium wave integrating capacitor C11, C12, shortwave testing tube M21, shortwave ascending pipe M22, shortwave reset transistor M23, the optional pipe M24 of shortwave integrating capacitor, shortwave line EAC M25, shortwave integrating capacitor C21, C22 and Two-color Infrared Detectors, in each pixel unit circuit, power vd D connects the drain electrode of medium wave testing tube M11, and earth terminal GND connects the source electrode of shortwave testing tube M21, medium wave test signal TEST1, medium wave integral control signal INT1, medium wave the first reset signal RESET1, the optional signal ADDC1 of medium wave integrating capacitor connects respectively medium wave testing tube M11, medium wave ascending pipe M12, medium wave reset transistor M13, the grid of the optional pipe M14 of medium wave integrating capacitor, shortwave test signal TEST2, shortwave integral control signal INT2, shortwave the first reset signal RESET2, the optional signal ADDC2 of shortwave integrating capacitor connects respectively shortwave testing tube M21, shortwave ascending pipe M22, shortwave reset transistor M23, the grid of the optional pipe M24 of shortwave integrating capacitor, the capable gating signal HSEL1 of medium wave connects the grid of medium wave line EAC M15, the capable gating signal HSEL2 of shortwave connects the grid of shortwave line EAC M25, the source electrode of medium wave testing tube M11 connects the source electrode of medium wave ascending pipe M12, the drain electrode of shortwave testing tube M21 connects the source electrode of shortwave ascending pipe M22, the source electrode of the source electrode of medium wave ascending pipe M12 and shortwave ascending pipe M22 is connected to an end of Two-color Infrared Detectors jointly, the other end of Two-color Infrared Detectors connects common electric voltage Vcom, the drain electrode of medium wave ascending pipe M12 connects respectively medium wave reset transistor M13, the optional pipe M14 of medium wave integrating capacitor, the drain electrode of medium wave line EAC M15 and the end of integrating capacitor C11, the other end ground connection of integrating capacitor C11, the drain electrode of shortwave ascending pipe M22 connects respectively shortwave reset transistor M23, shortwave integrating capacitor choosing pipe M24, the drain electrode of shortwave line EAC M25 and the end of integrating capacitor C21, medium wave reset transistor M13 source ground, the other end of shortwave reset transistor M23 source electrode and capacitor C 21 all connects power vd D, the source electrode of the optional pipe M14 of medium wave integrating capacitor is through integrating capacitor C12 ground connection, the source electrode of the optional pipe M24 of shortwave integrating capacitor meets power vd D through integrating capacitor C22, the source electrode output medium wave integrated signal of medium wave line EAC M15, the source electrode output shortwave integrated signal of shortwave line EAC M25,
the middle wave train is read a grade circuit, the shortwave row are read a grade circuit, medium wave output buffer stage and shortwave output buffer stage are known circuits, the middle wave train is read grade circuit and is contained N identical middle wave train sensing element, the shortwave row are read grade circuit and are contained N identical shortwave row sensing element, the medium wave integrated signal of the medium wave line EAC source electrode output of all pixel unit circuits of same row is linked together and be connected to the middle wave train read grade circuit corresponding in wave train sensing element, the shortwave integrated signal of the shortwave line EAC source electrode output of all pixel unit circuits of same row is linked together and is connected to the shortwave row read the corresponding shortwave row of grade circuit sensing element, in all, the output terminal of wave train sensing element links together and is connected to the input end of medium wave output buffer, medium wave output buffer output system serial output medium wave signal Vout1, the output terminal of all shortwave row sensing elements links together and is connected to the input end of shortwave output buffer, shortwave output buffer output system serial output short-wave signal Vout2, during the optional signal ADDC1 of medium wave the second reset signal RESET11, medium wave integrating capacitor connects the wave train read each medium wave sensing element of grade circuit the optional Capacity control end of medium wave the second reset terminal, medium wave integration, shortwave the second reset signal RESET22, the optional signal ADDC1 of shortwave integrating capacitor connect the optional Capacity control end of shortwave the second reset terminal, shortwave integration that the shortwave row are read each shortwave sensing element of grade circuit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104458004A (en) * | 2014-11-25 | 2015-03-25 | 中国电子科技集团公司第十一研究所 | Double-spectral-section monolithic integration linear array type infrared focal plane readout circuit and design method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412533A (en) * | 2002-11-20 | 2003-04-23 | 中国科学院上海技术物理研究所 | Reading circuit structure of double-colour line-array infrared focus plane detector |
| CN1455585A (en) * | 2003-06-18 | 2003-11-12 | 北京大学 | Readout circuit of focal plane for quick-flasing charge amplifying structure and its readout method |
| US6870565B1 (en) * | 1998-11-24 | 2005-03-22 | Micron Technology, Inc. | Semiconductor imaging sensor array devices with dual-port digital readout |
| CN101009762A (en) * | 2007-01-26 | 2007-08-01 | 东南大学 | Read-out circuit of infrared focal plane |
| US8481941B2 (en) * | 2011-05-02 | 2013-07-09 | National Chi Nan University | Dual function injection type array readout device and circuit and dual function readout module |
-
2013
- 2013-03-20 CN CN201310089181.5A patent/CN103175614B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6870565B1 (en) * | 1998-11-24 | 2005-03-22 | Micron Technology, Inc. | Semiconductor imaging sensor array devices with dual-port digital readout |
| CN1412533A (en) * | 2002-11-20 | 2003-04-23 | 中国科学院上海技术物理研究所 | Reading circuit structure of double-colour line-array infrared focus plane detector |
| CN1455585A (en) * | 2003-06-18 | 2003-11-12 | 北京大学 | Readout circuit of focal plane for quick-flasing charge amplifying structure and its readout method |
| CN101009762A (en) * | 2007-01-26 | 2007-08-01 | 东南大学 | Read-out circuit of infrared focal plane |
| US8481941B2 (en) * | 2011-05-02 | 2013-07-09 | National Chi Nan University | Dual function injection type array readout device and circuit and dual function readout module |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104458004A (en) * | 2014-11-25 | 2015-03-25 | 中国电子科技集团公司第十一研究所 | Double-spectral-section monolithic integration linear array type infrared focal plane readout circuit and design method |
| CN104458004B (en) * | 2014-11-25 | 2017-08-08 | 中国电子科技集团公司第十一研究所 | Bispectrum section single-chip integration line type infrared focal plane read-out circuit and design method |
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