CN103176752A - Super-endurance solid-state drive with Endurance Translation Layer (ETL) and diversion of temp files for reduced Flash wear - Google Patents
Super-endurance solid-state drive with Endurance Translation Layer (ETL) and diversion of temp files for reduced Flash wear Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
- G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2015—Redundant power supplies
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
- G06F2211/10—Indexing scheme relating to G06F11/10
- G06F2211/1002—Indexing scheme relating to G06F11/1076
- G06F2211/109—Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
Abstract
A flash drive provided by the present invention has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table (that stores the data-type bits and pointers to data or tables in DRAM). Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
Description
Present patent application is relevant
[the 1st section] this application is the part continuity in " the multi-level band of flash memory system and block channel-equalization " (United States serial 12/475,457, May 29 2009 date of application).
[the 2nd section] this application is the part continuity of " having combined flash to write in the flash memory system of command queue closes occuring simultaneously of part mapping table " (sequence number 12/347,306, on Dec 31 2008 date of application, Application No. is 8112574).
[the 3rd section] this application is the part continuity in " based on the storage system of high-performance, high persistence nonvolatile memory " (United States serial 12/141,879, June 18 2008 date of application).
[the 4th section] this application is relevant with " high persistence nonvolatile memory " (United States serial 7,953,931, February 21 2008 date of application).
[the 5th section] this application is relevant with " reference voltage that the unit that reduces the multi-bit cell flash memory is intensive, adjust the multi-bit cell flash memory " (U.S. Patent number 7,333,364, April 19 2007 date of application).
Technical field
[the 6th section] the present invention is relevant with flash drives, especially increases relevant with life with the persistence of flash drives.
Background technology
[the 7th section] flash memory is widely used in the Peripheral storage in computer system, even is used for the primary storage of portable set.1987, Fujio doctor Masuoka of Toshiba invented the NAND flash memory.Flash memory adopts with charge storage the EEPROM (Electrically Erasable Programmable Read Only Memo) on floating grid (EEPROM) unit.Memory cell is usually by avalanche current programming, then utilizes wearing tunnel (passing very thin oxide layer) effect and be wiped free of in quantum mechanics.Unfortunately, in the process of programming or wiping, some electronics may be trapped in very thin oxide layer.In programming cycle subsequently, these stranded electronics will reduce the electric charge of storing in the unit, suppose a constant program voltage.Generally, the rising program voltage is to compensate stranded electronics.
Due to the increase of density and the size of flash memory, the size of storage unit is shunk [the 8th section].The thickness that comprises the oxide of tunnel oxide also decreases.Oxide is thinner, and electric charge more easily is captured, and sometimes also more easily breaks down.The floating grid of NAND flash memory is used for trapped electron.The quantity of the electronics in floating grid may affect the voltage level of output.Can obtain different voltage levels by controlling the number that locks into the electronics of depletion layer in ablation process.Less floating grid zone often limit can captive electronics (only having now a hundreds of electronics) maximum quantity.Owing to programming/reading interference, electronics may leak into floating grid or be caught by floating grid.The variation of electron number can have influence on the variation of Voltage-output level, and then changes reading result.
The quantity of programming-erase cycle that [the 9th section] flash memory can bear is about 100,000 times, and this makes and becomes possibility than the long life under normal read-write condition.Yet, distressfully be, less flashing storage unit has experienced more serious wearing and tearing, for two-layer unit, newer flash memory can bear and be less than programming-erase cycle 10,000 times, and for three-layer unit (TLC), newer flash memory can bear about 600 programming-erase cycle.If present trend continues, following flash memory may only allow programming-erase cycle 300 times.So low persistence may seriously limit the application of flash memory, and the application generation of solid magnetic disc is had a strong impact on.
One of method of the density of [the 10th section] increase flash memory will make more than one of each cell stores exactly.The different voltage levels of storage unit are assigned to different multiple bit values, distribute four voltage ranges as giving the unit of two.Yet although the noise margin of multilevel-cell (MLC) and three-layer unit (TLC) flash memory technology has reduced, persistent problem is aggravated.
[the 11st section] future, the persistence of bottom flash memory technology will be more and more lower.By various technology, flash drives can compensate the lower mar proof of bottom flash memory.For example, dynamic random storage (DRAM) buffer zone that is used for the data storage on flash drives can serve as write-back cache, when main frame is carried out write operation to identical Data Position, reduces the number of times that writes the bottom flash memory.
We the flash drives of expectation can overcome lower this problem of wearing and tearing persistence of bottom flash memory device [the 12nd section].The super persistence flash drives that we wish adopts a series of advanced management technology, and these administrative skills make the quantity that writes that arrives flash memory reduce, thereby reduces the quantity of programming-erase cycle on the bottom flash memory.We construct a super durable flash drives from low persistence flash memory at expectation.
Description of drawings
[the 13rd section] Fig. 1 is the block scheme that uses the super durable flash drives of low persistence flash memory.
[the 14th section] Fig. 2 A-C emphasizes the independent management of temporary file, to avoid that temporary file is write flash memory.
[the 15th section] Fig. 3 is memory map, has represented various types of data are stored in durable conversion layer (ETL) in intelligent storage switch (SSS) DRAM impact damper.
[the 16th section] Fig. 4 A-B is for using the standby partial block that excessively writes with the swap block piece of persistence.
[the 17th section] Fig. 5 is piece mapping, page-map and sector map.
[the 18th section] Fig. 6 has shown in super durable flash drives the map entry to different data types.
[the 19th section] Fig. 7 has shown complete page mapping and the mapping of part page of the paging file that uses unified mapping table and sub-sector map.
[the 20th section] Fig. 8 has shown file allocation table (FAT) mapping in unified mapping table.
[the 21st section] Fig. 9 A has shown the mapping of compressed page.
[the 22nd section] Fig. 9 B emphasizes the data stream of user data in the DRAM impact damper.
[the 23rd section] Fig. 9 C emphasizes the data stream of pagefile and temporary file in the DRAM impact damper.
[the 24th section] Figure 10 is one and according to host requests, the data type classified, and the process flow diagram that the files such as the pagefile of user data process, temporary file, FAT, file description block (FDB) are dispatched.
[the 25th section] Figure 11 shows and has shown a process that reads pagefile, temporary file or FDB file.
[the 26th section] Figure 12 A-C shows a process that is used for writing pagefile, temporary file or FDB file.
[the 27th section] Figure 13 A-B has shown a FAT path that leads to super durable flash drives.
[the 28th section] Figure 14 has shown the super durable flash drives subscriber data file how processing host reads.
[the 29th section] Figure 15 A-I has shown the how subscriber data file that writes in frequent access region and non-frequent access region of processing host of super durable flash drives.
[the 30th section] Figure 16 is a process flow diagram that shows old sector scale removal process.
[the 31st section] Figure 17 A-E uses frequent access (FA) high-speed cache and non-frequent access (NFA) high-speed cache of complete page and part page to carry out the process flow diagram that user data is processed.
[the 32nd section] Figure 18 A-B has shown the processing of encrypting the page and compressed page.
[the 33rd section] Figure 19 A-D has shown detection and the processing procedure of the bad page and bad piece.
[the 34th section] Figure 20 A-C has shown mapping table and other DRAM zone has been carried out initialized power up.
[the 35th section] Figure 21 is the process flow diagram of power process.
[the 36th section] Figure 22 A-B has shown multistage error correcting code (ECC) fetch program.
[the 37th section] Figure 23 A-B has shown the multistage ECC fetch program of simplifying.
[the 38th section] Figure 24 A-B has shown the reference voltage migration program.
[the 39th section] Figure 25 has shown how data are written in the flash memory of protective condition raising.
Summary of the invention describes in detail
[the 40th section] the present invention improves relevant with the persistence of flash drives.By providing following description, be intended to make those skilled in the art can make and use the present invention in application-specific and under requiring.Various modifications to preferred embodiment will be apparent for those skilled in the art, and rule defined herein can be applied in other embodiment.Therefore, the specific embodiment that the invention is not restricted to show with describe, but should be endowed consistent with principle disclosed herein and novel features wide region.
[the 41st section] writes the wearing and tearing that can reduce the bottom flash memory device by stoping unnecessary flash memory.DRAM impact damper in flash drives can be stored those does not need permanent storage and the data that therefore do not need to be written to flash memory.DRAM is not only faster, can also write over 1,000,000 times more.1966, DRAM stepped on Nader's invention by the Robert of IBM.When the user surfed the web or moves some tediously long application program, typical main frame can create a lot of unessential temporary files.The inventor recognizes, these files do not need to be written into flash memory, to reduce the wear intensity of flash memory.
[the 42nd section] typical system also can frequently cover the data of some type.These data that frequently covered preferably are stored in the impact damper of DRAM of flash drives, and according to a rule (as the time based on passage, the capacity of distribution etc.) or copy to flash memory according to outage or power fail.In power down, store these data that frequently covered into flash memory and also can significantly reduce the wearing and tearing of flash memory device.
[the 43rd section] these data that frequently covered may comprise the journal file of the frequent updating along with the appearance of new events.Usually, after system crash, up-to-date copy is checked.File allocation table (FAT) is another position that is frequently covered, because can be along with document creation or expansion and upgraded in this position.FAT is the interior nonresident portion of a less, if but each of FAT more is copied to flash memory in new capital, and its frequent visit can significantly increase the wearing and tearing of flash memory.File description block (FDB) is a similar structures that quilt frequently covers.FDB/FAT keeps the metadata from the file system of main frame.Various forms and DRAM impact damper are used together, create metadata, " file system " stored into DRAM and flash memory.If certain logical address (LBA) goes out the unjustified situation of current address, thereby before writing in the sub-mapping table of FDB/ in the sub-mapping table of FAT/ being intended to improve convenient not the visiting of write efficiency in the FAT zone or FDB zone, LBA (Logical Block Addressing) is added to a side-play amount, makes the page address boundary alignment in LBA (Logical Block Addressing) and flash memory.
[the 44th section] need to be according to rule (as the time based on passage, the capacity that distributes etc.) or in off-position/electric energy loss, the alternative document that bad block table, erase counters, refuse collection, mapping table and flash drives are produced stores flash memory into.Also can or in off-position/electric energy loss, the flash memory system meta file be stored into the DRAM impact damper and copy to flash memory according to rule (as the time based on passage, the capacity of distribution etc.), to reduce the flash memory wearing and tearing.Form above-mentioned and meta file are to be stored into flash memory under the condition of energising.In the time of device initialize, they are loaded into the impact damper of DRAM.Subsequently, the read/write of host data has changed the content of these data.When the situation of outage/electric energy loss occurring, the form that those are invalid and meta file need to be written into or backup in flash memory in stripe cell.In power fail, write buffer memory, fifo buffer, data input buffer district (DIB), persistence standby/host data of swap block (SPARE/SWAP piece) and other flash drives impact dampers also can copy to flash memory, so that system's recovery, if certain application-specific needs definite system's recovery point.
[the 45th section] another kind of method is to guarantee that the relevant data in the ETL of DRAM is copied to MLC.In the situation that powered-down, the valid data copy in ETL can be kept in MLC.When being electrified, the data in ETL can be re-loaded to DRAM from MLC.By recording difference, can revise the method for copy, thereby reduce the quantity of the data that copy, reduce to the MLC data writing.
Part mapping table in the ETL of [the 46th section] DRAM impact damper only has the entry (total N group mapping table) of 1 group of mapping table.Other N-1 group mapping table is stored in flash memory, and when the part mapping table occured to omit, they just can be sent to the DRAM impact damper.
[the 47th section] when being moved on hard disk or flash drives on the image ordinary practice of the main DRAM internal memory of main frame, system will use pagefile for memory management.If cause page swap file to be lost because of power fail, there is no much relations yet, because anyway need restarting systems, reinitialize memory management and paging system, the pagefile of any storage of deletion.In power-off/electric energy loss, in order to reduce the flash memory wearing and tearing, these pagefiles also can be stored in the DRAM impact damper, and might not copy in flash memory.
When [the 48th section] main frame sends request to flash drives, often follow the sequence of rules of data type.For example, at first main frame can access FAT, then accesses FDB, then reads or write certain data file.This cyclic sequence can help a super persistent flash drives that the data type is classified.FAT is always a predetermined memory location that depends on the type (Windows, Linux, apple OS, Android equipment etc.) of OS.Therefore, the access of the address in this scope is belonged to the access of FAT type.It is the FDB access after the FAT access.Next access is user data.Therefore, after user data can be identified as and follow FAT and FDB access closely.Super durable flash drives checks FDB, finds file extension, therefore can detect and process temporary file in the mode that is different from subscriber data file.
The file that [the 49th section] is every type can cause the flash memory wearing and tearing of flash drives.Whatsoever system all can all data of fair play.All things all are written into flash memory, when it enters the DRAM impact damper, are so from main frame, data that have the same buffered index by another section when evicting the DRAM impact damper from least.By the recognition data type and to the intention of main frame, then only the user data of the reality during normal running is written to flash memory, only critical data is write flash memory, then according to the regular operation of power fail, can significantly reduce writing of flash memory like this.
[the 50th section] can further reduce the flash memory wearing and tearing by packed data.For example, can leave in together in the single page in flash memory with other part page datas less than the data (part page data) of a whole page in flash memory, rather than the part page data is existed respectively in many independent pages.Also have some data files very little, only have a sector or less than a sector.These local sector files also can be put together.If flash memory capacity and density increase, the size of the page also can increase.For example, a flash memory page may be 16 sectors, and every sector 512 bytes may be also 8KB.But because many Hosts files are all very little, little data file (as only having 1KB) is stored in the independent flash memory page, the space that waste is a large amount of.These partial page files are put together, can raise the efficiency, and finally reduce the wearing and tearing of flash memory.Even a large file, the last page of this document may be the same with small documents little, thereby wasted a large amount of spaces.
[the 51st section] with flash memory page alignment compare, because two kinds of differences on the same flash memory page write at different time, do not line up from trooping of main frame and can cause the unnecessary amplification that writes.In addition, write-once just takies a flash memory page, and this may cause two pages of flash memories to be written into.By checking the start address of FAT1 table, can solve this point.Do not line up if there is the flash memory page boundary, all LBA address after the FAT1 start address adds a side-play amount to write the impact of amplification with reduction, just can realize alignment adjustment.
In a hostile environment, may there be software error in [the 52nd section] in the DRAM impact damper.Can use an extra over capacity to carry out the ECC parity checking to DRAM, to increase reliability.
[the 53rd section] although reduce the wearing and tearing of flash memory with single technology, may bring various improvement, if use simultaneously these technology, the persistence of flash memory just may increase greatly.Use these technology, super this target of durable flash drives may be achieved.
[the 54th section] Fig. 1 is the block scheme that uses the super durable flash drives of low persistence flash memory.Main frame 100 has the processor of an execution of program instructions and operating system (OS) (as Windows, Linux, apple OS or Android etc.) instruction.The primary memory of processor is arranged in main frame DRAM10, and main frame DRAM10 also stores the data of controlling for file system and the pagefile that is used for page exchange, and they are parts of memory management.When primary power broke down, standby power supply 41 made when power fail occurring for main frame 100 provides power supply, and main frame 100 can be sent to the critical data from main frame DRAM10 solid state drive (SSD) 102 or hard disk.Standby power supply 41 can use battery or uninterrupted power supply (ups) Unity etc.This allows the CPU of main frame close if having time application program, closes the equipment of connection.SSD102 has the standby power supply 42 of oneself, when primary power breaks down, allows SSD102 that critical data is write flash memory 30.Standby power supply 42 can utilize capacitor, ultracapacitor or battery.
[the 55th section] super persistence equipment of enhancement mode (SEED) the 11st is used and storage for one in main frame DRAM10.SEED11 can be used to alleviate the burden of SSD102.At first, SEED11 can separate and/or store those does not need permanent storage in the data of SSD102, as temporary file, and pagefile etc.If the SSS DRAM impact damper 20 of SSD102 is enough large, its part can be split into one can be by the driver of the direct access of SEED11.The second, SEED11 can execute the task with the CPU of main frame, compression/de-compression for example, encrypt/decrypt.The 3rd, SEED11 can the supported data write cache, and management is written to the page data of SSD102.SEED11 can generate software ECC or low density parity check code (LDPC), is convenient to page data is write SSD102.The 4th, SEED11 can be supported in the power supply opening of main frame 100/when closing, automatically be written into/copy the image of the SEED11 in stripe cell.
[the 56th section] SSD102 has main frame I/F16 interface, and this interface uses bus, is connected with main frame 100 as PCIe, SATA or USB (universal serial bus) (USB), Thunderbolt, eMMC, ISSD etc.Host data from main frame I/F16 interface is sent to intelligent storage switch (SSS) controller 40.SSS controller 40 is carried out various functions, to reduce the wearing and tearing of flash memory 30, for example, the temporary file from main frame 100 is stored in SSS DRAM impact damper 20, rather than is stored in flash memory 30.The data of other type, Tathagata can be buffered in SSS DRAM impact damper 20 from the pagefile of main frame 100, if but SSS DRAM impact damper 20 does not have additional space, and based on the application of server system, old pagefile can be thrown into flash memory 30.Equally, the flash memory file system of SSD102 is buffered in SSS DRAM impact damper 20, but is kept in flash memory 30.Various forms and impact damper are stored in SSS DRAM impact damper 20, and standby exchange of management table or file are also like this.These forms in SSS DRAM impact damper 20 may be the high-speed caches that is kept at the larger form in flash memory 30, for example system and bad block table, the mapping table of logical address-physical address, or other kinds mapping or system table.Due to the As time goes on and gradually wearing and tearing of each several part of flash memory 30, thereby flash memory 30 will have over capacity.Standby and swap block zone in SSS DRAM impact damper 20 provides over capacity for flash memory 30.
[the 57th section] DRAM I/F12 interface reads data and write SSS DRAM impact damper 20, and hyperchannel flash memory I/F14 interface is organized into several passages, to data page programme and erase flash memory 30 in piece.Native Command Queue (NCQ) manager 34 can be resequenced to the Host Command from main frame 100, and management is by the Host Command formation of main frame I/F16 interface reception.NCQ manager 34 writes the formation of Host Command input command and is resequenced and make up in command queue, reduced writing of flash memory 30.
[the 58th section] temporary file manager 44 identification is from the temporary file of main frame 100, as by reading the file extension of the host data that writes in FDB.Ephemeral data (having the file extensions such as tmp, temp) is stored in SSS DRAM impact damper 20, and being under an embargo deposits in flash memory 30.Can be according to dependency rule, as based on the time that disappears, the capacity etc. of distributing to ephemeral data or power-off/electric energy loss, ephemeral data is abandoned.
[the 59th section] Redundant Array of Independent Disks controller 36 writes new data in a plurality of passages of flash memory 30, can also provide redundancy backup and data to recover by copy data.ECC manager 28 adds it in data writing for generation of error correcting code, and compares with the ECC that regenerates by the ECC with storage, detects and correct the mistake that reads the aspect.It also is in charge of the flash memory page that needs extra ECC protection.It generates ECC for these pages, then when needed, and storage and the retrieval of management ECC data.The position of bad block management device 38 bad pieces of tracking in flash memory 30, and can further identify the bad page that writes local bad piece.Can extend the life-span of single like this, be bad because may only have in a page in piece, and other the page can continue to use.More complicated bad block management may reduce the overall wear of flash drives.
[the 60th section] wear measurement device 24 provides the wear leveling method of two types.A kind of is dynamically to select minimum average erasable several piece data writing from available empty piece; Another kind method is based on average erasable number of times critical value standard, in case reach this critical value, the flash memory data block is moved to another physical block flash memory 30 (having high average erasable number of times) from a physical block (having the erasable number of times of harmonic(-)mean).The mapping of the logical address-physical address in the mapping table that form manager 32 is managed is upgraded.Form manager 32 is also followed the tracks of the type that is stored in the data in each logical block, and in a single day temporary file, pagefile, FAT, FDB and subscriber data file are identified and classified and also just obtained the tracking of form manager 32 like this.
The data of [the 61st section] part page combine by page pool manager 22 the flash memory page of packing into.Sector combination manager 18 gathers together the part sector data.Partly page and part sets of sectors are got up and can be increased work efficiency, and reduce wear.Before being copied to flash memory 30, part page and the part sector data can be fitted together and cushion a period of time in SSS DRAM impact damper 20.Partitioned data set (PDS) is combined into whole page data, can reduces the number of times that writes flash memory.
[the 62nd section] can compress and/or encrypt data.The position of compressing mapping manager 26 mapping compression data blocks is compressed or writes, the data of reading are carried out decompress(ion) data.46 pairs of data that write of crypto engine are encrypted, and the data of reading are decrypted.
File system on [the 63rd section] TRIM manager 23 processing host 100 or the TRIM order of operating system.TRIM order expression main frame no longer needs certain sector, can or wipe its removing.The page after finishing is registered as " deleting " at " page status table "; During the backstage garbage reclamation, if this piece is confirmed as wiping candidate target, just this page can not be copied on new piece, at this moment just really carried out the TRIM order.TRIM manager 23 is carried out the inner self check that arranges, and no longer needs as which sector and the page in the tracking piece.Garbage collector also can be used for following the tracks of the piece that those are about to be wiped free of.In case no longer need certain complete piece, TRIM manager 23 startup garbage collectors or other erase mechanisms are wiped the data on this piece, and this piece can be reused.
S.M.A.R.T. order or supplier's order that [the 64th section] S.M.A.R.T. function 39 is processed from main frame 100 are as the correction of monitoring and controlling data, wearing and tearing, bad piece and other flash management.S.M.A.R.T. refer to self-monitoring, analysis and reporting techniques.Main frame can use arranging of S.M.A.R.T. order that some significant datas such as on time, average erasable number of times etc. from SSD equipment are monitored.Main frame can be diagnosed and life-span of definite SSD with these data.Before the SSD driver was scrapped, main frame can be changed it.In RAID, main frame can be avoided more expensive RAID5 configuration with the S.M.A.R.T. order.Functional manager 48 can comprise the function that a lot of main frames can open or close, as compression, encryption and combination etc.Functional manager 48 is responsible for communicating by letter with main frame 100, the use of management SSS DRAM impact damper 20, carry out other function, as when power supply breaks down, preferential which data of selecting are written into flash memory 30 from SSS DRAM impact damper 20, when power-fail with these data Replicas to flash memory 30.Functional manager 48 checks the form of file system, the size of trooping during with definite energising and the start address of FAT1.It can check the page size of the flash memory 30 of use.If the situation that the size of appearance and flash memory page does not line up, a side-play amount will be added into, and host clusters is alignd with the flash memory page boundary.
[the 65th section] Fig. 2 A-C has emphasized to want the separate management temporary file, to avoid that temporary file is write flash memory.In Fig. 2 A, host data is divided into the temporary file 112 that need not backup to flash memory.Host data and order are written to the data input buffer 108 in DRAM.Data are divided manager 109 and are consulted the LBA of every host requests, and determine which host requests is the data of issuing in the temporary file catalogue.Temporary file 112 also may comprise the request that main frame sends to the data of internal memory page area.Send to other host requests of non-temp directory to be divided into non-temporary file 110.Non-temporary file 110 is processed by page pool manager 22, and page pool manager 22 will be from the synthetic flash memory blocks of the page group of different host requests.The data of this non-temporary file 110 are stored in data write cache 111, and high-speed cache 111 is positioned at the non-temporary file district of DRAM.When data write cache 111 will be expired, data block was abandoned, and then write flash memory 30.
[the 66th section] merged in the page by sector combination manager 18 from the temporary file 112 of different host requests.Data block may be a page, sector or part sector, or various combination.This less granularity is particularly useful for temporary file, because it allows higher packaging efficiency, especially when less quantity of documents is numerous.These temporary files are stored in the temporary file district 113 in DRAM, and do not backup to flash memory 30.When the temporary file district 113 in DRAM is fast full, this district or extended, or temporary file that will be older deletion or cover.Therefore avoided temporary file is write flash memory 30.Can reduce the wearing and tearing of flash memory like this.
[the 67th section] Fig. 2 B has shown Data Segmentation.Data receiver host data in data input buffer 108.The LBA of host data will compare with the LBA scope that is used for the temporary file storage, as keeps for the temporary file sub-directory, or the LBA scope of the file of tmp or some other known temporary file extension name is arranged.When data are identified as temporary file, i.e. step 732, data will be moved to the temporary file district in DRAM, i.e. step 734.The data that non-ephemeral data is moved in DRAM write in buffer memory, i.e. step 736.This is non-temporary file district that is backed up to flash memory in DRAM.
[the 68th section] Fig. 2 C has shown the Data classification of temporary file.File system analytic process 740 is performed.This process has been identified the catalogue of storage temporary file, step 742.File system is offered help for identification.For example, can be by identify the file extension of .temp or tmp together with FAT with FDB.
[the 69th section] process 740 can be at running background, i.e. step 744, or move when system is in idle condition.In idle period of time, can search for FDB, obtain the LBA scope of each temp directory, i.e. step 746.Can be the scope creation look-up table of each temp directory, i.e. step 748.The LBA scope of the temporary file in this temp directory can be filled the entry of look-up table.
[the 70th section] Fig. 3 is the memory map of durable conversion layer (ETL), has shown the various types of data that are stored in SSS DRAM impact damper 20.The firmware of SSS controller 40 is managed when energising, the normally interaction between DRAM and flash memory when operation and power-off with ETL.The temporary file district 140 of SSS DRAM impact damper 20 is storing the temporary file that SSS controller 40 is identified by reading the FDB/FAT file extension that is stored in FAT/ mapping table 158th district and the sub-mapping table of FDB/ 160th district.Temporary file refers to expand the file of .tmp .temp by name .tmt .tof .trs .tst etc.The extension name of the temporary file of System Dependent may comprise .mp .log .gid .chk .old or .bak.The file extension of the temporary file that AutoCAD is relevant may comprise .SV $ .DWL .AC $.The extension name of the temporary file that Word is relevant may comprise .asd.The temporary file that Excel is relevant may comprise the file take .xar as extension name.Other application programs may be used own unique temporary file extension name.Temporary file district, internet 142 is storing the file of file extent .gif .jpg by name .js .htm .png .css .php .tmp .mp3 .swf .ico .txt .axd .jsp and .aspx.There is a table of searching each temporary file in 140th district and 142nd district.This table can come index by the logical address of main frame.
[the 71st section] data are extracted district 144 and are being stored extraction data and table of articles.Open computing machine, Windows operating system just generally is in open state to the mode of computer starting and which program and follows the tracks of at every turn.Windows is saved in the preextraction file to these information with the form of some small documents.When opening computer, Windows quotes the speed that these files improve start-up course next time.
[the 72nd section] preextraction file is a sub-folder in the Windows system folder.The preextraction file accompanies the function of self, there is no need deletion or empties its content.
The journal file of [the 73rd section] expansion .log by name or .evt is stored in journal file district 146, and also may there be the mapping table relevant to the journal file that is stored in this district in this district, and journal file also might be considered to a kind of temporary file.
[the 74th section] is used between the primary memory on main frame and peripheral storage device (as hard disk or SSD102) pagefile of swap data and is stored and is mapped in pagefile and mapping table district 148.The sense data high-speed cache of reading and be stored in SSS DRAM impact damper 20 from flash memory 30 is placed on and reads buffer area 151.The mapping table that reads cache entries can be used, and this mapping table comprises the pointer of data in label, significance bit and sensing flash memory 30.System region 150 is being stored the flash memory system data of the operating system use of SSS controller 40.Data storing in buffer zone 152 the origin host data (comprising LBA) that just are written to SSD102.Real host data was transferred to data write cache 154 afterwards, and then was written in flash memory 30.In order to reduce the quantity of flash memory write/erase, super the write caching technology relevant to data write cache 154 is used to data writing is cached to flash memory, further reduces the number of times of write/erase in flash memory with persistence is standby with swap block 156.
[the 75th section] writes and will at first data be write in buffer zone 152 from the data of main frame 100, through the processing (as compression) of controller, then data writing write cache 154, and then write flash memory 30.Constantly write this situation if there is a large amount of data from main frame 100, can't continue to flash memory 30 data writings.These data will be written to data write cache 154 continuously, until write completely, then the data stream from buffer zone 152 to data write cache 154 will stop.If the data of buffer zone 152 are also full, main frame will be received the notice that stops flow so.
[the 76th section] data write cache 154 uses a kind of persistence to write cache algorithm, data writing is stored in SSS DRAM impact damper 20, and can not be written in flash memory 30 before by throwing.Therefore, repeatedly writing the data in cover data write cache 154 of identical LBA arranged, and according to rule (as the time based on passage, the capacity of distribution etc.) or based on the abnormal conditions of power-off or power fail, data are write flash memory 30 in stripe cell.Data write cache 154 is also preserved part page data writing, until a plurality of part page is combined as whole page.Therefore, according to rule (as the time based on passage, the capacity of distribution etc.) or the burst accidents such as power-off or power fail, a plurality of part pages can be written in flash memory 30.
[the 77th section] is in a Multi Channel Controller structure, device controller can be with the data that are arranged as a plurality of pages (quantity of a plurality of pages can be identical with multichannel quantity) from high-speed cache 154 be written to flash memory in stripe cell, with the storage block of conveniently throwing out, utilize best the flash memory interface bandwidth.Each device controller comprises C bar passage, and every passage is connecting F flash memory dies, and D kernel arranged in the stacked structure of each chip, and each kernel has P plane.Stripe size is set to the F*D*P page.Stripe depth is set to the C*F*D*P page.Device controller is selected data from data write cache 154, data are write in the band of selected flash memory 30, then upgrades relevant mapping table entry according to corresponding physical address (PBA).Each passage only has a bus, thus only have endorse in one accessed.The F*D kernel is interlaced, shares a bus, realizes the maximum utilization of bus.The size of stripe cell can be C page or as many as C*F*D*P page.
[the 78th section] durable conversion layer (ETL) method has improved the persistence of the flash memory in low appointment erase cycles life-span.Flash memory interface has a plurality of channel bus, and each passage has a plurality of flash memory dies; Each chip has a plurality of kernels, and each kernel has a plurality of planes.Can access simultaneously all passages.
[the 79th section] can not access all kernels in same passage at one time simultaneously; Once can only access a kernel in same passage.Only when being written or read, other kernel just can access another kernel in a passage.Interlock and write or read the performance that can improve flash memory access.The data write cache is stored in the DRAM impact damper, is managed according to rule by controller.During greater than stripe cell, device controller can manage invalid data, and writes flash memory by flash memory interface when the invalid data in the data write cache.The distribution of device controller management data on each passage of flash memory.Device controller managed the interweaving of certain kernel of certain chip in data and each passage, and management mapping table entry is to follow the tracks of the mapping of LBA to PBA.
[the 80th section] in other alternate design, in the Multi Channel Controller structure, each passage can have its data write cache 154.Stripe cell is write each flash memory passage simultaneously, can realize that flash memory interface speed maximizes.
[the 81st section] user file data can according to=n(is as 2) hit rate be identified as frequent visit data and＜hit rate of n is identified as non-frequent visit data.They may be written to respectively two data write caches 154.The identical many data writings in LBA address that enter frequent access region will cover that in DRAM, those do not put into the old content of flash memory, can reduce the number of times that writes flash memory 30 like this.According to rule, as the time (as 1 hour) of passage, the capacity of distribution etc., or the emergency case such as power-off or power fail are in the data write cache in the data cached flash memory 30 that will be stored in stripe cell of frequent access region.According to another rule, as based on the time (as 15 minutes) of passage or the capacity that distributes etc. or the emergency case such as power-off or power fail, in the data write cache in the data cached flash memory 30 that will be stored in stripe cell of non-frequent access region.
The situation that [the 82nd section] do not line up if there is the LBA address, the LBA address will be added a side-play amount, alignd with the page address of flash memory 30 in the LBA address, and then to write cache 154 data writings, do like this and can improve the efficient that flash memory afterwards writes.
[the 83rd section] persistence is standby is used for garbage collecting function with swap block 156, and before writing data into flash memory, this function merges valid data and the data of evicting write cache from.Page status table 162 comprises a table that the page status entry is arranged, such as blank page, used page, rubbish page (TRIMed), bad page, need the page of extra ECC protection.The map entry of compression LBA table 161 store compressed user data.Piece/erase count table 164 is followed the tracks of erase counters and the bulk state of each physical block in flash memory 30.
The map information of [the 84th section] part page map table 166 storage part pagings.DRAM may not have enough spaces to place whole mapping table, and therefore, only some is loaded into DRAM to mapping table.Not in DRAM, then DRAM will evict the partial content of part mapping table from when the LBA table clause, and relevant LBA table is loaded on DRAM.Parton sector combination mapping table 168 is the data file less than a page, is used for storing sub-sector map information.The part mapping table of parton sector combination mapping table 168 only has the entry (total N group mapping table) of 1 group of mapping table.Other N-1 group mapping table is stored in flash memory, and when the part mapping table occured to omit, they were sent to SSS DRAM impact damper.
[the 85th section] S.M.A.R.T. data collector 170 has tables of data and S.M.A.R.T. function 39(Fig. 1) other information of using.Main frame can be filed a request to S.M.A.R.T. data collector 170 by S.M.A.R.T. order or supplier's order.
In [the 86th section] SSS DRAM impact damper 20, the size in each zone can be determined according to the whole size of SSS DRAM impact damper 20, page size, block size and the sector-size of flash memory 30, and according to whether using page mapping or piece mapping, perhaps according to estimating that what entry of this zone percent be that page mapping rather than piece mapping come definite.For example, SSS DRAM impact damper 20 may be 512MB DRAM, and wherein 240MB distributes to temporary file district 140,160MB and distributes to temporary file district, internet 142,12MB and distribute to data and extract district 144,6MB and distribute to journal file district 146 etc.
[the 87th section] is in the Multi Channel Controller structure, device controller can be from flash memory 30 reading out datas, and by multi-channel structure until various ETL table (the sub-mapping table 158 of FAT/, the sub-mapping table 160 of FDB/, page status table 162, compression LBA table 161, piece/erase count table 164, part page map table 166 and parton sector combination mapping table 168).
[the 88th section] is according to a rule (as based on the time of passage or the capacity of distribution etc.) or power-off or power fail, in the structure of a Multi Channel Controller, device controller can be with various ETL table (the sub-mapping tables 158 of FAT/ that are arranged to multi-page (quantity of multi-page equals multichannel quantity), the sub-mapping table 160 of FDB/, page status table 162, compression LBA table 161, piece/erase count table 164, part page map table 166 and parton sector combination mapping table 168) write in the flash memory of stripe cell, to realize the preferably utilization of flash memory interface bandwidth.
[the 89th section] from as shown in Figure 3 use in each zone of internal memory one by one that the situation of mapping table is different separately, can use one or more unified mapping tables.Can use back code shown in Figure 6 that the type of each entry File is made stipulations.
[the 90th section] Fig. 4 A-B is a partial block that quilt excessively writes.In Fig. 4 A, main frame before write all pages of 0-127 in a piece.At first, 128 pages all are stored in SSS DRAM impact damper 20, are copied to afterwards in flash memory 30 on physical block BLK2.Afterwards, main frame had covered the 10-99 page, but 0-9 page and 100-127 page was not write.The new host data of 10-99 page covers the old page data in SSS DRAM impact damper 20.Because in flash memory, the 10-99 page is out-of-date data, these pages are flagged as invalid page.
[the 91st section] is copied on physical block BLK550-9 page from the 0-9 page of physical block BLK2 when the invalid data in SSS DRAM impact damper 20 will be copied to flash memory 30.Equally, there is the invalid page 10-99 of new host data to be copied to from SSS DRAM impact damper 20 on 10-99 page the physical block BLK55 of flash memory 30.Be copied to the 100-127 page of physical block BLK55 from the 100-127 page of physical block BLK2.This logical block can be used for storing different logical blocks at the storage space of SSS DRAM impact damper 20 now, because the 0-127 page of old blocks of data all is stored in the physical block BLK55 of place now.The mapping table entry of this logical block has been done modification, points to physical block BLK55 rather than points to BLK2.Old physical block BLK2 full content can be used as refuse collection, it is arranged prepare to accept to wipe, bad piece detects and reuse this several steps operations.
[the 92nd section] Fig. 4 B is the standby example that operates with swap block 156 of persistence.SSS DRAM impact damper 20 can be distributed to the logical block of main frame at present without any the space.SSS DRAM impact damper 20 needs to observe the rule of " distribution of writing is arranged ".When main frame write section block data, SSS DRAM impact damper 20 just distributes a new piece entry, may be from the empty piece entry in SSS DRAM impact damper 20, or from SSS DRAM impact damper 20, legacy data is thrown the space of vacateing to flash memory 30.10-99 page from main frame is stored in the 10-99 page in this newly assigned in SSS DRAM impact damper 20.Read in the physical block BLK2 of 0-9 page from flash memory 30, the 100-127 page is also like this.Whole (0-127 page) then can copy to new physical block BLK55 flash memory 30 from SSS DRAM impact damper 20.The mapping table entry of this logical block is changed to points to physical block BLK55, rather than points to BLK2.Then old physical block BLK2 full content can be used as refuse collection, it is arranged prepare to accept to wipe, bad piece detects and reuses.The page status table will show the state of each independent page in flash memory.To be checked by the object block that garbage collector is wiped, understand its page status in piece by the page status table.Only damage the page and blank page beyond with the mistake the page and the page of cutting out can be copied to exchange area.
[the 93rd section] has the standby and swap block relevant with partial coverage in flash memory in an ancient deed algorithm.For example, data are written in a piece in flash memory, and then a part of content of raw data changes.At first controller writes new update content the stand-by block in flash memory.Then legacy data and new data will be integrated into swap block.After that, original block and stand-by block will be wiped free of.One time partial coverage can cause two pieces deleted.In some file algorithms, data need to be write back in original piece.In this case, with deleted three pieces that have.
[the 94th section] in a Multi Channel Controller structure, device controller can from a special modality of flash memory 30 with data read persistence standby with swap block 156.After standby and swap block operation, active data can be written into the same passage of flash memory 30.
[the 95th section] Fig. 5 is piece mapping, page-map and sector map.In order to realize maximum dirigibility, efficient and mar proof, according to the size of user data, the mapping of three types all will be used.
[the 96th section] is mapped on a whole physical block in flash memory 30 from a whole logical block of main frame in piece mapping.Host address 180 refers to the user data of 512 bytes.Sector K is a sector number that is used for identifying certain sector in certain page, for example the sector of 512 bytes in the page that 16 sectors are arranged.A band in passage J1 sign flash memory 30 is as 8 bands (with the structural similarity of RAID0) (size of a band is at least a page) in 8 passages.Page L is the page number that identifies a page in logical block, as certain one page in the piece of 128 pages.LBA-B is the block address of identification logical block M.The logical block mapping table comes index by LBA-B, and logical block M is mapped to physical block N(physical block address PBA-B in the physical address 182 of flash memory).Flash memory passage J2 can be deleted from physical block number.If two planes of flash memory, LSB passage J1 will be added to page L as LSB.If use one and the similar structure of RAID1 structure, a passage can be used as the counterpart of rest channels, and can not show in the drawings.
In page-map, mapping table is indexed out from logical address 184 by LBA-P [the 97th section], and LBA-P is the logical page number (LPN) that comprises logical block number M and logical page (LPAGE) numbering L.Page entries in mapping table produces a Physical Page numbering Y, and Physical Page numbering Y is that the size of physical block address, the page and PBA-P(Y in physical address 186 is the same with M, L, but value is different).Because number of pages is more much more than piece number, the quantity of the map entry of page-map is also just much bigger than the quantity of the map entry of piece mapping.A band in passage J1 identification flash memory 30 is as 8 bands (with the structural similarity of RAID0) in 8 passages.Passage J1 can be mapped to mapping table, so device controller can move on to page data in any passage, and is not limited only to special modality.Perhaps, if J1 equals J2 all the time, the J2 passage of flash memory can be deleted from physical block number.If two planes of flash memory, LSB passage J1 is used as LSB and adds page L to.If use a structure with the RAID1 structural similarity, a passage can be used as the equivalent of rest channels, and can not show in the drawings.
In sector map, mapping table is indexed out from logical address 188 by piece, page, sevtor address LBA-S [the 98th section].This is the logical page number (LPN) that comprises logical block number (LBN) M, logical page number (LPN) L and sector number K.Sub-mapping table and the page map table of a sector use together, and LBA-P and sector K are mapped to physical sector address a: PBA-S in physical address 190 like this, (size of Z and M, L, K are identical, but value is different).Because number of sectors is more much more than quantity and the quantity of piece of page, the quantity of the map entry that the quantity of the map entry of sector map is also just shone upon than piece is much bigger.A band in passage J1 sign flash memory 30 is as 8 bands (with the structural similarity of RAID0) in 8 passages.Passage J1 can be mapped to mapping table, so device controller can move on to page data in any passage, and is not limited only to certain special modality.Perhaps, if J1 equals J2 all the time, the J2 passage of flash memory can be deleted from physical block number.If two planes of flash memory, LSB passage J1 is used as LSB and adds page L to.If use a structure with the RAID1 structural similarity, a passage can be used as the equivalent of rest channels, and can not show in the drawings.
[the 99th section] large polynary belongs to the piece mapping, only has the piece of small part to belong to the page mapping.Have the relatively less page to belong to the fan mapping in the piece of a page mapping, in SSS DRAM impact damper 20, the size in whole mapping tables zone will remain in rational scope.When in SSS DRAM impact damper 20, the mapping table regional space was not enough, mapping table can be kept in flash memory 30, and the buffer memory of these map entrys is stored in SSSDRAM impact damper 20.
[the 100th section] Fig. 6 has shown the map entry that in super durable flash drives, different data types is defined.Except the data for every type provide independent mapping table, for example shown in Figure 3, also can use a unified mapping table will be mapped to from the logical address of main frame physical address in SSS DRAM impact damper 20 or flash memory 30.
[the 101st section] former position of each map entry in this unified mapping table is one and is used for code that the host data that this entry is shone upon is identified.This code bit also shows the size of mapped data, is complete page (FP), or part page (PP).
[the 102nd section] in when energising, storage and mapping table that known data type is distributed before SSS controller 40 is written into.After format, only have FAT/FDB entry and table to exist.Could create new file and new sub-directory after that.Because necessary first data writing before reading is so all data that read from main frame should be from certain known data type.For write operation, only have new file data just to need the specified data type.FDB/FAT is accessed in all membership of writing from main frame.
[the 103rd section] SSS controller 40 checks the new entry of FDB/FAT, to determine the data type of LBA.File in FDB is described and is comprised filename and file extension, initial position of trooping, file size and date created.SSS controller 40 utilizes this information to come specified data, and data are grouped in several data types under a certain type:
[the 104th section] PF: memory management is for exchanging to from main memory the pagefile that hard disk creates with file.Logical address by pagefile uses can find these pagefiles.Main frame is that required virtual memory distributes an available LBA scope.SSS controller 40 checks FDB, to determine the LBA scope of pagefile.
[the 105th section] TMP: from the temporary file of main frame.SSS controller 40 reads the file extension in the FDB entry, can find temporary file.The FDB entry writes before temporary file is write by main frame.Generally, at first main frame writes FAT, FDB then, is then temporary file, so in FDB, file extent star's file identification of .tmp is temporary file.FDB has initial position of trooping, size (quantity of trooping of use), and FAT has information (if this document is trooped greater than one) or the end-of-file (EOF) (last of file trooped) of next cluster location.
[the 106th section] FAT: from the FAT entry of main frame.Main frame writes two copies of FAT, and FAT1 is write in first predefined address realm, and FAT2 is write in the next address scope.For example, FAT1 is write logical address 0-8KB, and FAT2 is write logical address 8-16KB.Actual address realm depend on SSD capacity (for example: 16GB), the size of trooping (for example: 8KB).Actual address realm determines required total FAT table clause, as 16MB/8KB=2M.For FAT32, each entry needs 32, so address realm is 2M * 4=8MB.If each LBA is 512B, its LBA scope (8M/512=16K) is that " FAT_beg " arrives " FAT_beg+16K " so.
[the 107th section] FDB: from the FDB entry of main frame.SSS controller 40 is defined as the file description block entry immediately following a path after the FAT path.After format, can know root directory by FDB.FDB is upgraded in the write operation meeting of each file and sub-directory.Because the LBA scope that has been the FDB mark is so the SSS firmware is known the data that write FDB.Firmware further checks the data that are written in new sub-directory.In order to determine new FDB data type, new sub-directory provides initial cluster and size information.The FDB entry may have a predefined address realm, and this predefined address realm may promote or accelerate FDB and detect.
[the 108th section] DT: the data file of user data or application data.These are all the normal data files that is stored in flash memory.These data files may directly be stored in flash memory, may be also first to be buffered in a period of time in SSS DRAM impact damper 20, and the impact damper of then being thrown out enters flash memory or copies in flash memory when power supply is cut off.
[the 109th section] provides four kinds of different parameters from the order of main frame 100: initial LBA address, sector count (SC), order (read/write) and data (not having when reading).Determine the data that each is dissimilar, the firmware of SSS40 needs managing file system, as FAT32.From LBA0, it can authenticating documents system whether be FAT32, then its can find the LBA of FAT, FDB, temporary file etc. from the file system that writes SSD.In order to determine the data type of the new LBA that uses, it also relies on the FDB of SSS40 to go to check energetically that FDB is the change that in updating file/sub-directory, information is made.For example, if the name of a new temporary file is written to FDB, these information will comprise the initial LBA that troops of temporary file.Then SSS40 determines as the relevant LBA of trooping of ephemeral data type.In a candidate design, to be revised by SEED11 from the order of main frame 100, the 5th parameter with data type after modification included, to improve persistence and the performance of flash memory device.Data type can be temporary file, pagefile, FAT, FDB, FA data and NFA data (each data type can have multiple version: normal, as to compress, encrypt, compress+encrypt etc.).For example, the data type of " page " (normally) is 0x00, and the data type of " NFA data " (compression+encryption) is 0x13.The 5th parameter can discharge the firmware of above-mentioned special SSS40.For example, temporary file is with five parameter of data type " temp " as the host write command data.In addition, SEED11 can be by supporting the persistence that arranges to improve flash memory device of main frame 100.System arranges, and as being redirected page file, Windows temporary file, specific program temp directory, event log, index, system reducing etc., can copy on main frame DRAM10.The change of other settings, such as defragmentation forbidding, reduce the recycle bin size, cut out enable, S.M.A.R.T. enables etc., also can improve the persistence of flash memory device.In addition, SEED11 sends specific command to flash memory device 102.These specific commands are with the parameters such as page number, number of pages, page command and page data rather than No. LBA, sector count, sector instruction and sector data.Order may comprise the read/write information of temporary file, pagefile, FAT, FDB, FA data and the NFA data (each data type can have multiple version: normal, compression, encrypt compression+encrypt etc.) of data type.
[the 110th section] is for the wearing and tearing that reduce flash memory 30 and increase its persistence, usually only allows data file (DT) is written in flash memory.The entry of pagefile (PF), temporary file (TMP), FAT and FDB does not write in flash memory, but is stored in SSS DRAM impact damper 20.When cutting off the power supply/electric energy loss or do not have enough spaces to come all data of buffer memory the type when SSS DRAM impact damper 20, the data of these types just may be written into flash memory.
The following data type of front three identification of [the 111st section] data type:
[the 112nd section] 001 – pagefile (PF)
[the 113rd section] 01X – temporary file (TMP)
[the 114th section] 100 – FAT entries
[the 115th section] 101 – FDB entries
[the 116th section] 11X – data file (DT user data)
[the 117th section] last type bit (the 3rd or the 4th) is designated the entry of complete page (FP) or the entry of a part page (PP) to entry.The entry of complete page comprises one and points to data pointer (PTR) of position (in SSS DRAM impact damper 20) in DRAM, and the entry of part page comprises a pointer (SCTR) that points to sub-sector map.If last type bit is 0, this page is whole page data so, just there is no need to use sector map.
[the 118th section] if last type bit is 1, this page is by part mapping.Entry in unified mapping table is a pointer (SCTR) that points to the sub-sector map of this specific webpage.That sub-sector map may have a plurality of entries.Each entry and one or more complete sector, and/or certain part sector is corresponding.If the position of the first sub-sector is 0, the entry of this sub-sector is corresponding with one of host data complete sector so.The entry of minute sector comprises a pointer that points to the page of data in SSS DRAM impact damper 20, also comprises the sector count SC# of complete sector, and sector count SC# is the side-play amount from directed that page beginning.
[the 119th section] when the position of the first sub-sector be 1, the entry of sub-sector is corresponding with certain part sector.The entry of this sub-sector comprises one and points to the pointer of page of data beginning in SSS DRAM impact damper 20 and the side-play amount A(N of interior first byte of this page).This side-play amount is the beginning of partial data sector, is the length LEN (N) of partial data sector.
[the 120th section] Fig. 7 has shown complete page mapping and the mapping of part page of the pagefile that uses unified mapping table and sub-sector map.First three type bit 001 is used for identifying the entry of pagefile (PF).In order to reduce the wearing and tearing of flash memory, pagefile is stored in SSS DRAM impact damper 20, rather than in flash memory 30.These entries are used for shining upon the page pool 148(Fig. 3 in SSS DRAM impact damper 20).These entries are parts of unified mapping table 192.
Last type bit of first entry that [the 121st section] shows is 0, represents that this entry is a complete page (FP).First entry comprises a pointer (PTR) that points to SSS DRAM impact damper 20 certain position.The full page data of this pagefile just is stored in the page data district 196 of SSS DRAM impact damper 20.This position of SSS DRAM impact damper 20 can be read or be written to the data of main frame, to complete host requests.
The last type bit of second entry that [the 122nd section] shows is 1, represents that this entry is corresponding with part page (PP).SSS controller 40 checks the page data that imports into, belongs to complete page data or partial page data with specified data.For the partial data page, the SSS controller determines that also each sector (0～15) is complete sector data or part sector data, does not still have data.Second entry comprises a pointer (PTR) that points to certain position in SSSDRAM impact damper 20, and the sub-sector map of this entry is unified mapping table 192 places in the SSSDRAM impact damper just.The logic sector that extracts from host address is used for selecting a current entry at sub-sector map 194.
The first two entry of [the 123rd section] sub-sector map 194 is corresponding with complete sector, because their the first position, sub-sector is 0.These entries comprise a pointer (SPTR) that points to certain page location (PF-DRAM-PP) in SSS DRAM impact damper 20.Sector data just is stored in SSS DRAM impact damper 20.Memory sector data in order are from sector 0(SC) beginning is until last sector SC15.The entry of each complete sector in sub-sector map 194 also comprises sector count SC#, and it points to the sector in the pointer PF-DRAM-PP page pointed, and these are full sector datas.
Last entry in [the 124th section] sub-sector map 194 is corresponding with the part sector, because its first position, sub-sector is 1.Each part page entry and every sub-sector map 194 have at most a part sector.This entry comprises a pointer that points to different page locations (PF-DRAM-PP2) in SSS DRAM impact damper 20.The part sector data makes up, is stored in a page in SSS DRAM impact damper 20.
[the 125th section] entry also comprises start byte side-play amount A(N), start byte and the length LEN (N) of the part sector data in certain page of this side-play amount sensing location positioning.Part sector entry comprises LBA(piece+page+sector), what follow LBA closely is real part sector data, due to LBA in this example and LEN(N) built in self testing, sector data is less than 480 bytes.480 bytes are to full sector of use, part sector of 512 bytes.This scheme also is applicable to temporary file etc. and FDB.The unit-sized of the data splitting of complete page data and part page is page.Stripe cell can comprise complete page data and the part page data that combines.When data write invalid data in buffer memory greater than stripe cell, device controller manages invalid data, and by flash memory interface, it is write flash memory.
[the 126th section] FAT and FDB
[the 127th section] FAT is file allocation table.Main frame can use the basic size of trooping as each table clause.When the size of trooping is 4KB, the capacity of FAT is 4096KB, just needs 1024 FAT table clauses.For FAT32, the entry of 0000,0000 represents that this entry is not used, a FFFF, and the entry of FF0F represents the end of a file, next the trooping of effectively digital (for example, between 1～1023) expression is the position of this document.Main frame uses FDB to find the reference position of file, uses FAT to follow the tracks of that the next one is trooped and the position of ensuing trooping (being applicable to larger file), until till the indication of " FFFF, FF0F " entry arrived the end of this document.
[the 128th section] FDB is file description block.FDB storage file name and subdirectory name.In a typical FAT file system, after FDB starts from the FAT2 table.The starting point of FDB is root directory.After format, FDB only takies first after FAT2 table and troops.Corresponding " FFFF, FF0F " FAT entry is the end of file.When writing a file, file data is written to during this troops, and troops when being fully written when this, just has the data that this document is deposited in new trooping.The position of FAT1/2 (entry) is by from FFFF, the FF0F(end of file) be changed to the new position of trooping.If created a new sub-directory, this sub-directory will obtain a new cluster location.The size of FAT table is fixed, and the FAT table is fixed on continuous position.In case create, the position of FDB is just fixing, but new establishment the/trooping of expansion is dispersed on any untapped position.
[the 129th section] FDB preserves such as filename and extension name, the first position of trooping, establishment or revises the fileinfos such as date or time, size.FDB often changes.Only when creating file and sub-directory, so and because file is exaggerated or adds catalogue to when need to newly troop, FAT just changes.
[the 130th section] Fig. 8 has shown the FAT mapping in unified mapping table.The FAT entry is stored in one normally in the predetermined address realm by operating system definition.Exist in SSS controller 40 detects this scope to the operation of certain logical address data writing, data are taken as FAT entry 204 and write FAT158 district in SSS DRAM impact damper 20.A pointer, DRAM-FAT-BEG points to the beginning of FAT entry 204, and always obtains the page side-play amount in FAT entry 204 in the logical address of main frame.
[the 131st section] OS(operating system) safeguard two copies of FAT entry, i.e. FAT1 and FAT2.At first OS writes FAT1 with entry, then identical entry is write FAT2.The entry that writes FAT2 is written to a logical place, and this logical place is at first to be written to the page side-play amount of that entry of FAT1 and the summation of FAT1 table size.
[the 132nd section] do not remain on two tables of articles (FAT1 table of articles, another is the FAT2 table of articles) in SSS DRAM impact damper 20, and only has single FAT table to be maintained at DRAM.Only stored the FAT1 entry.Suppose the FAT2 entry and be complementary early than its FAT1 entry, and SSS controller 40 can verify whether FAT2 and FAT1 mate, SSS controller 40 can not send rub-out signal when both not mating.Can suppose simply that perhaps operating system never writes the unmatched FAT2 with FAT1.Therefore, read and write with FAT2 from the FAT1 of main frame and be mapped in SSS DRAM impact damper 20 FAT entry identical in FAT entry 204.
[the 133rd section] is in order to facilitate FAT1 and FAT2 access, an in store single sub-map entry in FAT mapping table 202.The page side-play amount of this entry is the FAT of FAT1 to be shown the page side-play amount of beginning, and perhaps FAT2 deducts the page side-play amount of the remaining part of size of FAT1 table.
Every sub-map entry in [the 134th section] FAT mapping table 202 has the pointer that points to the FAT1 entry in flash memory 30 a: F-PBA1-P, and second pointer: F-PBA2-P that points to the FAT2 entry in flash memory 30.In order to reduce the wearing and tearing of flash memory, the FAT entry may only can be kept in SSS DRAM impact damper 20, then copies in flash memory 30 in power-off/power failure.Perhaps, the FAT entry of all modifications can periodic replication arrive flash memory (as once a day), if or think that increasing the flash memory wearing and tearing can accept, and can copy to flash memory at once with them.
[the 135th section] preserved two independent copies although for FAT1 and identical FAT2 with it, only an entry is kept in DRAM in flash memory 30.
The front two of every sub-map entry in [the 136th section] FAT mapping table 202 is FAT flash memory mode bit.FAT flash memory mode bit represents whether FAT1 or FAT2 have been copied to flash memory, or only effective in SSS DRAM impact damper 20.When the flash memory position of FAT is that FAT1 table and the FAT2 that the FAT entry 204 in 00, DRAM has been copied in flash memory shows, and all these three positions are all effective.When FAT flash memory position is that 10, FAT1 is write DRAM by main frame, but main frame not yet writes identical entry FAT2, and new FAT1 not yet copies to flash memory.When the flash memory position of FAT is that 11, FAT1 and FAT2 are write DRAM by main frame, but FAT1 and FAT2 all by host duplication to flash memory.The FAT entry that writes in flash memory may reduce, but the persistence of flash memory has improved.
[the 137th section] in a Multi Channel Controller structure, device controller reads the data of FAT table from flash memory 30, and arrives ETL FAT table through multi-channel structure.
[the 138th section] is according to rule (as based on the time of passage and the capacity of distribution etc.), or according to special circumstances such as power-off or power fails, in a Multi Channel Controller structure, write FAT table data in the flash memory of device controller from ETL FAT table to stripe cell, to utilize best the flash memory interface bandwidth.These data are configured to a plurality of pages, (quantity of the page is suitable with multichannel quantity).
What [the 139th section] Fig. 9 A showed is the mapping of compressed page.Unconventional data are stored in the flash memory page by the data that will compress, also can improve the persistence of flash memory, because compression has reduced the size of data, have reduced the storage space requirement in flash memory.The data of compression can be buffered in SSSDRAM impact damper 20, and backup to when buffer memory has been expired in flash memory 30.
[the 140th section] before it being stored in SSS DRAM impact damper 20 or flash memory 30, SSS controller 40 can compress some data.Main frame writes several page datas in normal mode, comes the sector number of presentation logic address (LBA), page number and indication total data length.For example, main frame may write LBA2048 with data 1, SC=128, and this is totally 8 pages, the data of every page of 16 sectors.Compression engine in SSS controller 40 becomes the data compression of 128 sectors the packed data of 48 sectors.The data of the compression of these 48 sectors comprise data head and are stored in some packed datas of the first page compression, and other two pages of packed datas, totally 3 pages of packed datas.With not the compression before 8 pages compare, number of pages significantly reduces.
[the 141st section] SSS controller 40 is stored in these 3 pages of packed datas on the page in SSS DRAM impact damper 20 or flash memory 30 (being stored as packed data 214).The pointer MAP_PAGE_PTR that is stored in compression LBA table 212 points to this page.
[the 142nd section] SSS controller 40 has also created entry in the LBA table 210 of DRAM/PBA table, the LBA table 210 of DRAM/PBA table may be the part of unified mapping table (as unified mapping table 192).Yet the entry in the LBA table 210 of DRAM/PBA table is to encode for being mapped to packed data specially.
Each mapping item in the LBA table 210 of [the 143rd section] DRAM/PBA table comprises the front two that is called as " compressive state position ".If first compressive state position is 1, expression compression access; If first compressive state position is 0, represent that main frame is to the not routine access of packed data.For example, the 127th page is used PTR1 to be mapped to unpressed data.
[the 144th section] when being 1 in first compressive state position, and second compressive state position is 0, comprises not total size (number of pages) of packed data section in the entry in the LBA table 210 of DRAM/PBA table.If first compressive state position is 1, and second compressive state position is 1, comprises a side-play amount in the entry in the LBA table 210 of DRAM/PBA table so.Side-play amount is the skew to first entry of packed data section, and this entry comprises the size of packed data section.
[the 145th section] writes LBA2048 at main frame with data 1, totally 8 pages of SC=128() this example in, data 1 have 8 pages of entries in the LBA table 210 of DRAM/PBA table page.LBA2048 selects the 128th page in the LBA table 210 of DRAM/PBA table.Having 8 pages of entries in the LBA table 210 of DRAM/PBA table is used.First entry comprises total data size, and ensuing 7 entries comprise the side-play amount that refers to back first entry.
When main frame read the 133rd page (LBA=2128, SC=16), the 133rd page of entry in the LBA table 210 of DRAM/PBA table was read [the 146th section].The side-play amount that is stored in the entry of the 133rd page is 5, it refer to back the 128th page entry, wherein comprise the size of the total compression data of 3 pages.Read the entry of the 128th page from compression LBA table 212, ensuing two entries that also comprise compression LBA table 212 of reading, totally 3 pages of entries (sizes of the data of compression).Each entry is pointed to the packed data page in SSS DRAM impact damper 20 or flash memory 30.These three compressed page are read and decompression operation to all, to recover not 8 front page data pieces of compression.Then never extract the data that main frame is reading in packed data.Compression can be consistent with the control algolithm of hardware circuit or firmware.
[the 147th section] Fig. 9 B emphasizes the data stream of user data in SSS DRAM impact damper 20.The main frame data writing is written to data input buffer, and the latter identifies data type (as pagefile, temporary file, user data, FDB or FAT data type).If data will be compressed or encrypt, carry out compression and/or cryptographic operation.
[the 148th section] according to access frequency, user data is classified as frequent access (FA) or non-frequent access (NFA).Frequent access (FA) data are stored in independent buffer memory in the DRAM impact damper.FA and NFA are placed in different buffer memorys, can improve the flash memory persistence.
[the 149th section] then classifies as segregate FA data the data of complete page data or part page.Some parts page data and other part page datas are combined and are become the complete sector data.In order to distinguish different host accesss and LBA, the part sector data is also combined.The NFA data also classify as complete page data and part page data, and wherein part page data and other complete sector are in the same place with the part sector combination.
[the 150th section] Fig. 9 C is pagefile in the DRAM impact damper and the data stream of temporary file.The main frame data writing is written to data input buffer, and the latter identifies data type (as pagefile, temporary file, user data, FDB or FAT data type).If data will be compressed or encrypt, carry out compression and/or cryptographic operation.
[the 151st section] page data and temporary file are stored in places different in the impact damper of DRAM.The persistence of distributing special-purpose pagefile buffer zone and temporary file buffer zone can improve flash memory.
[the 152nd section] after compression and/or encrypting, the page data of isolation is classified as complete page data or part page data.Some parts page data and other part page datas are combined and are become the complete sector data.The part sector data also can be combined in becomes different pagefiles together.
[the 153rd section] temporary file also classifies as complete page ephemeral data and part page ephemeral data in compression and/or after encrypting, other complete sector of part page data and temporary file are in the same place with the part sector combination.
[the 154th section] Figure 10 is one and according to host requests, the data type classified, and the process flow diagram that pagefile, temporary file, FAT, the FDB of user data process dispatched.Comprise a logical address in the request of main frame, for example the LBA of an index of mapping table 192, step 304 are unified in conduct.A coupling entry from unified mapping table 192 is read.Former positions of described coupling entry are data qualifier bits, are used for representing which type of data is stored in this logical address.Depend on data qualifier bit, different processes is dispatched.
[the 155th section] if the data qualifier bit of described coupling entry is 001, i.e. step 306, and these data are used for the page field of the exchange from the primary memory to the peripheral storage device, and exchange is carried out by the memory manager on main frame.These files do not need to be stored in flash memory, thereby can reduce the wearing and tearing of flash memory.Invoking page document flow 308 sees Figure 11-12 for details.
[the 156th section] if the data qualifier bit of described coupling entry is 01, i.e. step 310; The temporary file that these data are used for not needing to be stored in flash memory calls temporary file flow process 312, sees Figure 11-12 for details.
[the 157th section] is when the data qualifier bit 100 of described coupling entry, i.e. step 314; These data are used for the FAT entry.Call FAT flow process 316, see Figure 13 for details.
In [the 158th section] step 315, when the data qualifier bit of described coupling entry is 101, these data are used for the FDB entry, call FDB flow process 318, see Figure 11-12 for details.
[the 159th section] do not belong to above-mentioned any type when data qualifier bit, and namely the calling data document flow 320.Data file flow process 320 sees Figure 14-15 for details.Data file is user data and application data, and these data should first be stored in data write cache 154, then is copied to flash memory in the situation that drive out of data write cache 154.
If data qualifier bit is 000, so described coupling entry is not yet distributed [the 160th section].This is that first main frame to this logical address writes.Data file flow process 320 shown in Figure 10 is determined main frame in the data that show what type, and carries out rational flow process.
[the 161st section] Figure 11 has shown a process that is used for reading pagefile, temporary file or FDB file.Each data type may have independent subroutine, and is perhaps similar because read process, can use combination process.
[the 162nd section] is because before reading out data, main frame always writes data into flash drives, and in the main frame ablation process, entry must be loaded in unified mapping table 192, therefore, should find the entry of a coupling in unified mapping table 192, read to serve all main frames.
In [the 163rd section] step 402, if the data qualifier bit of described occurrence is XX10 or 010, the entry of coupling is used for complete page data (FP is with reference to Fig. 6) so.The pointer PTR that this coupling entry reads from unified mapping table 192 is used for finding data, data is read on main frame, i.e. step 404.
In [the 164th section] step 402, if the data qualifier bit of described occurrence neither XX10 neither 010, mates so entry and is used for part page data (PP is with reference to figure 6).The pointer PTR that this coupling entry reads from unified mapping table 192 is used for finding sub-sector map, and namely execution in step 406.The initial sector counting is set to 0, and namely execution in step 410, in order to read first sector entry in sub-sector map.If first of the sub-sector entry of current sector is 0, namely execution in step 412, and complete sector will be read from SSS DRAM impact damper 20 pointer SCTR positions pointed so, and namely execution in step 414.Pointer SCTR current sector entry from sub-sector map 194 reads.Current sector is incremented to points to next sector.If current sector is not last sector, namely execution in step 408, first position of the sub-sector entry of the current sector of systems inspection, and namely execution in step 412, and repeat sectors process.
[the 165th section] if first of the sub-sector entry of current sector is 1, namely execution in step 412, and the part sector is read from SSS DRAM impact damper 20 so.The part sector is arranged on SCTR pointer of reading from sub-sector map 194 current sector entry page pointed, and namely execution in step 416.The byte offsets of the beginning of part sector is A(N in this page), and the length of part sector is LEN(N), current sector entry reads all data from sub-sector map 194.A part sector can only be arranged, so this process finishes in every page.
[the 166th section] Figure 12 A-C shows a process that is used for writing pagefile, temporary file or FDB file.Each data type may have independent subroutine, perhaps because ablation process is similar, can use combination process.
[the 167th section] is in Figure 12 A, if main frame provides a new complete page data, and step 420, but the data qualifier bit of the coupling entry in unified mapping table 192 is not XX10 or 010, step 424, and old data are used for part page (PP).By all 1's being write all 16 entries, step 426, the position that in sub-sector map 194, entry pointer SPTR points to is released, for using in the future.Because new data are corresponding with the complete page, and no longer need sub-sector map 194, so the old sub-sector map 194 that pointer PTR points to also is released.New pointer PTR is written on coupling entry in unified mapping table 192, and data qualifier bit is changed to XX10 or 010 with expression complete page (FP), step 428.Then the host data of complete page will be written in SSS DRAM impact damper 20 that pointer PTR position pointed of unifying coupling entry in mapping table 192, and namely execution in step 422.
In [the 168th section] step 424, data qualifier bit in the coupling entry in unified mapping table 192 is XX10 or 010, legacy data is corresponding with complete page, and this process just can be leapt to step 422, and the complete page data cover falls the legacy data in SSS DRAM impact damper 20.
In [the 169th section] step 420, provide the new data of part page when main frame, this process on Figure 12 B is proceeded.Neither 010 if the data qualifier bit of the occurrence in unified mapping table 192 is not XX10, namely execution in step 430, and legacy data is used for part page (PP).The position that pointer SPTR in sub-sector map 194 in entry points to is released, in order to use in the future, and step 432, the old sub-sector map that pointer PTR points to also is released.
[the 170th section] old part sector data needs deleted.SSS controller 40 checks the data splitting on currentitem side.If there is no data splitting, SSS controller 40 will be put the sign of end pointer, makes this page can be used for following partial data combination.If more than one of such combination by filling the gap of old partial data, moves up every other combination, and changes the A(N of its corresponding sub-mapping table).
[the 171st section] gap sector map 194 is arranged in SSS DRAM impact damper 20, and namely execution in step 436, creates the PTR pointer, this free list of this pointed.This new pointer PTR is written in coupling entry in unified mapping table 192, and for instruction unit paging (PP), data qualifier bit is changed to XX11 or 011, and namely execution in step 438.
In [the 172nd section] step 430, if the data qualifier bit of the coupling entry in unified mapping table 192 is XX10 or 010, be that old data are used for complete page (FP), execution in step 434, based on another request, complete data page in SSS DRAM impact damper 20 is released, in order to using in the future.Gap sector map 194 is arranged in SSS DRAM impact damper 20, and namely execution in step 436, creates the PTR pointer, this free list of this pointed.This new pointer PTR is written in coupling entry in unified mapping table 192, and in order to indicate partial page (PP), data qualifier bit is changed to XX11 or 011, and namely execution in step 438.
[the 173rd section] in Figure 12 C, new partial page data by a sector, a sector write in SSSDRAM impact damper 20, the sector entry is loaded in sub-sector map 194.
[the 174th section] if be a complete sector from the current sector of main frame, namely 324, the 1 of execution in step are 0, have the new entry of pointer SPTR and sector count SC to be written in sub-sector map 194, step 326.Complete both host data sectors is written to the position of SPTR and SC sign in SSS DRAM impact damper 20, step 390.If another both host data sectors is arranged, step 392, current sector will increase progressively, step 314, the then process of repeating step 324 and back.Otherwise process finishes.
[the 175th section] if be a part sector from the current sector of main frame, step 324, and data head will produce and meeting and combine from the part sector data of main frame and form a combined page.This combined page collects the part sector, and namely execution in step 302.Point to the start byte side-play amount A(N in the pointer SPTR, this combined page of this combined page) and the length LEN (N) of part sector data and data head be written in sub-sector map 194 in a new sub-sector entry, step 328.This process finishes, because for every host requests, only can receive a part sector from main frame.Data head comprises main frame LBA(piece+page+sector) information.The tail end pointer that data are added is later indicated the availability of the page.
[the 176th section] Figure 13 A-B has shown a FAT path that leads to super durable flash drives.In Figure 13, main frame reads or data writing to the ranges of logical addresses of the FAT that is determined by the SSD unprocessed form.In the time of the main frame data writing, namely execution in step 440, observe Figure 13 B; For the main frame reading out data, Figure 13 A continues step 442, and here, the address realm that logical address is brought with the address space of FAT1 and FAT2 compares.If logical address (FAT zone the first half) in the FAT1 spatial dimension, the page side-play amount is calculated as the remaining part of start address that deducts the FAT1 zone from the LBA of main frame so, and namely execution in step 444.In step 446, the FAT entry is read by an address from SSS DRAM impact damper 20.The start address (may be different from the FAT address in logical address space) that this address equals the FAT in SSS DRAM impact damper 20 adds the value of the page side-play amount gained that step 444 is calculated.These FAT data are returned to main frame and read to complete.
[the 177th section] if the logical address second portion of zone (FAT) in the FAT2 spatial dimension, the page side-play amount is calculated as the remaining part of start address that deducts the FAT2 zone from the LBA of main frame, step 448 so.In step 446, the FAT entry is read by an address from SSS DRAM impact damper 20.The start address (may be different from the FAT address in logical address space) that this address equals the FAT in SSS DRAM impact damper 20 adds the value of the page side-play amount gained that step 448 is calculated.These FAT data are returned to main frame and read to complete.Note that single FAT entry is stored in SSS DRAM impact damper 20, be used for from host access FAT1 and FAT2.
[the 178th section] in Figure 13 B, main frame is to the FAT data writing.When logical address in the FAT1 spatial dimension (FAT zone the first half), step 450, the page side-play amount is calculated as the remaining part of start address that deducts the FAT1 zone from the LBA of main frame so, namely execution in step 452.In step 454, be written into an address in SSS DRAM impact damper 20 from the FAT entry of main frame.The start address that this address equals the FAT in SSSDRAM impact damper 20 adds the value of gained after the page side-play amount that step 452 calculates.The flash memory mode bit of FAT in FAT mapping table 202 is updated to 10, and expression FAT1 is upgraded by main frame, but FAT2 not yet upgrades, and the FAT1 data in flash memory 30 are old, and namely execution in step 456.The page side-play amount of using step 452 to calculate, the sub-map entry in FAT mapping table 202 is accessed.
In [the 179th section] step 450, in the FAT2 spatial dimension (FAT zone the latter half), the host data corresponding with FAT2 is left in the basket when logical address, and namely execution in step 453.The single FAT entry that is stored in SSS DRAM impact damper 20 is written in a front host access.The flash memory mode bit of FAT in FAT mapping table 202 is updated to 11, and expression FAT1 and FAT2 are upgraded by main frame, and the FAT1 data in flash memory 30 and FAT2 are old, and namely execution in step 458.The page side-play amount of using step 453 to calculate, the sub-map entry in FAT mapping table 202 is accessed.
[the 180th section] mode bit can be used for regularly or in power-off/power failure, will be from the invalid FAT content backup of SSS DRAM impact damper 20 in flash memory 30.May need to check two mode bits of FAT mapping table 202.
[the 181st section] Figure 14 has shown the super durable flash drives subscriber data file how processing host reads.User data may comprise the user data of host stores, or the application program carried out on main frame of the user data of storing, but do not comprise temporary file, pagefile, FAT and FDB entry etc., because these data are just screened by the described step of Figure 10 before calling data file process 320.Be called and during the host requests read operation, the process of Figure 14 is called in data file process 320.Be called and the host requests write operation in data file process 320, the process of Figure 15 is called.
[the 182nd section] uses the logical address of host requests to find the entry of coupling in unified mapping table 192.Former that read described occurrence obtain data qualifier bit.If data qualifier bit is 11X1, the legacy data of so described occurrence is stored in flash memory 30, will be from flash memory 30 sense datas.When data qualifier bit is 11X0, described occurrence just refers to the data of storage in SSS DRAM impact damper 20, so will access the data that DRAM reads to obtain main frame, step 462.
[the 183rd section] if data qualifier bit is 110, step 460, data are used as complete page stores, read the complete page from SSS DRAM impact damper 20, step 476, during to find with the pointer PTR of described occurrence the position of sense data.If main frame is only filed a request to the several sectors on this page, extract these sectors and they are sent to main frame from whole page.If in determining step 462, data are stored in flash memory 30, use so pointer PTR to read flash memory 30 but not SSS DRAM impact damper 20.
If data qualifier bit is not 110, step 460, data are stored in part page (PP) [the 184th section].Find sub-sector map 194 with the pointer PTR that reads in coupling entry in unified mapping table 192, it is carried out read operation, step 466.Current sector is initialized to zero, step 464, or be initialised to other values of some host requests.The entry corresponding with current sector in sub-sector map 194 is read out.If first of this entry is 0, step 468, entry is pointed to complete sector so.Current entry reading pointer SCTR from sub-sector map 194 is used for finding the position of reading out data, depends on the result of 462 steps of front, may be in SSS DRAM impact damper 20 or flash memory 30.Current sector increases progressively, step 472.If current sector is not last sector, this process loops back step 468, step 474.This process ends at last sector.
[the 185th section] if first of the entry in the sub-sector map 194 corresponding with current sector entry is 1, step 468, entry directed section sector so.The pointer SPTR that the current entry of use from sub-sector map 194 read, the start byte side-play amount A(N in combined page), the length LEN (N) of part sector data and data head, the combination page reading section sector data from DRAM or flash memory (result that depends on the step 462 of front).This part sector data is sent to main frame together with complete sector data that early step 472 obtains.Because each host requests only allows a part sector, so the process that reads finishes.
[the 186th section] Figure 15 A-I has shown the how subscriber data file that writes in frequent access region and non-frequent access region of processing host of super durable flash drives.User data may comprise the user data of host stores, or the application program carried out on main frame of the user data of storing, but do not comprise temporary file, pagefile, FAT and FDB entry etc., because these data are just screened by the described step of Figure 10 before data file process 320.Be called and during the host requests read operation, the process of Figure 14 is called in data file process 320.Be called and during the host requests write operation, the process of Figure 15 is called in data file process 320.
[the 187th section] in Figure 15 A, the access counter of existing LBA (Logical Block Addressing) increases, step 810.This access counter is distinguished for distinguishing frequent access (FA) district and non-frequent access (NFA).These two zones are stored in respectively FA cache memory section and NFA cache memory section in DRAM impact damper 20.
After [the 188th section] enables compression, step 812, host data is transmitted to compression engine, step 814.Packed data with the new data head is usually less, and new, a less sector count (SC) that calculates is arranged.If compression does not cause size of data to change, such as the increase because of the packed data head, controller can be selected not carry out compressing.Compression entries and mapping table such as the LBA table 210 in Fig. 9 A and compression LBA table 212, have been full of entry.Packed data and new SC have replaced original host data and SC, step 816.
During [the 189th section] encryption enabled, step 818, host data or packed data are sent to crypto engine, step 820.Enciphered data has replaced original data, but size of data remains unchanged, step 822.
[the 190th section] when the counting of access counter during greater than threshold value N, step 824, and the destination of access is frequent access (FA) LBA, flow process shown in Figure 15 B continues.When the counting of access counter during less than threshold value N, step 824, (NFA) LBA is frequently accessed with regard to right and wrong in the destination of access, and flow process shown in Figure 15 C continues.
[the 191st section] is in chart 15B, when main frame writes the new FA data of whole page, step 480, execution graph 15B, flow process shown in D.Be used for seeking the entry of coupling in unified mapping table 192 from the logical address of main frame.When the data qualifier bit of coupling entry was 000, step 482 did not have the data that write before main frame on this address.Flow process skips to Figure 15 D.
When [the 192nd section] was 111 when the data qualifier bit in the coupling entry, step 484(tested in early days and has got rid of other possible data type bit patterns), the old page is part page (PP).Carry out old sector scale removal process 490(Figure 16), discharge old partial page data and the old then continuation of flow process shown in Figure 15 D of sub-sector map 194..
When [the 193rd section] was 110 when the data qualifier bit of coupling entry, namely execution in step 484, and the old page is complete page (FP).When data qualifier bit was 1101, namely execution in step 486, and legacy data is stored in flash memory 30.The pointer PTR data pointed that the coupling entry reads from unified mapping table 192 are placed into garbage collector in order to clear up later on and reuse, step 461.Then flow process shown in Figure 15 D continues.
[the 194th section] when data qualifier bit was 1100, namely execution in step 486, and legacy data is stored in SSSDRAM impact damper 20.Skip to Figure 15 D, namely execution in step 492, and new host data is written in SSS DRAM impact damper 20, the pointer PTR position pointed that in unified mapping table 192, the coupling entry reads.The coupling entry need not change.
[the 195th section] other enters the flow of Figure 15 D for all, and usage data type bit 1100 and pointer PTR will unify the position that coupling entry in mapping table 192 writes a special Receiving Host data writing in SSS DRAM impact damper 20, and namely execution in step 488.Data qualifier bit 1100 expressions are stored in the user file of the partial data page in DRAM.Then host data is written into that position in DRAM, and namely execution in step 492.Data write the FA high-speed cache in SSS DRAM impact damper 20 completely maybe will expire, step 650, and then partial data is dished out buffer memory to vacate additional space.The dish out complete FA cache page of buffer memory or complete FA cacheline can be identified, and step 652 is such as by search least recently used (LRU) page.Also can find the blank page in flash memory.The least recently used FA high-speed cache page is copied to the blank page in flash memory, and with " throwing out " FA complete page, namely execution in step 654.Reposition in the pointed flash memory of the page of " throwing out ", rather than the old position in DRAM.Writing flow process finishes.
[the 196th section] writes new partial data page when main frame, i.e. execution in step 480(Figure 15 B), flow process shown in Figure 15 F continues.
In Figure 15 F, when the data qualifier bit of coupling entry was 000, namely execution in step 502, the data that this address does not have main frame to write before [the 197th section].Without the coupling entry, or the coupling entry is not yet assigned to this data type.Do not need to clear up old coupling entry, so flow process is jumped into step 514.Otherwise flow process continues step 504.
When [the 198th section] was 111 when the data qualifier bit of coupling entry, step 504(tested in early days and has got rid of other possible data type bit patterns), the old page is part page (PP).Old part valve district data are sent to garbage collector, step 512.Garbage collector is used for depositing in flash memory 30 sector storage, that covered by new host data.Then flow process shown in Figure 15 H continues.
When [the 199th section] is 110 when the data qualifier bit in the coupling entry, step 504, the old page is complete page (FP).When data qualifier bit is 1101, step 506, old data are stored in flash memory 30.The pointer PTR old flash memory data pointed that the coupling entry reads from unified mapping table 192 are placed into garbage collector, clear up after a while and reuse, step 510.
[the 200th section] when data qualifier bit is 1100, step 506, old data are stored in SSSDRAM impact damper 20.Be stored in SSSDRAM impact damper 20, the pointer PTR old whole page data pointed that the coupling entry reads from unified mapping table 192 is released, as other purposes, and step 508.
[the 201st section] usage data type bit 1110 and pointer PTR will unify the position that coupling entry in mapping table 192 writes a special Receiving Host data writing in SSS DRAM impact damper 20, step 514.Data qualifier bit 1110 expressions are stored in the user file of the partial data page in DRAM.
[the 202nd section] current sector count is initialized as sector 0, and step 516 is write into the new pointer PTR establishment new sub-sector map 194 in position pointed that mates entry, step 518 in SSS DRAM impact damper 20.
[the 203rd section] in Figure 15 H, when main frame is current sector count when sending complete sector, step 324 uses 00, SPTR, SC, writes the entry in the sub-sector map 194 of being selected by current sector count, step 326.Type numerical digit 00 finger is stored in the complete sector in the FA high-speed cache of DRAM, and SPTR is a pointer that points to FA data in SSS DRAM buffer memory 20, and SC is current sector count.Complete sector from main frame is written into the page that in SSSDRAM buffer memory 20, FA high-speed cache pointer SPTR points to, the sector that SC points to, step 330.
[the 204th section] if current sector count is not last sector on the page, step 332, and so current sector count just increases, step 334, flow process is back to step 324, processes the next sector from main frame.
When [the 205th section] is current sector count transmitting portion sector when main frame, step 324, a data head just produces, and then combines the formation combined page with the part sector data from main frame.This combined page collects the part sector, facilitates the access of FA user data, step 322.Type bit is 10, points to the start byte side-play amount A(N in the pointer SPTR, this combined page of this combined page) and the length LEN (N) of part sector data and data head be written in sub-sector entry new in sub-sector map 194, step 329.Type bit 10 expression is stored in the part sector in the FA buffer area of DRAM.This process finishes, because for every host requests, only can receive a part sector from main frame.
[the 206th section] write full or approached when the data in the FA high-speed cache that writes SSSDRAM impact damper 20 and write when full, step 656, and then partial data is dished out buffer memory to vacate additional space.The sector data page of buffer memory of dishing out can be identified, such as by search least recently used (LRU) page.Also can find the blank page in flash memory.The least recently used high-speed cache page is copied to the blank page in flash memory, with " throwing out " part page.Reposition in the pointed flash memory of the page of " throwing out ", rather than the old position in DRAM.Writing flow process finishes.Before data " are dished out " generation, write and wear and tear in order to have reduced flash memory, there are a plurality of data writings of identical LBA not to be written in flash memory 20.
The flow that has shown the FA access in [the 207th section] Figure 15 B, D, F and H, and Figure 15 C, E, G and I have shown the flow of NFA access.In Figure 15 E, step 651 has checked FA buffer memory in NFA buffer memory rather than Figure 15 D, step 650, executable operations on the NFA buffer memory and on the NFA buffer memory.Equally, in Figure 15 I, the NFA buffer memory of part sector use step 323 compresses, and complete sector uses the NFA of step 331 to compress.Remaining FA flow and NFA flow are closely similar.
[the 208th section] process flow diagram of Figure 16 has shown the scale removal process of old sector.Old sector scale removal process 490 is used for clearing up the old entry of sub-sector map 194.Search sub-sector map 194 with the pointer PTR that reads coupling entry in unified mapping table 192.Current sector count is initialized to 0, step 520.
First of the current entry that [the 209th section] points to as current sector count in fruit sector map 194 is 0 o'clock, step 522, and this entry is corresponding with complete sector.The legacy data that the pointer SPTR that reads from current entry points to is placed into garbage collector and wipes and reuse (if flash memory) (in current entry, second is 1), or discharge for another flow process (if in SSS DRAM buffer memory 20) (in current entry, second is 0), step 524.
Current entry in [the 210th section] sub-sector map 194 is covered by 1 ' all s, shows that this entry is invalid, step 526.If current sector count is not last sector in the page, step 528, current sector count will increase, and step 530 begins the repetition flow process from step 522.
First of the current entry that [the 211st section] points to as current sector count in fruit sector map 194 is 1 o'clock, step 522, and this entry is corresponding with the part sector.The legacy data that the pointer SPTR that reads from current entry points to is placed into garbage collector and wipes and reuse (if flash memory) (in current entry, second is 1), or discharge for another flow process (if in SSS DRAM buffer memory 20) (in current entry, second is 0), step 532 because the part sector on the combination page, on combined page, only some is released, and is read from the entry of current sector from byte A (N) beginning of length LEN (N).
Current entry in [the 212nd section] sub-sector map 194 is covered by 1 ' all s, shows that this entry is invalid, step 526.When arriving last sector, step 528, sector clean-up process 490 finishes, and controls and returns to invoked procedure.
[the 213rd section] Figure 17 A-E uses FA high-speed cache and the NFA high-speed cache of complete page and part page to carry out the process flow diagram that user data is processed.In Figure 17 A, host data is identified as user data.Data writing from main frame moves to data input buffer district (DIB), step 830.When the data input buffer district is write when full, step 832, controller is beamed back request to main frame, requires main frame to stop sending the data that newly write, step 834.Then the data that newly write are read from DIB, and compression and/or encryption (as possibility), step 836.User data is divided into complete page or part page data, step 838, and FA or NFA data, step 840 and step 842.
[the 214th section] processed at Figure 17 B middle part paging FA user data.These data are stored in FA part page (FA-PP) buffer memory of DRAM, step 844.When the FA-PP buffer memory is full, step 846 requires main frame to stop sending more polynary certificate, step 848.The part page data that part page data and other main frames write is combined, step 850.This combination operation may require several cycles.When combination operation is completed, step 852, flow process shown in Figure 17 E continues.When combination operation was not completed, step 852 will be received the new data writing from main frame, step 854, and this new data moves to data input buffer district, step 858.If the data input buffer district is full, step 852, controller is beamed back request to main frame, requires main frame to stop sending new data writing, step 860.Flow process continues until combination is completed, step 852.
[the 215th section] processed at Figure 17 C middle part paging NFA user data.The NFA data are stored in NFA part page (NFA-PP) buffer memory of DRAM, in step 864.When the NFA-PP buffer memory is full, step 866 requires main frame to stop sending more polynary certificate, step 868.The part page data that part page data and other main frames write is combined, step 870.This combination operation may require several cycles.When combination operation is completed, step 872, flow process shown in Figure 17 E continues.When combination operation was not completed, step 872 will be received the new data writing from main frame, step 874, and this new data moves to data input buffer district, step 876.If the data input buffer district is full, step 878 controller will be beamed back request to main frame, require main frame to stop sending new data writing, step 880.Flow process continues until combination is completed, step 872.
[the 216th section] in Figure 17 D, complete page FA storage of subscriber data in the FA of DRAM complete page (FA-FP) buffer memory, step 882.When the FA-FP buffer memory full, step 886, the LRU page in the FA-FP buffer memory will " be thrown into " in the NFA-FP buffer memory so, step 888.This may cause the NFA-FP buffer memory to be filled with, and therefore, needs inspection NFA-FP to have or not and is filled with, step 890.
[the 217th section] complete page NFA usage data is stored in NFA complete page (NFA-FP) high-speed cache of DRAM, step 884.When NFA complete page buffer memory is filled with, step 890, the LRU page in NFA-FP " is thrown into " in flash memory so, step 892.
[the 218th section] in Figure 17 E, when data input buffer district (DIB) when being filled with, step 894, if new data writing is read from the data input buffer district, and compressed/as or to encrypt (as may), flow process skips back to Figure 17 A, step 836.If the data input buffer district is not filled with, step 894 allows main frame to send new data writing, step 896.When the new data writing of receiving from main frame, and these data are when being loaded into data input-buffer district, step 898, if new data writing is read from the data input buffer district, and compressed/or encrypt (as possibility), flow process skips back to Figure 17 A, step 836.
[the 219th section] when FA-PP is cached with new data, step 902, if new data writing and other part pages FA data combine, flow process rebound Figure 17 B, step 850.When NFA-PP was cached with new data, step 904 was carried out flow process rebound Figure 17 C, step 870 if new data writing and other part pages NFA data combine.
[the 220th section] Figure 18 A-B has shown the processing of encrypting the page and compressed page.In Figure 18 A, when main frame to the flash drives data writing, step 336, when compression is enabled, step 338, host data is sent to compression engine, step 340.After enabling compression, step 812(sees Figure 15 A), host data is transmitted to compression engine, step 814.Packed data with the new data head is usually less, and 342 new, less sector count (SC) that calculate in steps.Compression entries and mapping table such as the LBA table 210 in Fig. 9 A and compression LBA table 212, have been full of entry.Packed data has replaced original host data.
When [the 221st section] encrypted, step 344, host data or packed data are sent to crypto engine, step 346.Enciphered data has replaced legacy data, but size is constant, step 348.Then can continue high-level process flow.
What [the 222nd section] Figure 18 B showed is that main frame reads.After this Data Position encryption enabled, step 360, the data that read from flash memory 30 or SSSDRAM impact damper 20 are sent to decryption engine, step 350.Data decryption has replaced enciphered data, step 352.After this Data Position is enabled compression, step 354, the data that read or the data of deciphering are sent to decompression engine, step 356.Consult compression entries and mapping table, such as the LBA table 210 in Fig. 9 A and compression LBA table 212, in order to determine starting point and the whole size of packed data section.Extract from the packed data section actual sector that main frame requires, then step 358, these data have just got back to main frame.
[the 223rd section] data compression can reduce size of data.For dissimilar data, such as video, audio frequency etc., can use many different compress techniques.Every kind of dissimilar data need specific data compression algorithm to realize maximum big or small reduction.Applicable compression algorithm will select to obtain the algorithm of optimum.The data head that is added on packed data comprises the algorithm that compression engine is used.
[the 224th section] another kind of compress technique has reduced the quantity that writes flash memory.The flash memory controller is sought the content of data set.If have similarly, controller can not write flash memory with full content, but with the difference (if the variable increment is arranged between the two) of existing compressed data set and current data set and the available data collection of pointed.If repeat, the flash memory amount of writing can reduce more so.
[the 225th section] can comprise a flow process of following the trail of the piece read error from flash memory.This flow process comes in handy for collecting S.M.A.R.T. self-monitoring, analysis and reporting techniques.S.M.A.R.T. be a regular set, can be by collecting other significant datas of SSD, use then that supplier's order analysis data are debugged, statistics etc.
[the 226th section] can be collected data and may comprise: the power cycle counting, abnormal power cycle counting, bad block count during energising, bad piece stored counts, the piece that contains bad page counting during energising, the accumulation piece that contains bad page counting, the piece that contains bad page counting during energising, the cumulative error page count, the page count that needs extra ECC protection during energising, the page count of the extra ECC protection of accumulation, ECC read error counting during energising, the ECC significant errors counting of accumulation, during energising, main frame LBA reads counting, the main frame LBA of accumulation writes counting, during energising, the flash memory page reads counting, the accumulation page reads counting, during energising, the flash memory page writes counting, accumulation flash memory page writes counting, smallest blocks erase count during energising, largest block erase count during energising, total on time during energising, the accumulation on time.
[the 227th section] useful SSD health and fitness information can be from deriving collection information.Such as, comparison main frame LBA writes counting and the flash memory page writes counting, can provide to write to amplify indication.The flash memory page writes the service life state that counting, total on time, power cycle counting and abnormal power cycle counting can provide SSD102.Supplier can write quantity according to total main frame that the client buys a year number (such as 3 years) or flash drives actual guarantee is provided.The additional Information Availability that provides is in better guarantee policy, but not only uses for the purchase of several years.Guarantee writes quantity as the basis take total main frame of flash drives.The total main frame that is defined as flash drives for the lasting number of times of the specified write/erase of the flash memory dies that increases progressively the flash memory device capacity writes quantity.The number of times that can continue according to the specified write/erase of flash memory dies used and the actual erase of calculating each autonomous block count the to derive residual life of solid state drive (SSD).
[the 228th section] SSD is determined by following factors with/residual life: 1, average write/erase counting is higher than specified write/erase counting; 2, the main frame total data writes counting and writes higher than the total data of flash memory device; 3, write amplification (WA); 4, stand-by block reaches the max cap. ratio.For obtaining all necessary informations, the flash memory device controller need to be managed some S.M.A.R.T. functions.
[the 229th section] for first factor, piece/erase count table 164 has been safeguarded the state of write/erase counter and each piece.All non-bad piece additions, then divided by the quantity of non-bad piece, just can obtain average counter.Also need to be about specified the writing of flash memory type/number of erasures.Such as, be 5000 o'clock when on average writing specified the writing that erase count is 1000, MLC/erase count, SSD's has been 20% with the life-span so, residual life is 80%.
[the 230th section] for second factor, the total data that the flash memory device controller need be managed from main frame writes count accumulation life-span and the total data (both are all in sector location) that writes flash memory device.Such as, when accumulating to such an extent that total data writes and is counted as 100,000, the total data of flash memory device is written as at 500,000 o'clock, and SSD's has been 20% with the life-span so, and residual life is 80%.
[the 231st section] for the 3rd factor, and some sectors and the accumulation flash memory page that write accumulation life-span (data are in sector location) that amplification (WA) can write by the total data from main frame, each page that the flash memory type is relevant write counting (data are in units of pages) derivation.Combine with second factor, can obtain flash memory device service life state more accurately.Such as, when cumulative total is counted as 100,000(sector according to writing), 16 sector/pages, and accumulate the flash memory page write be counted as 3, the 000(page), write so amplification and can be calculated as 3000*16/100,000=0.48.Write to amplify and mean that less than 1 whole flash memory device algorithm has improved the serviceable life of write efficiency and SSD flash memory device.Can be expressed as cumulative total and write amplification according to writing to count multiply by, perhaps the total data of flash memory device writes divided by writing amplification.Combine if write the example that amplifies with in second factor, SSD's has been 9.6% with the life-span so, and residual life is 90.4%.
For the 4th factor, flash memory device need be followed the trail of the bad number of blocks that day by day increases progressively [the 232nd section].Produced the time, flash memory device may have the capacity of carrying out 90% flash memory firm.The flash memory device system will arrange out fixing part for operation code.Certain fixed part is used for metadata table S.M.A.R.T. performance data and collects.Certain fixed part is for the bad piece of manufacturing that has existed.Rest block is as stand-by block.To be write back in flash memory with the swap block district for the persistence that merges flash memory valid data and new data is standby, in order to use less stand-by block.Increased progressively the size that surpasses regulation.As time goes on bad piece increases progressively.Useful stand-by block quantity reduces.When stand-by block quantity is 0, can affect performance with garbage collection activity more frequently not because of the blank block that writes new data.If the quantity of stand-by block reduces to zero, in theory, it is little that free space compares the capacity of claiming, flash memory device can be declared useless.If flash memory device does not use fully, the flash memory device controller can reduce capacity by the sector total quantity of a subregion in the 16 byte cutting recordings that are reduced in main start record (MBR), rather than the declaration flash memory device is useless.If there is the LBA that surpasses new reduction capacity to exist, the flash memory device controller will check FAT and FDB, then revise all relevant FAT, FDB and the LBA data of new LBA address in the new size limited field.
[the 233rd section] can combine above-mentioned all four factors if SSD has used life-span/residual life more complicated.
The total data of [the 234th section] flash memory device write depend on installed capacity (P, such as carry out total internal memory 90%) and flash memory type.Total internal memory is take chip used quantity (N) and die size (size (K) of the interior megabyte of the quantity (J) of the piece in flash memory and each piece) as basic.The flash memory type decided quantity of the supported program/erase cycles of each flash memory blocks (H, MLC are 5000).The total data of flash memory device writes and can be expressed as N*J*K*H*P.Such as, device has 4 MLC chips, and each chip has 8,192 pieces, and each piece has 2 megabyte, and the amount of capacity of device is 90% internal memory so.The total data of flash memory device is written as 4*8,192*2M*5,000*90%=294,912,000 megabyte (or 576,000 sectors write).
[the 235th section] always writes from the expection of flash memory device capacity (the flash memory dies quantity (N) used that depends on device, and flash memory type (such as the MLC of the program/erase cycles of 5000 times (H)) megabyte quantity (K) in number of blocks in flash memory (J) and piece).Entire life that flash memory calculates by the hour estimate to depend on user's use amount, such as the megabyte quantity that writes flash memory every day (G, formula comprise write amplification).Therefore work hours be expected to be N*J*K*H*24/G.Such as, contain 64GB flash memory device (N=4, the J=8 of multilevel-cell (MLC) (H=5,000), 192, K=2) write 8,000 megabyte (G=8,000) every day in working environment, result obtains 1,069, the expected life of 400 hours (44,558 days or 122 years).The ratio of the ratio that in fact, the number percent in SSD life-span used can be by bad number of blocks and total block data amount, average block write/erase counting and the flash memory write/erase counting of regulation etc. is calculated.Such information reminding user takes the necessary measures and avoids fault-time.
The function of the Data Collection that [the 236th section] carried out can help user and firmware engineering teacher to assess the firmware operational excellence degree of super permanance SSD.The quantity that writes that writes quantity and flash memory by comparison means can realize the real amplification that writes.By comparing each piece write/erase counting, minimum/maximum/average counter can show the good degree (dynamically consuming balance and static consume balance) of consuming balanced algorithm.
[the 237th section] mean time between failures (MTBF) value prediction is the important element of product development.The runtime summation can obtain mean time between failures divided by the quantity that fault detected.Each runtime obtains by deducting (after the maintenance) working time (outside the plan) stop time.The all working of the extended cycle of operation of this application regulation, such as compression, data write buffer memory, ECC, bad page management, endurance standby/exchange, various forms etc., can cause the increase of MTBF value.
May there be read error in [the 238th section] some pieces when using first order ECC.Use the more powerful ECC of more ECC position to can be used for these pieces.
[the 239th section] will increase progressively a great read error counter when using more powerful secondary ECC can't correct the read error of generation.These ECC error counters can be used by the piece supervisory routine, when determine the quantity of every page of ECC used position in piece is increased to secondary ECC, or when piece are labeled as bad piece and remove physical block and wait until rear use.
[the 240th section] S.M.A.R.T. data collector 170 may need the memory headroom of one or two page.Controller comes the mapped page purposes with the LBA page address that exceeds main frame LBA scope.
[the 241st section] Figure 19 A-D has demonstrated the flow process that detects and process the bad page and bad piece.In Figure 19 A, in case certain piece in flash memory 30 is wiped free of, the erase counters of this physical block is incremented, and the state of piece is changed to sky piece (000) or the empty piece (100) of bad page is arranged, the state of piece and the state of current page before depending on, step 554.Piece/erase count table 164(Fig. 3) insufficient space of DRAM is stored in SSS DRAM impact damper 20, if will be backed up in flash memory 30.Piece/erase count table 164 comprises the erase counters of each physical block and the state of this piece.Bulk state can be a three-bit value, the 000 blank good piece of expression, and 011 and 111 bad pieces of expression, 100 expressions had both comprised the bad piece of part that bad page also comprises good page.
[the 242nd section] piece/erase count table 164 also can be included in the page status table of finding bad page in certain piece.The good page of 000 value representation of page status, the protected page of 100 secondary ECC rather than 25 one-level ECC is used in 001 expression, and 010 expression has used the page, 110 representation pages to contain rubbish/pruning data, and 11X represents bad page.
After [the 243rd section] erase block, check the state of each page in this piece.Read the page status table of this physical block, step 556, current page is initialized as the page 0.When if the current page state is 11X, step 562, current page has been labeled as bad page so.This page does not need further processing.When if current page is no more than in piece last page, step 560, current page increases to the lower one page in piece, step 558, and next current page repeats this flow process, step 562.
In Figure 19 B, in physical block, all pages are all through processing [the 244th section].In piece, the quantity of all bad pages is definite, step 564.When the counting of the bad page in piece surpasses when limiting the quantity of T3, step 566 announces that this piece is bad piece.The state of this physical block in piece/erase count table 164 becomes 011, step 568.Do not re-use this physical block.Reduce bad block counter of part (BAD_BP_CNT) and increase progressively bad block counter, step 570.
[the 245th section] in Figure 19 C, current page is not labeled as the bad page in advance, step 562(Figure 19 A).Clash operation all positions in the page are erased to erasure values, such as 1, the position of reading current page, look at whether to wipe all positions.Obtain the number count of the position in the erase status page not, such as 0, step 574.These are error bits.But ECC can correct these mistakes, if the quantity of bit-errors is very little, this page still can use so.
[the 246th section] represents too many error bit when the position counting of not wiping is less than first threshold T1(; even use additional software ECC protection; still increased the risk of applicable this page); step 572; and the state of current page is that the page is when needing protection (XX1); step 576, this page has used secondary ECC to be labeled as to need protection so.Page status becomes the blank page (001) that needs protection, step 582.Get back to Figure 19 A and process next current page.
[the 247th section] is less than first threshold T1 when the position counting of not wiping, step 572, and also the state of current page is not when needing protection the page of (XX1), step 576, and the page is protected without secondary ECC so.When not wiping position counting greater than Second Threshold T2 (the error bit level that expresses possibility and gross mistake occurs and need additional software ECC to help to correct a mistake after causing), step 578, secondary ECC page counter increases progressively, step 584, page status becomes 001, step 582, and if when host data is stored in this Physical Page, secondary ECC will use afterwards.Get back to Figure 19 A and process next current page.
[the 248th section] when the page without secondary ECC protection, step 576, and when not wiping the position counting and being not more than Second Threshold T2, step 578, page status is good so.One-level ECC is enough to correct the anticipation error in this current page.If unmarked is the good page, page status just becomes 000, step 580.Get back to Figure 19 A and process next current page.
[the 249th section] in Figure 19 D, current page do not wipe the position more than first threshold T1, step 572(Figure 19 C).Surpass threshold value T1 representation page not wipe the position more than the position that secondary ECC can correct; The page can't be used safely for bad page.
[the 250th section] when the physical block state be in piece during bad page (1xx), step 586, this piece has been marked as bad page piece in piece/erase count table 164.In this piece, other bad pages are arranged, do not need to change the state of piece.But, by changing the state of the page in the page status table into 110, current page can be labeled as bad page, step 592.Increase progressively bad page counter, in step 594 step, then return to Figure 19 A and process next current page.
[the 251st section] when the physical block state was not 1xx, in step 586 step, piece is unmarked in piece/erase count table 164 was bad piece of part.In this piece without other bad pages.The state of piece in piece/erase count table 164 is changed to the blank block (100) that contains the bad page, step 588.Increase progressively bad block counter of part (BAD_BP_CNT), step 590.And, make the page status in the page status table into 110, just current page is labeled as the bad page, step 592.Bad page counter increases progressively, and then step 594 is returned to Figure 19 A and processed next current page.
[the 252nd section] SSD can comprise many flash memory dies (such as 16 flash memory dies).May run into some special circumstances, such as one side or whole chip when flash memory dies are bad.If capacity excess, the flash memory capacity of SSD can absorb the capacitance loss of one side or whole flash memory dies.Particular algorithm that can the operative installations controller is avoided loss, such as recovering data, adjusting the stripe unit size of flash memory device, in order to avoid flaw face or chip are arranged.Can use idle chip to change out of order chip, realize over capacity.
[the 253rd section] Figure 20 A-C shows the initialization flow process when mapping table and other DRAM zone switch on power.In Figure 20 A, when connecting power supply on SSD, read power-off pointer, step 660 from flash memory.This power-off pointer is arranged at last power supply off period.When the power-off pointer is normal, step 662, power cycle counting (PCC) increases progressively step 664.Otherwise abnormal electric power cycle count (AB_PCC) increases progressively step 668.
[the 254th section] relates to two kinds of possible schemes herein.The flash memory of option A when more new power disconnects, and option b is copied to flash memory with the image of DRAM when power supply disconnects.As operational version A, step 670 is when abnormal power-down being detected, with various forms, such as page status table, compression LBA table, piece/erase count table, page-map and sub-sector map and sorted table, be copied in flash memory 30 step 676 from DRAM impact damper 20.Be copied in the FAT district of DRAM impact damper 20 being stored in FAT2 table in flash memory, step 678, and in DRAM establishment FAT sector map.
[the 255th section] is when normal power down being detected, step 662 is with different forms, such as page status table, compression LAB table, piece/erase count table, page-map and sub-sector map and sorted table, be copied in flash memory 30 step 672 from DRAM impact damper 20.But the FAT1 of storage table is copied to from flash memory in the FAT district of DRAM impact damper 20, step 674, and in DRAM establishment FAT sector map.Therefore, when normal power down has been selected FAT1, abnormal power-down will be selected FAT2, because main frame first write FAT1 before writing FAT2, and the main frame FAT2 that may have no time to write during the phase in abnormal power-down.
[the 256th section] in Figure 20 B, the FDB entry is copied to DRAM from flash memory, and FDB sector map creates in DRAM, step 680.Use supplier order obtains the LBA scope of pagefile, step 682 from main frame.Pagefile district's establishment of DRAM impact damper 20, step 684, the mapping table of pagefile and sub-mapping table also create.
[the 257th section] creates the temporary file district in the DRAM impact damper, step 686, and create mapping and the sub-mapping table of temporary file.Because during power-off, temporary file is wiped free of but not is copied to flash memory, so temporary file is not copied to DRAM from flash memory during energising.
[the 258th section] DRAM reads buffer memory and DRAM and writes to be buffered in DRAM impact damper 20 and arrange, and step 688 also can arrange in related tables.When user or firmware become scheme into A or B, scheme pointer position also changes, step 689.
[the 259th section] compared with flash memory, and reading buffer memory and writing buffer memory in the DRAM impact damper is smaller.There are a lot of management by methods to read the use of buffer memory.A kind of usage depends on the operational phase, such as the initialization that switches on power, a part of code of preload from flash memory (being fixed by the user), so as accelerating initialization and after wipe.Another kind of usage depends on that the user uses and can force to distribute a part to read buffer zone for this application, and can wipe after withdrawing from application.This application is relevant with the time, such as the backup at midnight also logs in work in the morning.A kind of algorithm can be used for carrying out the supervision to the read buffers flow of particular applications; This can get rid of large-scale application or the inessential problem that reads the buffer memory bulk zone of occupying of file; Only have wherein sub-fraction can stay the read buffers district.This bootable more effectively use is read buffer memory.And another usage be use algorithm supervise and analyzes recently or more often use, stay the reading out data that reads in buffer memory.If read the insufficient space of buffer memory, those are not will being capped of using or not too often use recently.
[the 260th section] in the Multi Channel Controller structure, if the current accessed district not at buffer area, Setup Controller can arrive from flash memory 30 reading out datas and by multi-channel structure and read buffer memory and mapping table 151.Data can be original, compression, that encrypt, synthesis classification or the above-mentioned type.Controller is fetched raw data according to the reading that records in each mapping table from read buffer memory, then data are sent back to main frame 100.
In Figure 20 C, for the abnormal power-down of operational version B, the DRAM reflection that will preserve before outage was copied to DRAM impact damper 20 from flash memory, step 690 went on foot [the 261st section].The DRAM reflection comprises a lot of forms and the impact damper in dynamic random dynamic storage impact damper 20.Processing is retained in Host Command undetermined in data input buffer, step 692.Data in DRAM are write impact damper or the standby valid lines with swap block of persistence upgrade and write in flash memory, step 694.In DRAM reflection, any renewal of FAT or FDB all is copied in FAT1, the FAT2 or FDB district of flash memory, step 696.Also the renewal with page status table, compression LBA table, piece/erase count table, page-map table or sub-sector or sorted table writes flash memory, step 698.DRAM old in erase flash memory videos, and is aside that next DRAM reflection creates a new zone in flash memory, in case abnormal power-down, step 699.
[the 262nd section] Figure 21 is the flow diagram of outage flow process.When power supply is normally closed, step 702, the power-off pointer is set as normally so, step 710.Use battery or other backup batteries, All hosts order undetermined in the deal with data input buffer, step 712.
[the 263rd section] normal powered-down is the order of receiving from main frame.Voltage display or comparator can detect voltage and descend suddenly and trigger the disconnection of SSD controller.Interrupt routine can arrange the outage flow process so.When abnormity of power supply disconnects, step 702, the power-off pointer is made as extremely, step 704.When operational version B, step 706, so with the content replication of DRAM impact damper 20 to the clear area of flash memory, step 708.All the elements of DRAM impact damper 20 or can copy only for the content of selected areas.The DRAM zone can be by priority or continuous compound rate.
[the 264th section] is different from normal power down, and option A will be abandoned the data in impact damper 152.When operational version A, when perhaps normal power down had been completed the processing of Host Command, the data of DRAM write impact damper or the standby valid lines renewal with swap block of persistence writes in flash memory, step 714.Any renewal of FAT in DRAM reflection or FDB is copied in FAT1, the FAT2 or FDB district of flash memory step 716.Also the renewal with page status table, compression LAB table, piece/erase count table, page-map table or sub-sector or sorted table writes flash memory, step 718.
The protection of [the 265th section] multilayer power-off protection can guarantee that data are protected.The standby power supply 41 of main frame provides power supply for whole system when primary power breaks down.This time of having given SSD device 102 abundances with the data backup in DRAM impact damper 20 to flash memory 30.If SSD102 and host power supply disconnect, even having the additional capacity of electric capacity or super capacitor, standby power supply 42 can't power to guarantee some of them, the data backup that DRAM impact damper 20 is interior of sufficient electric weight is still arranged to flash memory 30.
[the 266th section] restarts for anti-locking system, and device is completed identical order until then outage switches on power.Withdraw from computing machine, user account is closed, but computing machine is still preserved easy access, so that user's login next time.When withdrawing from, invalid data and meta information table are updated in flash memory 30, identical during with powered-down.
[the 267th section] for the portable unit of charged pool, such as smart mobile phone, panel computer, notebook etc., device will detect battery electric quantity to be reduced, and stopping device.Before closing, Setup Controller is with the closer peripheral unit, such as SSD102.In this case, power supply is from the battery of portable unit.
Another guarantees that the method for DRAMETL relevant data is that it is copied to multilevel-cell [the 268th section].During power-off, effectively copying of ETL data can be retained in multilevel-cell.When switching on power, the data of ETL can load back DRAM from multilevel-cell.Can record a small amount of difference, revise clone method.This difference will reduce the quantity of copy data, therefore reduce writing of multilevel-cell.
[the 269th section] for senior ECC protection system, discusses following algorithm.The ground floor protection is to store the built-in ECC holding circuit (such as 24 ECC) of the protected data of generation with the unnecessary byte of every page.If ground floor protection fault position reaches predeterminated level (such as 12), can use second layer software ECC maker, generate software ECC(such as 50), further more protection.If ground floor ECC fails correction of data, use so second layer software ECC storage correct data.The protected data that second layer software ECC generates and detect table and will be stored in DRAM impact damper 20 according to a rule (such as according to the time that consumes, the capacity of distribution etc.) or when the situation of power-off or power fail, and be copied in flash memory 30.
[the 270th section] another kind of method is to use low density parity check code (LDPC), and this check code is a kind of error correcting code of linearity.Be different from ground floor ECC protection, the method can increase the extra error correction ability.
[the 271st section] can be by all strip data being carried out RAID5 and so on parity checking or to by carrying out the 3rd layer of ECC for a stick that needs special protection generates odd and even data.The protected data that the 3rd layer of bar tape parity ECC generates and detect table and will be stored in DRAM impact damper 20 according to a rule (such as according to the time that consumes, the capacity of distribution etc.) or when power-off or the power fail, and be copied in flash memory 30.
[the 272nd section] if second layer software ECC fails protected data, the 3rd layer of bar tape parity ECC will only have one group of out of order situation of strip data for second layer software ECC.
[the 273rd section], heightened reference voltage or turn down if flash memory can be accepted special command if second or the 3rd layer of ECC can't store bad data, can use the 4th layer of reference voltage regulator.If flashing storage unit is written into, writing or reading and will cause being written into the interference of unit adjacent cells so.This interference can increase the electronics of this unit floating grid or therefrom remove electronics.In case the quantity of electronics causes output voltage to cross the border of basic voltage, reads so incorrect.According to flash designs, reference voltage is regulated the regulator (such as 3 of higher levels, 3 of lower levels) that some may be arranged.By beginning the on probation of each flow process by flash memory dies used and the special layers that the read error accumulation of knowing determines.If data can't be stored, next reference voltage levels so on probation is until all possible layer is all through overtesting.If data are successfully stored, can use reference voltage levels to begin next reference voltage adjusting test.If all reference voltage levels all can't be stored data, use so layer 5.
[the 274th section] each reference voltage levels may be all with counter.When data were successfully stored, corresponding counter will increase progressively.Which layer these counters help to find out is suitable for dealing with problems most.
[the 275th section] provides the ECC layer 5 of protection by all reading results of collecting each reference voltage.The maximum algorithm of intending right (PRML) and so on of local acknowledgement can be used for analyzing data and stores raw data.
[the 276th section] can provide more senior ECC protection by main frame 100 as a kind of selection.Main frame generates more senior ECC protected data and link information.Then use supplier's demanded storage ECC data and with being connected of DRAM impact damper 20, move at last the stand-by block district of flash memory 30.
[the 277th section] Figure 22 A-B has shown the fetch program of multilayer ECC.In Figure 22 A, at every turn the reading of physical block in flash memory 30, each of this piece reads counter (LBA_RD_CNT) and increases progressively step 540 by sector count (SC).When reading middle generation mistake, step 720 is carried out so ECC and is checked 722 as ECC.When the ECC mistake higher than first threshold T1, step 724, and during higher than Second Threshold T2, step 726, and still can correct the time, this data are corrected and provided to step 728 so, step 732, and increase progressively ECC and read counter ECC_RD_CNT.When mistake during higher than T1 but lower than T2, if the 3rd layer of ECC or software ECC also exist, this moment, the 3rd layer of ECC or software ECC will generate so, step 730.The software ECC that generates is stored in DRAM impact damper 20, and is managed by SSS40.According to rule, this information will be stored in flash memory 30.
[the 278th section] in Figure 22 B, for the mistake that can't correct, when software ECC had existed, step 734 was used it for so and is corrected a mistake, step 736.Increase progressively ECC2 and read counter (ECC2_RD_CNT).When mistake was corrected, step 738 can obtain data, step 732 so.
[the 279th section] breaks down as ECC, but has stripe parity, step 742, and when being no more than one group of strip data and breaking down, step 744 can be used other group band and parity checking recombination datas, step 746 so.Band reads counter (STRP_RD_CNT) and just increases progressively.Otherwise, call reference voltage converse routine 740.
[the 280th section] shown the multilayer ECC fetch program of simplifying in Figure 23 A-B.In Figure 23 A, at every turn the reading of physical block in flash memory 30, each of this piece reads counter (LBA_RD_CNT) and increases progressively step 541 by sector count (SC).When reading middle generation ECC mistake, step 750 is carried out so ECC and is checked 752.When the ECC mistake higher than first threshold T1, step 754, but still can correct the time, step 758, data move to the diverse location in flash memory, step 760 so, and can obtain these data, step 762, and ECC reads counter ECC_RD_CNT and increases progressively.
[the 281st section] in Figure 23 B, when there being bar tape parity check and correction, step 756, and be no more than a group and break down, step 764 can be used other group band and parity checking recombination datas, step 766 so.Increase progressively band and read counter (STRP_RD_CNT).Otherwise, call multilayer reference voltage converse routine 740.
[the 282nd section] Figure 24 A-B has shown multilayer reference voltage converse routine.When having called reference voltage converse routine 740, iteration parameter N is set as zero, step 770, and the current state (RVSTATE) of reference voltage register is copied in the setting (RV_REG) of current reference voltage register step 772.Use these reference voltages to arrange order is write in flash memory, step 774, and carry out ECC inspection, step 776.When mistake can't be corrected, step 778, and iteration parameter N is when reaching maximal value 2M, and step 780 increases progressively great counting, step 786 so.Reference voltage converse routine 740 breaks down.Compare with specified reference voltage, the reference voltage adjustment is higher or lower.It is 2M that each higher or low adjustment has M layer, maximal value.
In addition, iteration parameter N increases progressively [the 283rd section], step 782 step, use the lower batch of setting of doing for the test reference voltage, and step 784 step, and program is carried out the lower whorl iteration.
[the 284th section] in Figure 24 B, copies the current iteration reference voltage and sets (RV_REG) and increase progressively reference count, step 788 when mistake can be corrected.Data move to the diverse location in flash memory, step 790, and can use step 792.When data were shown mistake according to the predeterminated level digital display, data moved to reposition, and more new data, continue to end interference time of next round read/write.XXXX_RC_CNT is that the reference voltage of every layer of flash memory is replied counter, such as RVH1_RC_CNT, RVLm_RC_CNT etc.
[the 285th section] Figure 25 has shown the data of protecting, writing flash memory with strengthening.Find the physical block address of the data that newly write, such as using look-up table, step 794.When the needs Additional Protection, step 796, stripe cell is confirmed, and step 798 generates parity, step 802 from strip data.Preserve parity and it be connected step 804 with data.Then strip data is write physical block address, step 806.Embodiment and replacement embodiment
[the 286th section] inventor has planned several other embodiments.Such as, many codings of data qualifier bit, other mode fields, pointer etc. are possible.The data type mode bit is the former positions in entry not necessarily.Entry can with other forms in entry interrelate, such as the independent form that is used for mark or significance bit.Temporary file can have various expansions, and new expansion can increase in search directory.By well-known program, such as word processor and web browser, the temporary file of generation has well-known file extent, but can add at any time additional extension.These extra file expansions can be upgraded in the control software that increases to SSS controller 40 by firmware.
The large I of the DRAM impact damper that [the 287th section] each part of ETL is used is determined by the firmware of SSD controller.Driven terms of mechanics, each part of ETL can be regulated according to user's use or right of priority automatic or manual by controller firmware.Due to the limited size of DRAM impact damper 20, the function that is not all ETL can be used simultaneously.Each function of ETL is all applicable to actual working environment.Controller can be adjusted the shared size of each ETL, in order to make the DRAM impact damper obtain largest optimization.Can regularly transfer in capable accommodation according to the use pattern of device.
[the 288th section] is for the TLC flash memory device, the DRAM impact damper can be used non-volatile random access memory (NVRAM), such as phase transition storage (PCM), ferroelectric random storer (FRAM), magnetoresistive RAM (MRAM), memistor, phase-change random access memory (PRAM), resistance random access memory (RRAM), racing track storer and nanometer random access memory (NRAM) etc., replace.The advantage of phase transition storage is: all forms that ETL supports etc. can be preserved (need not put into flash memory) therein, and flash memory specific data (writing buffer memory etc. such as data) is even also can preserve when power-off, therefore, even also no longer need the standby power supply circuit when power supply cuts off suddenly.Temporary file and mapping table 140, reading buffer memory and mapping table 151 can be when power-off or arbitrarily abandon during the initialization of next round power initiation.Be different from MLC, the shortcoming of non-volatile random access memory is cost.For MLC, shortcoming is the restriction of the slow and write/erase number of times of speed.By distributing the part only contain through the TLC of the powerful page of programming, can obtain MLC from TLC.Some functions of ETL can be carried out in the static RAM (SRAM) in intelligent storage exchange control unit 40.
[the 289th section] is in the ETL flash memory device, the DRAM impact damper is available combination also, such as the DRAM+SRAM(static RAM), the DRAM++MLC(multilevel-cell), the DRAM+PCRAM(phase-change random access memory), the DRAM+MRAM(magnetoresistive RAM) etc., substitute.When using the combination of dynamic random storage buffering, during such as the DRAM+ multilevel-cell, the function that ETL supports manages in DRAM, and some of them are stored in multilevel-cell.Some data in the DRAM impact damper can abandon at last, can not move to temporary file of multilevel-cell etc., mapping table 140 during such as power-off, read buffer memory and mapping table 151.Form and the data that need to preserve when power-off such as piece scrub techniques table 164, page status table 162, S.M.A.R.T. data collector 170 etc., will use standby power supply to be stored to multilevel-cell when the power supply accident is closed.Another method of preserving relevant data in DRAMETL is that it is copied to multilevel-cell.If outage, effectively copying of ETL data can be kept in multilevel-cell.When starting power supply, those data of ETL can be transmitted back DRAM from multilevel-cell.Can record the quantity that can reduce copy data, thereby reduce a small amount of difference that multilevel-cell writes, revise clone method.
[the 290th section] DRAM+ multilevel-cell or DRAM+ single layer cell (SLC) and nonessential use single layer cell/multilevel-cell/three-layer unit dissimilar.On the contrary, by distributing the part only contain through the three-layer unit of the powerful page of programming, can obtain multilevel-cell from three-layer unit.By distributing multilevel-cell or a three-layer unit part that only contains through the powerful page of programming, can obtain single layer cell from multilevel-cell or three-layer unit.
[the 291st section] lasting counting described herein attempts to solve the persistent problem of non-volatile flash memory.Concentrated nonvolatile memory is arranged, such as using competitive counting to replace the magnetoresistive RAM of non-volatile flash memory, phase transition storage, resistance random access memory, memistor, nanometer random access memory etc.
[the 292nd section] super durable flash drives can and hard disk drive (HDD) associating, super durable flash drives is as buffer memory, hard disk drive is as storer.Super durable flash drives has overlength endurance, is more suitable for as buffer memory.This hybrid device can improve overall performance.Another kind of way of preserving relevant data in DRAMETL is that it is copied to hard disk drive.When outage, effectively copying of ETL data can be kept in hard disk drive.When switching on power, those data in ETL can be transmitted back DRAM from hard disk drive.Can record the quantity that can reduce copy data, thereby reduce a small amount of difference that hard disk drive writes, revise clone method.
The start image of [the 293rd section] operating system can be pre-loaded into the DRAM impact damper, in order to accelerate host-initiated.In case start-up routine finishes, discharge the DRAM impact damper and wait until subsequent normal operations.
[the 294th section] when main frame entered dormancy or standby mode, invalid DRAM impact damper must write flash memory.When the host subscriber withdrawed from, invalid DRAM impact damper can write flash memory.
The combination of [the 295th section] data writing is not limited to one page Unit one.Data splitting can be included into larger unit, such as, multipage and whole etc.
[the 296th section] is described to when the classification of host accessing data type: will compare from logical address and the more than one address realm of main frame, this relatively may only compare the part of logical address and the scope of expression address realm.Also can pass through to decompose the main frame data writing specified data type of specific format,
Such as FAT form or FDB form.Also can check the data layout that early stage main frame in order writes.With the FAT file system as an example.FDB/FAT is the metadata of FAT file system.The alternative document system such as LINUX, Apple OS and Android etc., have separately the metadata that oneself has different names, but character is suitable.
[the 297th section] each piece all can be divided into the multipage zone.Such as, a piece can have 16 pages, and 4 districts, each district have 4 pages.In this replaceable embodiment, some mappings are used for the district, but not independent page or piece.In addition, under special circumstances, can there be one page in each district.Although each district has a plurality of pages, district's pattern but not page-mode need map entry still less.
Can select troop or distinguish in the position that the logical sector address (LSA) of [the 298th section] main frame is higher.All entries in mapping table can be used for same district.When the area code of logical sector address was corresponding with the area code of all entries in mapping table, the LBA in logical sector address selected an entry in mapping table.Also can use and mix or the multi-level mapping table.Since the LBA scope of known FAT1/2 can dispense content data type position " 100 ".On mapping table, piece granularity or page-granular may be arranged.
The copying of [the 299th section] piece moved and to be not so good as page-map frequent, because violate in page-mode that the order of non-single layer cell storage writes the situation of rule and not as frequent in block mode.This has increased the persistence of flash memory system, has also promoted performance.
[the 300th section] mapping table can arrange in expanded address space, also can use greater than the actual address or the illegal address that are used for maximum address in address space.Can be by main frame sequence of pages reserved address, or can again plan the address location.Other embodiments, such as being used for data-center applications, the page or temporary file can be used as and just be usually used in the data processing, simplify controller function, but consume the flash memory persistence.Lasting persistence is standby can use DRAM impact damper 20 to replace flash memory 30 as lasting spare parts/exchange bufferings with the swap block district, and the over capacity of expansion is provided.In the situation that main frame provides arbitrarily closes compression function of compression function.In other embodiments, controller can be processed subscriber data file as pagefile, to simplify controller function.
Can there be a lot of variablees in [the 301st section] piece figure.ROM (read-only memory) (ROM) such as Electrically Erasable Read Only Memory (EEPROM) can be connected with controller or its part, and can be used for being diastema storage of processor storing firmware.This firmware also can be stored in main flash memory module.Host interface bus can be Serial Advanced Technology Attachment (SATA) bus, peripheral interconnection (PCIe) bus, standard flash memory (CF) bus or USB (universal serial bus) (USB), firmware 1394 buses, optical-fibre channel (FC) bus, the Thunderbolt etc. set up.Internal bus can use such as Serial Advanced Technology Attachment (SATA) bus, integrated device electronics (IDE) bus, peripheral interconnection (PCIe) bus, standard flash memory (CF) bus, USB (universal serial bus) (USB), secure digital (SD) bus, multimedia card (MMC) bus, firmware 1394 buses, optical-fibre channel (FC) bus, the various industry ethernets etc. set up.SCFD can comprise and only comprises single layer cell or multilevel-cell flash memory, or both combinations.
[the 302nd section] flash memory can be embedded on motherboard or SSD plate or on separate modular.Can increase capacitor, impact damper, resistor and other parts.The intelligent storage exchange control unit can be combined into an integral body with motherboard, or is arranged on separate board or module.Flash memory can combine with the intelligent storage exchange control unit, or combines with unprocessed non-volatile flash memory chip as monolithic devices or card module or plate.
[the 303rd section] uses multilayer director, and such as during the total regulator at controller arranges, the controller in can only memory transactions can be needed more simpler than individual layers controls such as consume equilibrium, bad block management, mapping again, buffer memory, power managements.Can only use more cheap hardware in memory controller, such as using controller 8051 processors, diastema storage of processor, intelligent storage task manager, rather than more powerful processor core are such as the senior order machine ARM-9 central processing unit kernel of simplifying.For application-specific, consider more powerful processor.
The flash memory blocks of [the 304th section] varying number and distribution can be connected on the intelligent storage interchanger.But not use LBA storage bus interfaces or general serial packet bus, other universal serial bus are such as synchronous double data rate (DDR), open NAND flash memory interface, Toggle NAND, difference string original data bus, legacy flash memory interface etc.
[the 305th section] mode logic is only the lead-in wire state being detected when the power connection, rather than the state of dedicated pin detected.The particular combination of lead-in wire state or order can be used for the start-up mode change.The multibus protocol chip can be furnished with the individual character lead-in wire that additional serial bus interface uses, and maybe can be furnished with the programmable register that is arranged on hub or interchanger pattern.
[the 306th section] task manager, controller, process, function can be carried out with various ways.Function and process can be programmed, and are carried out by central processing unit or other processors, or can carry out in specialized hardware, firmware or combination.Many divisions of function can be replaced.The intelligent storage exchange control unit can be hardware, maybe can comprise firmware, software or both combinations.
By using with the parity/ECC of many flash memories passage and the strip data section being deposited in polynary non-volatile, the reliability of whole system improves [the 307th section].Such as, the 9th flash memory dies can use together with flash memory interface.If one of eight flash memory dies run into serious read error, the parity of other eight flash memory dies is write the 9th flash memory dies, the excessive data protection is provided.But, use possibly the central processing unit engine with the DDR/SDRAM buffer memory, in order to satisfy the computing power requirement that complicated ECC/ parity is calculated and generated.Another benefit is, even flash memory blocks or flash memory module are impaired, data can be recovered, or the intelligent storage interchanger can start " fault restoration " or " automatic Reconstruction " program, insert a new flash memory module, and recover or rebuild the data of " loss " or " impaired ".The failure tolerant of whole system improves greatly.
The floating grid of [the 308th section] flashing storage unit is by adding electronics to programme.Flash memory is controlled the page and is write the electronics that inserts, in order to remain between two reference voltage levels.The bit line of NAND flash memory structures is connected to a string 32 unit, and each unit is connected to again 32 different word lines.After the unit data writing, writing and reading and can cause interference to this unit adjacent cells.This disturbs and will add the floating grid of electronics to this unit, or therefrom removes electronics.Cycle is grown and also can affect the electron amount of this unit floating grid.Due to the variation of electron amount in floating grid, output voltage level is also corresponding change when reading.If the variation of output voltage level exceeds the boundary of reference voltage, reading result is wrong so.
[the 309th section] can change wider or narrower data bus and flash memory dies, such as with 16 or 32 bit data passages.The inside and outside that can be used for the intelligent storage interchanger with the replaceable bus structure of nested or segmented bus.Can use two above internal buss in the intelligent storage interchanger, to increase operational throughput.External bus in available more complicated exchange optical fiber is replaced.
[the 310th section] available various ways is completed the data band, such as parity check sum ECC.Can resequence to packets of information according to being used for placing the data ordering of resequencing overlapping memory block.The intelligence interchanger can combine with other assemblies, also can be used as the unit chip.
[the 311st section] can increase extra ducts or temporary buffer and FIFO.Such as, the main frame FIFO in intelligent storage exchange control unit 40 can be the part of controller 40, also can be stored in impact damper RAM.All can provide the individual page impact damper in each passage.Can increase clock source.
[the 312nd section] encapsulation separately, monolithic or multi-disc encapsulation can comprise an above flash memory and/or the polynary passage of intelligent storage interchanger.Invention is not limited to the use of SCFD.SCFD can replace with any one non-volatile device with non-volatile flash memory and controller.
[the 313rd section] multilevel-cell formula flash memory device can be with four multilevel-cell flash memory dies that contain two panel data passages, but can use different arrangements to form other flash memory module, such as, four, eight or more polynary according to passage, or eight, 16 or layer unit sheet more the more.Flash memory device and passage can be lined up chain, shape or array-like.Such as, 4 flash memory devices can be used as a chain and are connected to the intelligent storage interchanger.The set of other sizes or partition scheme can be used for the different accesses of storer.
[the 314th section] main frame can be PC motherboard or other PC platforms, device for mobile communication, PDA(Personal Digital Assistant), digital camera, the tool of production or tester, composite set or other devices.Main frame main line or host apparatus interface can be SATA, PCIE, Thunderbolt, SD, USB, eMMC, iSSD or other host buses, and the inside main line of flash memory module can be PATA, hyperchannel SSD, multi-functional SD/MMC, standard flash memory (CF), USB or other parallel interfaces.Flash memory module can be the PCB of standard, or the multichip module of sealing in TSOP, BGA, LGA, COB, PIP, SIP, CSP, POP or other multi-discs encapsulation (MCP), also can comprise unprocessed NAND flash memory dies, perhaps unprocessed NAND flash memory dies can be the flash memory dies of separation or the non-volatile burst flash memory of other kinds.Internal bus can be shared wholly or in part, can be also the bus of separating.The SSD system can be with circuit board and other assemblies, such as LED pointer, electric capacity, resistance etc. use together.Can add power management at more than one layer.
[the 315th section] direction word is relative as high and low, upper and lower, top, bottom etc., can be along with variations such as the rotation of system or data, unexpected upsets.These words are used for tracing device, but are not to be absolute.
[the 316th section] non-volatile burst flash memory can be on the flash memory module of the controller that may contain encapsulation, also may the flash memory mould in the monolithic encapsulation on.The monolithic encapsulation can be integrated into PCBA, or directly is integrated on mainboard so that further simplification is installed, reduced production costs and reduce integral thickness.Flash memory dies also can use together with other implementing measures, comprises the open frame card.
[the 317th section] is not only intelligent storage exchange control unit 40 to be used for flash memory storage, can also increase additional functionality.Such as, music player can comprise the music controller that is stored in MP3 data in flash memory.Can add earphone socket on device, user's plugged earphone is listened to the music.Wireless microphone (such as the bluetooth microphone) can add to and connects wireless headset on device, but not uses earphone socket.Also can add the infrared ray microphone, such as IrDA.Also can add bluetooth transceiver for wireless mouse, PDA, keyboard, printer, digital camera, MP3 player or other wireless devices.Bluetooth transceiver can replace connector as initial connector.The Bluetooth adapter device can be furnished with connector, radio frequency (RF) transceiver, baseband controller, antenna, flash memory (EEPROM), voltage stabilizer, crystal, light emitting diode (LED), resistance, electric capacity and inductor.These assemblies can be arranged on PCB before wrapping into plastics or metal shell.
[the 318th section] size of data is such as sector, page piece etc. may be different.There are 512 bytes a sector, and a page can have 16 sectors and a piece can have 128 pages to can be used as illustration.
As a kind of selection, the data writing of ETL can be compressed one by one and is written into data as a units of pages by the flash memory controller and write in buffer memory [the 319th section].The packed data of main frame can be large scale, such as greater than stripe cell, can be also small size, such as less than a sector.Add data head, show the relation of data field main frame LBA.Separately packing list has marked the data that write in the cache bar tape cell and the LBA of data head deviation post from the main frame to data.Data write buffer memory can have the capacity that surpasses two stripe cell.Write full or reach time restriction when data write buffer memory, the stripe cell of selection will write buffer memory from data and move to flash memory.Data packing list has marked from main frame to the flash memory stripe cell and the LBA of data head deviation post.For covering the legacy data of main frame, if still being kept at data, packed data writes in buffer memory, can will move on packed data, more new data is added into data and writes buffer memory, upgrades compaction table, abandons legacy data.In addition, if packed data is kept in flash memory, compare new legacy data, and the generation incremental data shows its difference.Interpolation incremental data and data head thereof enter data and write buffer memory.Legacy data position before the new data head also comprises.Compaction table has marked the LBA of incremental data position.
The background of [the 320th section] invention part can comprise the background information of inventive problem or environment, but not describes by other means prior art.Therefore the contained material of background parts does not represent that the applicant admits former technology.
[the 321st section] any method described herein or program are carried out by machine or computer, and design is carried out by machine, computer or other devices, are not only by people's independent execution under the condition auxiliary without machine.The actual result that produces can comprise report, perhaps by other displaying contents of the display device such as computer monitor, projection arrangement, audio frequency generating apparatus and related media device, also can comprise the hard copy printout data that machine generates.Computer is another actual result to the control of other machines.
[the 322nd section] above-mentioned advantage and benefit are not suitable for all embodiments of invention.When word " refers to " that when the statement part occurred, the applicant planned the statement part and is included into the 6th section, 35USC the 112nd chapter.Usually word " refers to " have before the mark of an above word.Word " refers to " that word before is to want to reduce the mark that the statement part is quoted, but not thinks the expression structure restriction.The statement of this kind finger+function intends containing the structure of execution function described herein and structural equivalents thereof, and equivalent structure.Such as, although nail is different with screw structural, they all fulfil fastening function, therefore have equivalent structure.Do not use the statement that word " refers to " will can not be included into the 6th section, 35USC the 112nd chapter.Signal is typical electronic signal, but can be visual signal, such as the transmission of available fiber line.
[the 323rd section] above-mentioned purpose of the description of contrive equipment having been expressed illustration and explanation.Be not to want detailedly, maybe invention be limited in the precise forms of announcement.According to above-mentioned instruction, many modifications and variations may be arranged.This paper is intended that invention scope and is not subjected to the restriction of this detailed description, and is subjected to the restriction of appended statement.
Claims (21)
1. super durable flash drives comprises:
A host interface from the read-write of main frame Receiving Host;
Dynamic random storage (DRAM) impact damper that is used for the data storage;
A flash memory that is used for storage save data when outage, the erasable and page of the piece of this flash memory can write;
A main frame that receives according to host interface reads and writes and makes a response, thus the controller that flash memory access and DRAM buffer access are controlled, and this controller writes the DRAM impact damper with host data;
A durable conversion layer (ETL) of carrying out in the DRAM impact damper, this conversion layer is controlled by the controller that interim storage and the consume of minimizing flash memory are provided;
One is kept in the DRAM impact damper and writes buffer memory by the data of controller management;
One is used for the Redundant Array of Independent Disks that data distribute in DRAM, this structure writes new data by several flash memory passages; This structure is managed by controller; With the backup battery of electric power was provided for DRAM buffer, flash memory and controller in when outage; This backup battery has enough capacity, can make controller according to the requirement of backup rules with the data Replica of durable conversion layer in flash memory.
2. super durable flash drives according to claim 1, wherein durable conversion layer (ETL) exists
Carry out in the DRAM impact damper, it comprises:
Portion is stored in the DRAM impact damper and by the page-map table of controller access, this page-map table has the selected entry of host logical address;
Portion is stored in the DRAM impact damper, by the polynary sub-sector map of controller access, the polynary sector entry that every one's share of expenses for a joint undertaking sector map is selected by sector number in a page forms;
Sector entry in this table is comprised of following part:
" partly-position, sector " refers to that entry is the sector entry of main frame partial data, and entry is the part sector entry of host machine part data;
" page pointer " is used to specify the page location in the DRAM impact damper of storing complete sector data or part sector data;
" sector identifier " when entry is the complete sector entry, is used for the sector in the identification page location;
When entry is part sector entry, be used for " byte offset " of start byte position in the identification page location, and " length " that indicates part sector data length;
Wherein complete magnetic region entry and part magnetic region entry are stored in polynary sub-sector map;
Be stored in the DRAM impact damper and by the data of controller access; Every page of stripe cell part page data that includes complete page data or grouping wherein;
In the data data writing buffer memory that its middle controller permission main frame will be stored, then according to a rule, stripe cell is write in flash memory.
3. super durable flash drives according to claim 2, wherein have entry in mapping table, and it comprises:
" data qualifier bit " refers to the data type of storing for the logical address that entry is selected;
When the full page host data is stored in DRAM, or when the full page host data is stored in flash memory, be used to specify therein " pointer " of position, wherein when host data was the part page data, pointer specified in the mapping table position that is used for storing sub-sector in polynary sub-sector map;
Wherein data qualifier bit refers to the data type selected from the group that comprises following content:
A file allocation table (FAT) entry;
A file description block (FDB) entry;
One creates, data is exchanged to from the main frame primary memory pagefile of super durable flash drives by the host stores manager;
One in FAT entry (temporary file that indication is created by the main frame executive routine) by the temporary file of file extent sign, this temporary file can be wiped when power-off/power failure; With a user file, be used to the host subscriber to store user data or request for data;
Its middle controller allows user file is copied to flash memory, but does not allow temporary file is write flash memory, like this, by stoping, temporary file is write flash memory, can reduce the flash memory consume.
4. super durable flash drives according to claim 1, wherein durable conversion layer (ETL) is carried out in the DRAM impact damper, and it further comprises:
A bad block management device: the piece in erase flash memory, when generating an erase block, this manager starts:
" counting " refers to the quantity of not wiping the position in page in this erase block is added up;
When the quantity of not wiping the position surpasses low threshold value, but when being no more than higher thresholds, this page marker is the protection page, and increases to the quantity of the error correcting code (ECC) of this protection page stores;
" page marks " refer to start when the quantity of not wiping the position surpasses higher thresholds, be the bad page with page marks, and the not activity of storage host data therein;
" repetition " refers to counting mode and the page marks mode of all pages in the repetition erase block;
" bad page count " is used for calculating the bad page quantity of erase block;
" piece mark " refers to that what start is labeled as bad piece with erase block, and all not activities of storage host data in any page of bad piece when erase block has many bad pages that surpasses block threshold value.
5. super durable flash drives according to claim 1, wherein durable conversion layer (ETL) is carried out in the DRAM impact damper, and it further comprises:
One be stored in the DRAM impact damper, by the data input buffer of controller access;
Article one, the series connection compressor circuit that comprises compression main frame writing mode, packed data interpolation data head mode, renewal compressing mapping table mode;
Its middle controller also comprises an adaptive compression algorithm (select appropriate algorithm and compress data writing according to the data type that arranges);
Like this, by reducing the size of data writing, make the amount of writing of flash memory still less, in order to extend the persistence of flash memory.
6. super durable flash drives according to claim 1, wherein durable conversion layer (ETL) is carried out in the DRAM impact damper, and it further comprises:
Collect the S.M.A.R.T. function of flash memory device health and fitness information, wherein the quality guarantee of flash memory device is to write quantity and definite according to total main frame that the client buys the time limit or flash drives.
7. a durable conversion layer (ETL) method can increase the persistence of the flash memory with shorter erase cycle life-span, and the method comprises:
Read or write when making a response what main frame received, control the access to flash memory and dynamic random storage (DRAM) impact damper, and write host data by controller to the DRAM impact damper;
Create ETL in the DRAM impact damper that controller is controlled, and use this ETL that interim storage is provided, to reduce the flash memory loss;
Distributed data in the DRAM impact damper forms therein the Redundant Array of Independent Disks structure that data distribute, and writes new data by several passages of flash memory, and the RAID structure is by controller management;
Usage data is divided manager and is confirmed that data type is non-ephemeral data type or is the ephemeral data type; And use backup battery to be DRAM impact damper and flash memory and controller power supply when outage, backup battery has enough capacity, makes controller the non-ephemeral data in durable conversion layer to be copied in flash memory according to a rule.
8. durable conversion layer according to claim 7 (ETL) method further comprises:
The data of using controller management to be stored in the DRAM impact damper write buffer memory;
Write the whole page data by the ETL storage of the DRAM impact damper that mates the appointment of entry pointer;
When host data is used for the part page of flash memory:
Create or locate the sub-sector map that is mated the appointment of entry pointer by mapping table;
For each full sector data of main frame, upgrade the entry of sub-sector map, indication is stored in full sectors type and the full sector pointers in the DRAM impact damper;
For the part sector data of main frame, upgrade the entry in sub-sector map, indication storage area sector, its length and start byte displacement;
Sub-sector map has the entry of full sector and part sector;
Wherein every page of stripe cell comprises the part page data of whole page data or grouping;
Its middle controller allows that the main frame data writing is stored in data and writes in buffer memory, then according to a rule, stripe cell is write in flash memory.
9. durable conversion layer according to claim 7 (ETL) method, wherein ETL carries out in the DRAM impact damper, and the method further comprises:
Use compression manager to control various functions;
The data write cache that management DRAM stores in impact damper;
Write first data from main frame, and data writing is write the data head of buffer memory beginning;
Write a new data from main frame, and data are write the data head on previous data side in buffer memory;
Wherein, when the more new writen data of accepting from main frame, and legacy data is when being in data and writing buffer area, and controller will be wiped legacy data and data head thereof, and after invalid data is moved to legacy data, then additional more new data and data head thereof;
Wherein, when invalid data size surpasses stripe unit size, and data write buffer memory completely the time, and controller can write flash memory with stripe unit size.
10. durable conversion layer according to claim 7 (ETL) method, wherein ETL carries out in the DRAM impact damper, and the method further comprises:
The data of using controller management to deposit the DRAM impact damper in are write buffer memory;
Acceptance is from Initial master value of writing of main frame;
Host logical address distributes the data type figure place of indication FAT type in file allocation table (FAT) address realm the time, and file allocation table (FAT) address realm is specified by the format manipulation of storage FAT entry; Host logical address distributes the data type figure place of indication FDB type in file description block (FDB) address realm the time, and file description block (FDB) address realm is specified by the operating system of storage FDB entry;
If the data type figure place is not made otherwise allocated, so the data type figure place of indicating user file type is distributed;
Write in new entry being assigned to the data type figure place that Initial master writes, new entry is arranged in the mapping table with pointer;
The Initial master data that are received from initializes host are write a certain position of ETL of the DRAM impact damper of pointed;
Storage data in the DRAM impact damper are moved in flash memory, so that the storage data possess the data type figure place of indicating user file type;
During power-off/power failure, the storage data in DRAM impact damper ETL are moved in flash memory, so that data possess the data type figure place of indication file allocation table or file data buffer zone type, can reduce like this wearing and tearing of flash memory.
11. durable conversion layer according to claim 7 (ETL) method further comprises:
Create data and write buffer area in the DRAM impact damper;
Record the access frequency of each logical block addresses;
Wherein, access frequency is during greater than the predefine value, and logical block addresses will be classified as " frequent access ", otherwise, be " non-frequent access " so;
When accessed logical block addresses is frequent access, data are deposited to frequent access buffer district;
When accessed logical block addresses is non-frequent access, data are deposited to non-frequent access buffer district;
Wherein, non-frequent access buffer district can preferentially be write flash memory, and preferentially or non-frequent access logic block address access frequent by other covers.
12. durable conversion layer according to claim 7 (ETL) method further comprises:
The data of using controller management to deposit the DRAM impact damper in are write buffer memory;
Use controller management from the logical block addresses of importing into of main frame;
In the problem that do not line up that checks under the power connection state between file system address and the flash memory page, determine required offset in alignment amount;
Add side-play amount in logical block addresses to importing into, will import logical block addresses into and snap to the flash memory page.
13. durable conversion layer according to claim 7 (ETL) method further comprises:
The data of using controller management to deposit the DRAM impact damper in are write buffer memory;
The operating series compressor circuit, the compression main frame writes, and data head is added into packed data, and upgrades compressing mapping table;
Wherein, controller further comprises various compression algorithms;
Select appropriate algorithm, according to data set type compression data writing;
When data set has identical data set, use compressing mapping table, point to identical compressed data set;
When data set has similar data set, use compressing mapping table, point to identical compressed data set, and use the pointed incremental data;
When data set does not have similar data set, will be the compressing mapping table move to the DRAM impact damper, and change the pointer in compressing mapping table;
When size of data does not reduce, keep raw data after compression;
Like this, the reducing of the size of data writing, the data that cause writing flash memory tail off, thereby improve the flash memory durability.
14. durable conversion layer according to claim 7 (ETL) method further comprises:
The data of using controller management to deposit the DRAM impact damper in read buffer memory;
Receive read requests from main frame, obtain logical block addresses;
Reading out data from flash memory after not being checked through read error, sends data to main frame;
When being checked through read error, method one activates, and execution error correction code (ECC) checks, generates a series of error codes;
When number of bit errors was less than first threshold value, method two activated, and used first order error correcting method and corrected error code, then will revise data and be sent to main frame;
Number of bit errors is more than first threshold value and when being less than second threshold value, and method three activates, and uses first order error correcting method and corrects error code, then will revise data and be sent to main frame, if before there is no generation, generates the software error correction code;
Number of bit errors is more than second threshold value and also can use ECC and correct the time, and method four activates, and uses first order error correcting method and corrects error code, then will revise data and be sent to main frame, if before there is no generation, generates the software error correction code;
Number of bit errors is during higher than the correction limit of first order error correcting, and method five activates, and the software error correction code that generates before using is corrected error code, then will revise data and be sent to main frame;
Number of bit errors is higher than the correction limit of first order error correcting, and when the application software error correcting code can't be corrected, method six activates, abandon a segment data, parity checking segment data and other segment data used in the segment data group are rebuild this segment data, then will revise data and be sent to main frame;
Number of bit errors is higher than the correction limit of first order error correcting, and when the application software error correcting code can't be corrected, and the segmentation parity data be can't use the time, and method seven activates, and carries out the reference voltage handoff routines, then sends and has revised data to main frame.
15. durable conversion layer according to claim 7 (ETL) method further comprises:
The data of using controller management to deposit the DRAM buffer zone in read buffer memory;
Receive read requests from main frame, obtain logical block addresses;
Reading out data from flash memory after not being checked through read error, sends data to main frame;
When being checked through read error, method one activates, and execution error correction code (ECC) checks, generates error code;
When number of bit errors was less than a threshold value, method two activated, and used first order error correcting method and corrected error code, then will revise data and be sent to main frame;
Number of bit errors is more than threshold value and also can use ECC and correct the time, method three activates, use first order error correcting method and correct error code, then will revise data and be sent to main frame, reorientate the old physical block of flash memory data to the new physical block position, this old physical block of mark is " abandoning ";
When number of bit errors is corrected limit higher than first of first order error correcting, method four activates, abandon a segment data, parity checking segment data and other segment data used in the segment data group are rebuild this segment data, then will revise data and be sent to main frame, reorientate the old physical block of flash memory data to the new physical block position, this old physical block of mark is " abandoning ";
Number of bit errors is corrected limit higher than first of first order error correcting, and the segmentation parity data when method five activates, carries out the reference voltage handoff routines can't use the time, then will revise data and be sent to main frame.
16. durable conversion layer according to claim 7 (ETL) method further comprises:
The data of using controller management to deposit the DRAM buffer zone in read buffer memory;
When number of bit errors was corrected limit higher than first of first order error correcting, changing method activated, and adjusts in the following manner the reference voltage grade:
Different register values are write in the flash memory dies register, to read the data in flash memory dies;
Wherein, reference voltage grade or higher or lower than the default reference electric pressure;
Use trained reference voltage to read the interior data of flash memory dies;
After using trained reference voltage grade and first order error correcting successfully to read the interior data of flash memory dies, will revise data and be sent to main frame, storage adjusted reference voltage grade is for later on;
After using trained reference voltage grade and first order error correcting successfully not to read the interior data of flash memory dies, use the previous software error correction code that generates, to revise data and be sent to main frame, storage adjusted reference voltage grade is for later on;
When using trained reference voltage grade, first order error correcting and the previous software error correction code reading out data failure that generates, calculate new adjustment reference voltage and use this reference voltage grade in new iteration;
And all predefine reference voltage grades all the failure after, the report gross error, do not send and revised data; Like this, when number of bit errors is corrected limit higher than first of first order error correcting, adjust the reference voltage grade, thereby improve the flash memory durability.
17. durable conversion layer according to claim 7 (ETL) method further comprises:
When a block in flash memory has been wiped free of, increases erase blocks and smear the block of writing in frequency table and smear and write number of times;
Read erase blocks page status table, have polynary page entries, each page entries to store the state of the page in erase blocks in the page status table, state comprises bad page or good page indication;
Each page in erase blocks reads the page entries on the page from the page status table;
When the page status in the page status table is shown as " bad ", process lower one page;
When the page status in the page status table is shown as " good ", calculates and do not wipe the bit number on this page;
When not wiping the bit number over first threshold, the change page status shows bad page in page entries, increase bad number of pages;
Do not wipe the bit number and be between first threshold and Second Threshold, and the page status in the page status table shows that when needing error correcting code (ECC) protection, processing is one page down;
Do not wipe the bit number and be between first threshold and Second Threshold, and the page status in the page status table shows when not needing the ECC protection, the page status in change page status table, showing needs the ECC protection, increases ECC protection page number;
When bad number of pages of erase blocks surpasses the 3rd threshold value, show that erase blocks is not bad piece, do not write new data to erase blocks, like this, can wipe bad block by calculating bad number of pages of erase blocks identification, and allow bad page to be present in piece, thereby improve the flash memory durability.
18. a durable conversion layer (ETL) method can increase the persistence of the flash memory with shorter erase cycle life-span, the method comprises:
Create durable conversion layer (ETL) in dynamic random storage (DRAM) impact damper by controller management, use this conversion layer interim storage is provided, reduce flash memory consume degree with this;
Create spare area/exchange area in the DRAM impact damper;
Operation control is used the spare area/exchange area in the DRAM impact damper, merges valid data and new data in flash memory, and generates pooled data;
And pooled data is write in flash memory;
Like this, controller will use in the dynamic random memory buffer standby/function of exchange, and the function in non-flash memory.
19. durable conversion layer according to claim 18 (ETL) method further comprises:
For providing wear leveling, the block in flash memory controls;
When controller needed the flash memory block to write data by the spare area/exchange area in the DRAM buffer zone, test zone bulk state/smear and write frequency table was selected to smear to write the minimum block of number of times from the block list that is in the sky bulk state;
Can not select to smear and write the highest block of number of times.
20. durable conversion layer according to claim 18 (ETL) method further comprises:
For providing wear leveling, the block in flash memory controls;
Device free and the highest smearing when writing number of times and reaching predetermined threshold, utilize block state/smear and write frequency table, select targetedly one group have minimum smear write number of times with the highest empty piece of writing number of times of smearing that has of block and same quantity, by the spare area/exchange area in the DRAM buffer zone, from minimum smear to write copy data to the highest smearing the number of times block and write the number of times block, then wipe minimum smearing and write the number of times block;
Recycle minimum smearing and write the number of times block;
Each block is smeared the increment of writing number of times to be minimized.
21. durable conversion layer according to claim 18 (ETL) method further comprises:
Create the page status table in the DRAM buffer zone;
Operation control, the state of each the flash memory page of page status table record in use DRAM impact damper;
After wiping a block, the state of each page in this block is set to " blank page ";
After writing a page, the state of the change page used;
When host data writes same logical page address, data are write the new flash memory page, with the old page
State is set to " wiping/ cut out the page ";
Receive when cutting out order from main frame, the respective page state is set to " wiping/ cut out the page ";
When the page is identified as bad page, page status is set is " bad page ";
The page that in the process of clearing and retrieving station, will not be shown as " wiping/ cut out the page " moves in new block;
Create spare area/exchange area in the DRAM impact damper;
Operation control, the spare area in use DRAM impact damper/exchange area merges valid data and the new data in flash memory, and generates pooled data;
Wherein, can be checked through the state of each page in target block from the page status table;
Wherein, the page status of valid data page is shown as " having used the page "; Page status is not shown as " bad page ", " blank page " or " having cut out the page ";
Pooled data is write flash memory;
Like this, controller will use in the DRAM impact damper standby/function of exchange, and the function in non-flash memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/540,569 US8959280B2 (en) | 2008-06-18 | 2012-07-02 | Super-endurance solid-state drive with endurance translation layer (ETL) and diversion of temp files for reduced flash wear |
| US13/540,569 | 2012-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103176752A true CN103176752A (en) | 2013-06-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013100690727A Pending CN103176752A (en) | 2012-07-02 | 2013-03-05 | Super-endurance solid-state drive with Endurance Translation Layer (ETL) and diversion of temp files for reduced Flash wear |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN103176752A (en) |
| DE (1) | DE102013106242A1 (en) |
| TW (1) | TW201403318A (en) |
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| DE102013106242A1 (en) | 2014-04-17 |
| TW201403318A (en) | 2014-01-16 |
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